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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-23 18:56:25 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-23 18:56:25 -0800 |
| commit | 11e50c0e9ecec6439d44064a0e1a016dc2b3188b (patch) | |
| tree | 09864e1567931a57399d2feeac48ec6aa581334b | |
| parent | f180dba753c9f4bfb3b89575b0d224c73a1e8897 (diff) | |
| download | yosys-11e50c0e9ecec6439d44064a0e1a016dc2b3188b.tar.gz yosys-11e50c0e9ecec6439d44064a0e1a016dc2b3188b.tar.bz2 yosys-11e50c0e9ecec6439d44064a0e1a016dc2b3188b.zip | |
Test for (* keep *)-ed abc9_box_id
| -rw-r--r-- | tests/simple_abc9/abc9.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index ee01ab5dc..52ccb3e1d 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -291,3 +291,19 @@ module abc9_test035(input clk, d, output reg [1:0] q); always @(posedge clk) q[0] <= d; always @(negedge clk) q[1] <= q[0]; endmodule + +module abc9_test036(input A, B, S, output [1:0] O); + (* keep *) + MUXF8 m ( + .I0(I0), + .I1(I1), + .O(O[0]), + .S(S) + ); + MUXF8 m2 ( + .I0(I0), + .I1(I1), + .O(O[1]), + .S(S) + ); +endmodule |