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* techmap: Replace pseudo-private member usage with the range accessor function...Alberto Gonzalez2020-05-141-3/+3
* techmap: sort celltypeMap as it determines techmap orderEddie Hung2020-05-141-1/+5
* Replace `std::set`s using custom comparators with `pool`.Alberto Gonzalez2020-05-141-4/+4
* techmap: prefix special wires with backslash for use as IdStringEddie Hung2020-05-143-12/+14
* Further clean up `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-5/+6
* Use `emplace()` for more efficient insertion into various `dict`s.Alberto Gonzalez2020-05-141-8/+8
* Build constant bits directly rather than constructing an object and copying i...Alberto Gonzalez2020-05-141-2/+5
* Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.Alberto Gonzalez2020-05-141-2/+2
* Use `emplace()` rather than `insert()`.Alberto Gonzalez2020-05-141-1/+1
* Clean up pseudo-private member usage and ensure range iteration uses referenc...Alberto Gonzalez2020-05-141-17/+17
* Clean up extraneous buffer.Alberto Gonzalez2020-05-141-5/+2
* Replace `std::map` with `dict` for `unique_bit_id`.Alberto Gonzalez2020-05-141-1/+1
* Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and `c...Alberto Gonzalez2020-05-141-3/+3
* Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and `outb...Alberto Gonzalez2020-05-141-3/+3
* Replace `std::map` with `dict` for `TechmapWires` type.Alberto Gonzalez2020-05-141-1/+1
* Replace `std::map` with `dict` for `celltypeMap`.Alberto Gonzalez2020-05-141-3/+3
* Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.Alberto Gonzalez2020-05-141-4/+4
* Replace `std::map` with `dict` for `positional_ports`.Alberto Gonzalez2020-05-141-1/+1
* Add specialized `hash()` for type `dict` and use a `dict` instead of a `std::...Alberto Gonzalez2020-05-143-10/+25
* Replace `std::map` with `dict` for `simplemap_mappers`.Alberto Gonzalez2020-05-143-5/+5
* Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-10/+10
* Replace `std::string` and `RTLIL::IdString` with `IdString` in `passes/techma...Alberto Gonzalez2020-05-141-21/+21
* Do not modify design modules while iterating over `modules()`.Alberto Gonzalez2020-05-141-1/+4
* Clean up pseudo-private member usage, superfluous `std::vector` instantiation...Alberto Gonzalez2020-05-141-76/+70
* Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-057-31/+34
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| * frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-047-31/+34
* | Merge pull request #2012 from whitequark/fix-wasi-abc-buildwhitequark2020-05-051-3/+3
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| * | Update ABC to include WASI support fixes.whitequark2020-05-021-1/+1
| * | Fix WASI builds with abc enabled.whitequark2020-05-011-2/+2
* | | Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_WEddie Hung2020-05-053-11/+34
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| * | | synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-043-11/+34
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* | | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-053-2/+22
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| * | | verilog: set src attribute for primitivesEddie Hung2020-05-042-2/+6
| * | | tests: add tests for primitives' srcEddie Hung2020-05-041-0/+16
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* | | Merge pull request #2023 from YosysHQ/eddie/specify_srcEddie Hung2020-05-052-18/+26
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| * | verilog: fix specify src attributeEddie Hung2020-05-042-18/+26
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* | Merge pull request #1996 from boqwxp/rtlil_source_locationsEddie Hung2020-05-041-13/+13
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| * | frontend: Include complete source location instead of just `location.first_li...Alberto Gonzalez2020-05-011-13/+13
* | | Merge pull request #2000 from whitequark/log_error-trapwhitequark2020-05-032-3/+44
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| * | | kernel: Trap in `log_error()` when a debugger is attached.whitequark2020-05-032-3/+44
* | | | Merge pull request #2014 from YosysHQ/claire/fixoptaluClaire Wolf2020-05-032-7/+31
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| * | | | test: add test for #2014Eddie Hung2020-05-021-0/+12
| * | | | Fix the other "opt_expr -fine" bug introduced in 213a89558Claire Wolf2020-05-021-7/+19
* | | | | Merge pull request #2013 from YosysHQ/eddie/aiger_fixesEddie Hung2020-05-026-42/+101
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| * | | | abc9_ops: -reintegrate to be sensitive to start_offset tooEddie Hung2020-05-021-3/+5
| * | | | tests: aiger test for wire->start_offset != 0Eddie Hung2020-05-022-0/+41
| * | | | aiger: fixes for ports that have start_offset != 0Eddie Hung2020-05-023-39/+55
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* | | | Merge pull request #2010 from YosysHQ/claire/fixoptClaire Wolf2020-05-022-7/+29
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| * | | Add testcase for #2010Eddie Hung2020-05-011-0/+10
| * | | Fix "opt_expr -fine" bug introduced in 213a89558Claire Wolf2020-05-011-7/+19
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