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author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-20 21:57:23 +0000 |
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committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-14 20:06:54 +0000 |
commit | bd54d67ad4a24992c4161f12b2c8e42df2a65569 (patch) | |
tree | 82393d46c31ce64e212e699932bc71f192247362 | |
parent | 982562ff13b475ec96af6e12e0ad8fdec42f91b6 (diff) | |
download | yosys-bd54d67ad4a24992c4161f12b2c8e42df2a65569.tar.gz yosys-bd54d67ad4a24992c4161f12b2c8e42df2a65569.tar.bz2 yosys-bd54d67ad4a24992c4161f12b2c8e42df2a65569.zip |
Further clean up `passes/techmap/techmap.cc`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
-rw-r--r-- | passes/techmap/techmap.cc | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index d137365c2..898aceccd 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -568,7 +568,7 @@ struct TechmapWorker { IdString derived_name = tpl_name; RTLIL::Module *tpl = map->module(tpl_name); - dict<IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end()); + dict<IdString, RTLIL::Const> parameters(cell->parameters); if (tpl->get_blackbox_attribute(ignore_wb)) continue; @@ -782,16 +782,17 @@ struct TechmapWorker // do not register techmap_wrap modules with techmap_cache } else { std::pair<IdString, dict<IdString, RTLIL::Const>> key(tpl_name, parameters); - if (techmap_cache.count(key) > 0) { - tpl = techmap_cache[key]; + auto it = techmap_cache.find(key); + if (it != techmap_cache.end()) { + tpl = it->second; } else { if (parameters.size() != 0) { mkdebug.on(); - derived_name = tpl->derive(map, dict<IdString, RTLIL::Const>(parameters.begin(), parameters.end())); + derived_name = tpl->derive(map, parameters); tpl = map->module(derived_name); log_continue = true; } - techmap_cache[key] = tpl; + techmap_cache.emplace(std::move(key), tpl); } } |