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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-19 22:21:52 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-14 20:06:53 +0000 |
| commit | 64c16f8c1364bbe45bc17a54c29d70990efb45ad (patch) | |
| tree | e36715cd937c3aa3959a48ac4947fd25203b8f4f | |
| parent | 2fb4931e5be2c2a0c80ffbca73ad74ebb8c9032f (diff) | |
| download | yosys-64c16f8c1364bbe45bc17a54c29d70990efb45ad.tar.gz yosys-64c16f8c1364bbe45bc17a54c29d70990efb45ad.tar.bz2 yosys-64c16f8c1364bbe45bc17a54c29d70990efb45ad.zip | |
Replace `std::map` with `dict` for `positional_ports`.
| -rw-r--r-- | passes/techmap/techmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 9779ecae9..651f772c9 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -204,7 +204,7 @@ struct TechmapWorker design->select(module, m); } - std::map<IdString, IdString> positional_ports; + dict<IdString, IdString> positional_ports; dict<Wire*, IdString> temp_renamed_wires; pool<SigBit> autopurge_tpl_bits; |