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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-19 22:41:21 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-14 20:06:54 +0000 |
| commit | 6d64d768b07a027fff42515dbba4cdb6f060d17a (patch) | |
| tree | 51e03986ad55762f67f867d490e618069c8d405e | |
| parent | 5cb4ae46665574e721161d4eb38552f0938b9948 (diff) | |
| download | yosys-6d64d768b07a027fff42515dbba4cdb6f060d17a.tar.gz yosys-6d64d768b07a027fff42515dbba4cdb6f060d17a.tar.bz2 yosys-6d64d768b07a027fff42515dbba4cdb6f060d17a.zip | |
Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and `cellbits_to_tplbits`.
| -rw-r--r-- | passes/techmap/techmap.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 96508845d..b4df6142e 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -862,9 +862,9 @@ struct TechmapWorker techmap_do_cache[new_tpl] = true; tpl = new_tpl; - std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map; - std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap; - std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits; + dict<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map; + dict<RTLIL::SigBit, RTLIL::SigBit> port_connmap; + dict<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits; for (auto wire : tpl->wires().to_vector()) { |