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| author | Claire Wolf <clifford@clifford.at> | 2020-05-02 11:20:02 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-02 11:20:02 +0200 |
| commit | ca3fc3c882b9a454c48bee7d701fa5cb254ae671 (patch) | |
| tree | 3650eb235d6bb48b4bd0ac395d806074225ae0c5 | |
| parent | bbde2419420a86635baf2b730ebe58ed6edca5bb (diff) | |
| parent | 7f9ecddb7f868a083ace6c82f97d80c2dd72dd29 (diff) | |
| download | yosys-ca3fc3c882b9a454c48bee7d701fa5cb254ae671.tar.gz yosys-ca3fc3c882b9a454c48bee7d701fa5cb254ae671.tar.bz2 yosys-ca3fc3c882b9a454c48bee7d701fa5cb254ae671.zip | |
Merge pull request #2010 from YosysHQ/claire/fixopt
Fix "opt_expr -fine" bug introduced in 213a89558
| -rw-r--r-- | passes/opt/opt_expr.cc | 26 | ||||
| -rw-r--r-- | tests/opt/bug2010.ys | 10 |
2 files changed, 29 insertions, 7 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 2b35ace5e..3f664c8d1 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -682,25 +682,37 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); bool sub = cell->type == ID($sub); + int minsz = GetSize(sig_y); + minsz = std::min(minsz, GetSize(sig_a)); + minsz = std::min(minsz, GetSize(sig_b)); + int i; - for (i = 0; i < GetSize(sig_y); i++) { - RTLIL::SigBit b = sig_b.at(i, State::Sx); - RTLIL::SigBit a = sig_a.at(i, State::Sx); - if (b == State::S0 && a != State::Sx) + for (i = 0; i < minsz; i++) { + RTLIL::SigBit b = sig_b[i]; + RTLIL::SigBit a = sig_a[i]; + if (b == State::S0) module->connect(sig_y[i], a); else if (sub && b == State::S1 && a == State::S1) module->connect(sig_y[i], State::S0); - else if (!sub && a == State::S0 && b != State::Sx) + else if (!sub && a == State::S0) module->connect(sig_y[i], b); else break; } if (i > 0) { cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); - cell->setPort(ID::A, sig_a.extract_end(i)); - cell->setPort(ID::B, sig_b.extract_end(i)); + log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module)); + SigSpec new_a = sig_a.extract_end(i); + SigSpec new_b = sig_b.extract_end(i); + if (new_a.empty() && is_signed) + new_a = sig_a[i-1]; + if (new_b.empty() && is_signed) + new_b = sig_b[i-1]; + cell->setPort(ID::A, new_a); + cell->setPort(ID::B, new_b); cell->setPort(ID::Y, sig_y.extract_end(i)); cell->fixup_parameters(); did_something = true; diff --git a/tests/opt/bug2010.ys b/tests/opt/bug2010.ys new file mode 100644 index 000000000..cef820867 --- /dev/null +++ b/tests/opt/bug2010.ys @@ -0,0 +1,10 @@ +read_verilog <<EOT +module test ( + input signed [1:0] n, + output [3:0] dout +); + assign dout = n + 4'sd 4; +endmodule +EOT + +equiv_opt -assert opt -fine |