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authorEddie Hung <eddie@fpgeh.com>2020-05-04 10:21:47 -0700
committerEddie Hung <eddie@fpgeh.com>2020-05-04 10:21:47 -0700
commitad8e7878f6321b9c35ae41b651a7da9a733ce4be (patch)
tree1c1cdf3eb952ef875665540ce86dc2c474ac3e40
parent584780d776c92bc91731dbc2710dd8d9a624dc70 (diff)
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tests: add tests for primitives' src
-rw-r--r--tests/various/primitives.ys16
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/various/primitives.ys b/tests/various/primitives.ys
new file mode 100644
index 000000000..9307ca50f
--- /dev/null
+++ b/tests/various/primitives.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module top(input a, b, output [5:0] y);
+and (y[0], a, b);
+nand (y[1], a, b);
+or (y[2], a, b);
+nor (y[3], a, b);
+xor (y[4], a, b);
+xnor (y[5], a, b);
+endmodule
+EOT
+select -assert-count 1 t:$and a:src=<<EOT:2.4-2.17 %i
+select -assert-count 1 t:$and a:src=<<EOT:3.5-3.18 %i
+select -assert-count 1 t:$or a:src=<<EOT:4.3-4.16 %i
+select -assert-count 1 t:$or a:src=<<EOT:5.4-5.17 %i
+select -assert-count 1 t:$xor a:src=<<EOT:6.4-6.17 %i
+select -assert-count 1 t:$xor a:src=<<EOT:7.5-7.18 %i