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author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-20 05:59:00 +0000 |
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committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-14 20:06:54 +0000 |
commit | 982562ff13b475ec96af6e12e0ad8fdec42f91b6 (patch) | |
tree | 10b3356724d94fb6070f8af49849b3603733bc19 | |
parent | c658d9d59d98063fec463e17978a3e2f449f38de (diff) | |
download | yosys-982562ff13b475ec96af6e12e0ad8fdec42f91b6.tar.gz yosys-982562ff13b475ec96af6e12e0ad8fdec42f91b6.tar.bz2 yosys-982562ff13b475ec96af6e12e0ad8fdec42f91b6.zip |
Use `emplace()` for more efficient insertion into various `dict`s.
-rw-r--r-- | passes/techmap/techmap.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index da53e8448..d137365c2 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -117,7 +117,7 @@ struct TechmapWorker constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, log_id(connbits_map.at(bit).first), connbits_map.at(bit).second); } else { - connbits_map[bit] = std::pair<IdString, int>(conn.first, i); + connbits_map.emplace(bit, std::make_pair(conn.first, i)); constmap_info += stringf("|%s %d", log_id(conn.first), i); } } @@ -710,21 +710,21 @@ struct TechmapWorker } if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) - parameters[ID::_TECHMAP_CELLTYPE_] = RTLIL::unescape_id(cell->type); + parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type)); for (auto &conn : cell->connections()) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) { std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector(); for (auto &bit : v) bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0); - parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))] = RTLIL::SigSpec(v).as_const(); + parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); } if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) { std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector(); for (auto &bit : v) if (bit.wire != nullptr) bit = RTLIL::SigBit(RTLIL::State::Sx); - parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))] = RTLIL::SigSpec(v).as_const(); + parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); } if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) { auto sig = sigmap(conn.second); @@ -735,7 +735,7 @@ struct TechmapWorker value[i] = it->second; } } - parameters[stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))] = value; + parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value); } } @@ -773,7 +773,7 @@ struct TechmapWorker val = val >> 1; } } - parameters[stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))] = value; + parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value); } } @@ -882,8 +882,8 @@ struct TechmapWorker wire->port_id = 0; for (int i = 0; i < wire->width; i++) { - port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i); - port_connmap[RTLIL::SigBit(wire, i)] = RTLIL::SigBit(new_wire, i); + port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), RTLIL::SigBit(wire, i)); + port_connmap.emplace(RTLIL::SigBit(wire, i), RTLIL::SigBit(new_wire, i)); } } |