synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad

3 files changed, 34 insertions, 11 deletions

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index ab740ea0d..b9b236a0c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -30,6 +30,11 @@ struct SynthEcp5Pass : public ScriptPass
 {
 	SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
 
+	void on_register() YS_OVERRIDE
+	{
+		RTLIL::constpad["synth_ecp5.abc9.W"] = "300";
+	}
+
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -324,6 +329,14 @@ struct SynthEcp5Pass : public ScriptPass
 
 			if (abc9) {
 				run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
+				std::string abc9_opts;
+				if (nowidelut)
+					abc9_opts += " -maxlut 4";
+				std::string k = "synth_ecp5.abc9.W";
+				if (active_design && active_design->scratchpad.count(k))
+					abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+				else
+					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
 				if (nowidelut)
 					run("abc9 -maxlut 4 -W 200");
 				else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 9724b7dd5..2b211572d 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -29,6 +29,13 @@ struct SynthIce40Pass : public ScriptPass
 {
 	SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
 
+	void on_register() YS_OVERRIDE
+	{
+		RTLIL::constpad["synth_ice40.abc9.hx.W"] = "250";
+		RTLIL::constpad["synth_ice40.abc9.lp.W"] = "400";
+		RTLIL::constpad["synth_ice40.abc9.u.W"] = "750";
+	}
+
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -373,14 +380,15 @@ struct SynthIce40Pass : public ScriptPass
 			if (!noabc) {
 				if (abc9) {
 					run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
-					int wire_delay;
-					if (device_opt == "lp")
-						wire_delay = 400;
-					else if (device_opt == "u")
-						wire_delay = 750;
-					else
-						wire_delay = 250;
-					run(stringf("abc9 -W %d", wire_delay));
+					std::string abc9_opts;
+					std::string k = "synth_ice40.abc9.W";
+					if (active_design && active_design->scratchpad.count(k))
+						abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+					else {
+						k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str());
+						abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
+					}
+					run("abc9 " + abc9_opts);
 				}
 				else
 					run("abc -dress -lut 4", "(skip if -noabc)");
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 1c190d37e..229ffcb3d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -619,11 +619,13 @@ struct SynthXilinxPass : public ScriptPass
 				run("techmap " + techmap_args);
 				run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
 				std::string abc9_opts;
-				auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
-				if (active_design->scratchpad.count(k))
+				std::string k = "synth_xilinx.abc9.W";
+				if (active_design && active_design->scratchpad.count(k))
 					abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
-				else
+				else {
+					k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
 					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
+				}
 				if (nowidelut)
 					abc9_opts += stringf(" -maxlut %d", lut_size);
 				if (dff_mode)