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* Bump versiongithub-actions[bot]2021-11-011-1/+1
* Merge pull request #3066 from YosysHQ/claire/verific_gclkClaire Xen2021-10-311-12/+67
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| * Fix verific gclk handling for async-load FFsClaire Xenia Wolf2021-10-311-12/+67
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* Bump versiongithub-actions[bot]2021-10-301-1/+1
* Add missing items in CHANGELOGMiodrag Milanovic2021-10-291-0/+6
* Update command reference part of manualMiodrag Milanovic2021-10-291-340/+1444
* Bump versiongithub-actions[bot]2021-10-281-1/+1
* Merge pull request #3063 from YosysHQ/micko/verific_aldffMiodrag Milanović2021-10-272-8/+1
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| * Enable async load dff emit by default in VerificMiodrag Milanovic2021-10-271-1/+1
| * Revert "Compile option for enabling async load verific support"Miodrag Milanovic2021-10-272-8/+1
* | ecp5: Add support for mapping aldff.Marcelina Kościelnicka2021-10-272-13/+13
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* proc_dff: Emit $aldff.Marcelina Kościelnicka2021-10-271-32/+7
* dfflegalize: Add tests for aldff lowering.Marcelina Kościelnicka2021-10-272-0/+240
* dfflegalize: Add tests targetting aldff.Marcelina Kościelnicka2021-10-277-7/+320
* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-2712-1053/+1137
* Bump versiongithub-actions[bot]2021-10-271-1/+1
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-2515-42/+397
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-255-28/+61
* Bump versiongithub-actions[bot]2021-10-261-1/+1
* Compile option for enabling async load verific supportMiodrag Milanovic2021-10-252-1/+8
* Bump versiongithub-actions[bot]2021-10-221-1/+1
* Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-212-6/+8
* Merge pull request #3057 from YosysHQ/claire/verific_latchesClaire Xen2021-10-211-4/+61
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| * Fix verific.cc PRIM_DLATCH handlingClaire Xenia Wolf2021-10-211-1/+7
| * Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}Claire Xenia Wolf2021-10-211-4/+55
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* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-212-63/+46
* Bump versiongithub-actions[bot]2021-10-211-1/+1
* If verific have vhdl lib it is required by other libsMiodrag Milanovic2021-10-201-0/+4
* Forgot to remove from main listMiodrag Milanovic2021-10-201-1/+1
* Option to disable verific VHDL supportMiodrag Milanovic2021-10-203-11/+50
* Bump versiongithub-actions[bot]2021-10-201-1/+1
* Fixed Verific parser error in ice40 cell libraryClaire Xenia Wolf2021-10-191-22/+62
* Merge pull request #3045 from galibert/masterMiodrag Milanović2021-10-191-0/+18
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| * CycloneV: Add (passthrough) support for cyclonev_oscillatorOlivier Galibert2021-10-171-1/+11
| * CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_pu...Olivier Galibert2021-10-171-0/+8
* | Fixes in vcdcd.pl for newer Perl versionsClaire Xenia Wolf2021-10-191-3/+3
* | Bump versiongithub-actions[bot]2021-10-181-1/+1
* | dfflegalize: remove redundant check for initialized dlatchPaul Annesley2021-10-171-4/+0
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* Bump versiongithub-actions[bot]2021-10-161-1/+1
* Merge pull request #3044 from YosysHQ/micko/verific_bufif1Claire Xen2021-10-151-2/+2
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| * Support PRIM_BUFIF1 primitiveMiodrag Milanovic2021-10-141-2/+2
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* Bump versiongithub-actions[bot]2021-10-121-1/+1
* Merge pull request #3039 from YosysHQ/claire/verific_aldffClaire Xen2021-10-112-1/+91
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| * Add Verific adffe/dffsre/aldffe FIXMEsClaire Xenia Wolf2021-10-111-0/+3
| * Fixes and add comments for open FIXME itemsClaire Xenia Wolf2021-10-081-1/+34
| * Add support for $aldff flip-flops to verific importerClaire Xenia Wolf2021-10-082-1/+55
* | Merge pull request #3040 from YosysHQ/micko/split_module_portsClaire Xen2021-10-111-0/+2
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| * | Split module ports, 20 per lineMiodrag Milanovic2021-10-091-0/+2
* | | Merge pull request #3041 from YosysHQ/mmicko/module_attrClaire Xen2021-10-111-0/+1
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| * | Import module attributes from VerificMiodrag Milanovic2021-10-101-0/+1
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