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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-20 12:37:22 +0200 |
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| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-20 12:37:22 +0200 |
| commit | 150ce305f9d51ec92380eb544e64af3770be5bdb (patch) | |
| tree | 480bc27693a91e2707b927be8a084cd51870e315 | |
| parent | 17269ae59bda6bcf60dbc9ad9d00afc69aa05499 (diff) | |
| download | yosys-150ce305f9d51ec92380eb544e64af3770be5bdb.tar.gz yosys-150ce305f9d51ec92380eb544e64af3770be5bdb.tar.bz2 yosys-150ce305f9d51ec92380eb544e64af3770be5bdb.zip | |
Forgot to remove from main list
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -500,7 +500,7 @@ endif ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib -VERIFIC_COMPONENTS ?= verilog vhdl database util containers hier_tree +VERIFIC_COMPONENTS ?= verilog database util containers hier_tree ifneq ($(DISABLE_VERIFIC_VHDL),1) VERIFIC_COMPONENTS += vhdl CXXFLAGS += -DVERIFIC_VHDL_SUPPORT |