diff options
| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-10-11 10:00:20 +0200 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-10-11 10:00:20 +0200 |
| commit | c8074769b081f26b2129910502dd9031acd01a2a (patch) | |
| tree | 01d437b1bccf3f4d5afa64b6df01b68212e9b669 | |
| parent | 34f1df84357e8d053b930970ff53e24f35e1b1b9 (diff) | |
| download | yosys-c8074769b081f26b2129910502dd9031acd01a2a.tar.gz yosys-c8074769b081f26b2129910502dd9031acd01a2a.tar.bz2 yosys-c8074769b081f26b2129910502dd9031acd01a2a.zip | |
Add Verific adffe/dffsre/aldffe FIXMEs
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| -rw-r--r-- | frontends/verific/verific.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 59fdda068..b8742e61d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1864,6 +1864,7 @@ Cell *VerificClocking::addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec s log_assert(gclk == false); log_assert(disable_sig == State::S0); + // FIXME: Adffe if (enable_sig != State::S1) sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); @@ -1875,6 +1876,7 @@ Cell *VerificClocking::addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::Si log_assert(gclk == false); log_assert(disable_sig == State::S0); + // FIXME: Dffsre if (enable_sig != State::S1) sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); @@ -1886,6 +1888,7 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL:: log_assert(gclk == false); log_assert(disable_sig == State::S0); + // FIXME: Aldffe if (enable_sig != State::S1) sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); |