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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-29 13:31:41 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-29 13:31:41 +0200 |
| commit | c0edfa878833f8c6a2a90c3466448783eae3fa28 (patch) | |
| tree | a202d663ba7296437db561c1e945668c08a05c74 | |
| parent | 55f07fe56f3bba9fea6b2ba3a446c5a199014136 (diff) | |
| download | yosys-c0edfa878833f8c6a2a90c3466448783eae3fa28.tar.gz yosys-c0edfa878833f8c6a2a90c3466448783eae3fa28.tar.bz2 yosys-c0edfa878833f8c6a2a90c3466448783eae3fa28.zip | |
Add missing items in CHANGELOG
| -rw-r--r-- | CHANGELOG | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -16,6 +16,12 @@ Yosys 0.10 .. Yosys 0.10-dev - Fixed an issue where connecting a slice covering the entirety of a signed signal to a cell input would cause a failed assertion + * Verific support + - Importer support for {PRIM,WIDE_OPER}_DFF + - Importer support for PRIM_BUFIF1 + - Option to use Verific without VHDL support + - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS} + Yosys 0.9 .. Yosys 0.10 -------------------------- |