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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-10-21 18:26:47 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-10-21 20:20:31 +0200 |
commit | 5cebf6a8efb4f1e9b836db76be0bb2a964932905 (patch) | |
tree | faac24ad43f2365ae39bf005c48e1e2e963290e2 | |
parent | 51d42cc917d66917439955616bc5a3842e5d6301 (diff) | |
download | yosys-5cebf6a8efb4f1e9b836db76be0bb2a964932905.tar.gz yosys-5cebf6a8efb4f1e9b836db76be0bb2a964932905.tar.bz2 yosys-5cebf6a8efb4f1e9b836db76be0bb2a964932905.zip |
Change implicit conversions from bool to Sig* to explicit.
Also fixes some completely broken code in extract_reduce.
-rw-r--r-- | kernel/rtlil.h | 4 | ||||
-rw-r--r-- | passes/techmap/extract_reduce.cc | 10 |
2 files changed, 8 insertions, 6 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e072d5bd1..96982d2d9 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -756,7 +756,7 @@ struct RTLIL::SigBit SigBit(); SigBit(RTLIL::State bit); - SigBit(bool bit); + explicit SigBit(bool bit); SigBit(RTLIL::Wire *wire); SigBit(RTLIL::Wire *wire, int offset); SigBit(const RTLIL::SigChunk &chunk); @@ -838,7 +838,7 @@ public: SigSpec(const std::vector<RTLIL::SigBit> &bits); SigSpec(const pool<RTLIL::SigBit> &bits); SigSpec(const std::set<RTLIL::SigBit> &bits); - SigSpec(bool bit); + explicit SigSpec(bool bit); SigSpec(RTLIL::SigSpec &&other) { width_ = other.width_; diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index b2da126ab..892e9a364 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -152,10 +152,10 @@ struct ExtractReducePass : public Pass log_assert(y.size() == 1); // Should only continue if there is one fanout back into a cell (not to a port) - if (sig_to_sink[y[0]].size() != 1) + if (sig_to_sink[y].size() != 1 || port_sigs.count(y)) break; - x = *sig_to_sink[y[0]].begin(); + x = *sig_to_sink[y].begin(); } sinks.insert(head_cell); @@ -183,13 +183,15 @@ struct ExtractReducePass : public Pass continue; } + auto xy = sigmap(x->getPort(ID::Y)); + //If this signal drives a port, add it to the sinks //(even though it may not be the end of a chain) - if(port_sigs.count(x) && !consumed_cells.count(x)) + if(port_sigs.count(xy) && !consumed_cells.count(x)) sinks.insert(x); //It's a match, search everything out from it - auto& next = sig_to_sink[x]; + auto& next = sig_to_sink[xy]; for(auto z : next) next_loads.insert(z); } |