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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-10 10:01:45 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-10 10:01:45 +0200 |
| commit | 93fbc9fba4400814a859a9d9bfb05b3b92500e31 (patch) | |
| tree | 1775fd2caeda1e86afd260ecf03a1b651c56cca3 | |
| parent | d8f6d7b18d23a588fc537f12aef3c4c8ddbe3418 (diff) | |
| download | yosys-93fbc9fba4400814a859a9d9bfb05b3b92500e31.tar.gz yosys-93fbc9fba4400814a859a9d9bfb05b3b92500e31.tar.bz2 yosys-93fbc9fba4400814a859a9d9bfb05b3b92500e31.zip | |
Import module attributes from Verific
| -rw-r--r-- | frontends/verific/verific.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 231003753..c03e16eb2 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -917,6 +917,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se } else { log("Importing module %s.\n", RTLIL::id2cstr(module->name)); } + import_attributes(module->attributes, nl, nl); SetIter si; MapIter mi, mi2; |