iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| \| *	Fix BTOR output tags syntax in writye_btor	Clifford Wolf	2019-03-23	1	-2/+1
\| \| *	Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals	Clifford Wolf	2019-03-23	2	-1/+9
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* \|	Cope with SHREG not having E port; Revert $pmux fine tune	Eddie Hung	2019-03-23	1	-4/+3
* \|	Add support for SHREGMAP+$mux, also fine tune $pmux	Eddie Hung	2019-03-22	1	-1/+24
* \|	Leftover printf	Eddie Hung	2019-03-22	1	-1/+0
* \|	Fixes for multibit	Eddie Hung	2019-03-22	1	-18/+38
* \|	Working for 1 bit	Eddie Hung	2019-03-22	1	-11/+49
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-22	7	-44/+115
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\| *	Merge pull request #889 from YosysHQ/clifford/fix888	Clifford Wolf	2019-03-22	1	-1/+10
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\| \| *	Fix mem2reg handling of memories with upto data ports, fixes #888	Clifford Wolf	2019-03-21	1	-1/+10
\| * \|	Merge pull request #890 from YosysHQ/clifford/fix887	Clifford Wolf	2019-03-22	1	-1/+26
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\| \| * \|	Trim init attributes when resizing FFs in "wreduce", fixes #887	Clifford Wolf	2019-03-22	1	-1/+26
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\| * \|	Merge pull request #891 from YosysHQ/xilinx_keep	David Shah	2019-03-22	2	-25/+31
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\| \| *	xilinx: Add keep attribute where appropriate	David Shah	2019-03-22	2	-25/+31
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\| *	Improve "read_verilog -dump_vlog[12]" handling of upto ranges	Clifford Wolf	2019-03-21	1	-3/+6
\| *	Improve read_verilog debug output capabilities	Clifford Wolf	2019-03-21	3	-15/+42
* \|	Add '-nosrl' option to synth_xilinx	Eddie Hung	2019-03-21	1	-6/+16
* \|	Opt	Eddie Hung	2019-03-21	1	-1/+1
* \|	Fix spacing	Eddie Hung	2019-03-20	1	-239/+239
* \|	Fine tune cells_map.v	Eddie Hung	2019-03-20	1	-19/+15
* \|	Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length	Eddie Hung	2019-03-19	2	-58/+34
* \|	Add support for variable length Xilinx SRL > 128	Eddie Hung	2019-03-19	2	-17/+67
* \|	Restore original synth_xilinx commands	Eddie Hung	2019-03-19	1	-1/+2
* \|	Fix spacing	Eddie Hung	2019-03-19	1	-1/+1
* \|	shregmap -tech xilinx to delete $shiftx for var length SRL	Eddie Hung	2019-03-19	1	-10/+3
* \|	Fix INIT for variable length SRs that have been bumped up one	Eddie Hung	2019-03-19	1	-1/+1
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-19	53	-38/+2398
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\| *	Merge pull request #885 from YosysHQ/clifford/fix873	Clifford Wolf	2019-03-19	1	-2/+4
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\| \| *	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873	Clifford Wolf	2019-03-19	1	-2/+4
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\| *	Merge pull request #808 from eddiehung/read_aiger	Eddie Hung	2019-03-19	35	-6/+632
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\| \| *	Merge https://github.com/YosysHQ/yosys into read_aiger	Eddie Hung	2019-03-19	113	-792/+6364
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\| * \|	Merge pull request #884 from zachjs/master	Clifford Wolf	2019-03-19	2	-1/+61
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\| \| * \|	fix local name resolution in prefix constructs	Zachary Snow	2019-03-18	2	-1/+61
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\| * \|	Update issue template	Clifford Wolf	2019-03-17	1	-5/+5
\| * \|	Update issue template	Clifford Wolf	2019-03-17	1	-0/+8
\| * \|	Merge pull request #877 from FelixVi/master	Clifford Wolf	2019-03-16	1	-1/+4
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\| \| * \|	Add note about test requirements in README	Felix Vietmeyer	2019-03-16	1	-1/+4
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\| * \|	Improve mix of src/wire/wirebit coverage in "mutate -list"	Clifford Wolf	2019-03-16	1	-29/+84
\| * \|	Merge pull request #876 from YosysHQ/clifford/fmcombine	Clifford Wolf	2019-03-16	4	-17/+374
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\| \| * \|	Add "fmcombine -fwd -bwd -nop"	Clifford Wolf	2019-03-15	1	-10/+59
\| \| * \|	Add fmcombine pass	Clifford Wolf	2019-03-15	4	-17/+325
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\| * \|	Merge pull request #875 from YosysHQ/clifford/mutate	Clifford Wolf	2019-03-15	4	-5/+862
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\| \| * \|	Improvements in "mutate" list-reduce algorithm	Clifford Wolf	2019-03-15	1	-13/+36
\| \| * \|	Add "mutate -cfg", improve pick_cover behavior	Clifford Wolf	2019-03-14	1	-46/+101
\| \| * \|	Add a strictly coverage-driven mutation selection strategy	Clifford Wolf	2019-03-14	1	-1/+70
\| \| * \|	Improve "mutate" wire coverage metric	Clifford Wolf	2019-03-14	1	-1/+16
\| \| * \|	Add more mutation types, improve mutation src cover	Clifford Wolf	2019-03-14	1	-92/+268
\| \| * \|	Fix smtbmc.py handling of zero appended steps	Clifford Wolf	2019-03-14	1	-5/+5
\| \| * \|	Add "mutate" command DB reduce functionality	Clifford Wolf	2019-03-14	1	-12/+181
\| \| * \|	Add hashlib "<container>::element(int n)" methods	Clifford Wolf	2019-03-14	1	-0/+6