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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-22 19:14:04 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-22 19:14:04 -0700 |
| commit | 0895093c7ce91e13c7fa8e878ae41f8877b3870d (patch) | |
| tree | 0521707d4c3f62e9f83cbee3bcc56dd7753ce6ce | |
| parent | 456295eb6686316dd6090ed32787bd91dc6e8d61 (diff) | |
| download | yosys-0895093c7ce91e13c7fa8e878ae41f8877b3870d.tar.gz yosys-0895093c7ce91e13c7fa8e878ae41f8877b3870d.tar.bz2 yosys-0895093c7ce91e13c7fa8e878ae41f8877b3870d.zip | |
Leftover printf
| -rw-r--r-- | passes/techmap/shregmap.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 7e01ff134..d9a4aba99 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -119,7 +119,6 @@ struct ShregmapTechXilinx7 : ShregmapTech j = cell->getParam("\\S_WIDTH").as_int(); int k = 0; for (auto bit : sigmap(cell->getPort("\\B"))) { - printf("%d\n", bit.offset); sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j, k++); if (k == width) { k = 0; |