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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 14:54:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 14:54:43 -0700 |
| commit | f239cb821edb86c3ec48782139e982819f073a7c (patch) | |
| tree | bcbe2dfbf46fe9549f80378198b36392a3127ca6 | |
| parent | 24553326dde876b51179e092e608ce8174a44681 (diff) | |
| download | yosys-f239cb821edb86c3ec48782139e982819f073a7c.tar.gz yosys-f239cb821edb86c3ec48782139e982819f073a7c.tar.bz2 yosys-f239cb821edb86c3ec48782139e982819f073a7c.zip | |
Fix INIT for variable length SRs that have been bumped up one
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 1d538e262..94a48dbc2 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -106,7 +106,7 @@ module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q); else begin // For variable length, bump up to the next length // because we can't access Q31 - \$__SHREG_ #(.DEPTH(DEPTH+1), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q)); + \$__SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q)); end end else begin |