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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-19 20:31:53 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-19 20:31:53 +0100 |
| commit | 8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5 (patch) | |
| tree | e24d5d241672cbaddf17fce33f5429392014e5e9 | |
| parent | a7ac8393d47303aa3f2bbd103dfde1ec32e12941 (diff) | |
| parent | fe1fb1336b44bb073125aa4b42f12baa316e9fea (diff) | |
| download | yosys-8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5.tar.gz yosys-8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5.tar.bz2 yosys-8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5.zip | |
Merge pull request #885 from YosysHQ/clifford/fix873
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index accc7a259..805ae8e6e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -120,7 +120,8 @@ struct SynthXilinxPass : public Pass log("\n"); log(" map_cells:\n"); log(" techmap -map +/xilinx/cells_map.v\n"); - log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT\n"); + log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); + log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); log(" clean\n"); log("\n"); log(" check:\n"); @@ -274,7 +275,8 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { Pass::call(design, "techmap -map +/xilinx/cells_map.v"); - Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT"); + Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); Pass::call(design, "clean"); } |