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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-21 15:04:44 -0700 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-21 15:04:44 -0700 |
commit | 4cc6b3e942a54e94f472df7817788dc321955a20 (patch) | |
tree | caa045c3746e74c9ebe00fd9b7978decb53fb4c8 | |
parent | 5597270b9e2331d8836c8c24a073aadc1e19584a (diff) | |
download | yosys-4cc6b3e942a54e94f472df7817788dc321955a20.tar.gz yosys-4cc6b3e942a54e94f472df7817788dc321955a20.tar.bz2 yosys-4cc6b3e942a54e94f472df7817788dc321955a20.zip |
Add '-nosrl' option to synth_xilinx
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 0eccb97f2..5237cc4c6 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -64,10 +64,13 @@ struct SynthXilinxPass : public Pass log(" (this feature is experimental and incomplete)\n"); log("\n"); log(" -nobram\n"); - log(" disable infering of block rams\n"); + log(" disable inference of block rams\n"); log("\n"); log(" -nodram\n"); - log(" disable infering of distributed rams\n"); + log(" disable inference of distributed rams\n"); + log("\n"); + log(" -nobram\n"); + log(" disable inference of shift registers\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); @@ -110,8 +113,8 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" simplemap t:$dff*\n"); - log(" shregmap -tech xilinx\n"); + log(" simplemap t:$dff* (only without -nosrl)\n"); + log(" shregmap -tech xilinx (only without -nosrl)\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); @@ -149,6 +152,7 @@ struct SynthXilinxPass : public Pass bool vpr = false; bool nobram = false; bool nodram = false; + bool nosrl = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -193,6 +197,10 @@ struct SynthXilinxPass : public Pass nodram = true; continue; } + if (args[argidx] == "-nosrl") { + nosrl = true; + continue; + } break; } extra_args(args, argidx, design); @@ -257,8 +265,10 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); - Pass::call(design, "simplemap t:$dff*"); - Pass::call(design, "shregmap -tech xilinx"); + if (!nosrl) { + Pass::call(design, "simplemap t:$dff*"); + Pass::call(design, "shregmap -tech xilinx"); + } if (vpr) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); |