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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 12:55:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 12:55:52 -0700 |
| commit | 544843da717734ab9bd9bd88f71db2475fc3abc0 (patch) | |
| tree | f069f4b4d6e0acda7b785102dd1e1b6e4179bf64 | |
| parent | 7b7ddbdba79c94266074e516497f4811d2b5bfc7 (diff) | |
| download | yosys-544843da717734ab9bd9bd88f71db2475fc3abc0.tar.gz yosys-544843da717734ab9bd9bd88f71db2475fc3abc0.tar.bz2 yosys-544843da717734ab9bd9bd88f71db2475fc3abc0.zip | |
techmap inside map_cells stage
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 1 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 4173814fd..c80e51bd0 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -134,7 +134,6 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o else begin \$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(L[lower_clog2-1:0]), .E(E), .Q(T0), .SO(T1)); \$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L[lower_clog2-1:0]), .E(E), .Q(T2), .SO(T3)); - wire [1023:0] _TECHMAP_DO_ = "techmap -map +/techmap.v"; assign Q = L[lower_clog2] ? T2 : T0; end if (DEPTH == 2 * lower_depth) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 326684daf..cabf0b76e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -283,7 +283,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); Pass::call(design, "clean"); |