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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 16:14:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 16:14:08 -0700 |
| commit | ae2a625d0507c9e7476497e0064ffa003aa761f1 (patch) | |
| tree | 5b81313b17908ec07985f30775cad08f5547b52c | |
| parent | 9156e18f9215f7e8e5a36e068b137b01810769b1 (diff) | |
| download | yosys-ae2a625d0507c9e7476497e0064ffa003aa761f1.tar.gz yosys-ae2a625d0507c9e7476497e0064ffa003aa761f1.tar.bz2 yosys-ae2a625d0507c9e7476497e0064ffa003aa761f1.zip | |
Restore original synth_xilinx commands
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 61895e032..0eccb97f2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -112,7 +112,7 @@ struct SynthXilinxPass : public Pass log(" opt -full\n"); log(" simplemap t:$dff*\n"); log(" shregmap -tech xilinx\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); @@ -266,6 +266,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); } + Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); } |