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* Merge pull request #744 from YosysHQ/gatecat/const-in-macrogatecat2021-07-011-1/+1
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| * interchange: Fix handling of constants in macrosgatecat2021-07-011-1/+1
* | interchange: Reserve site ports only reachable from dedicated routinggatecat2021-07-011-0/+4
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* interchange: arch: move macro expansion step before ios packingAlessandro Comodi2021-06-181-1/+1
* Fixing old emails and names in copyrightsgatecat2021-06-121-2/+2
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-111-0/+1
* Using hashlib in archesgatecat2021-06-021-16/+3
* Use hashlib for core netlist structuresgatecat2021-06-021-2/+2
* interchange: Preliminary implementation of macro expansiongatecat2021-05-211-0/+1
* Run clangformatgatecat2021-05-161-2/+1
* interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-131-11/+15
* interchange: arch: do not allow site pips within sitesAlessandro Comodi2021-05-121-6/+0
* interchange: Fix bounding box computationgatecat2021-05-111-2/+2
* interchange: Adding a basic global buffer placergatecat2021-05-071-0/+10
* interchange: Initial global routing implementationgatecat2021-05-071-0/+20
* interchange: Implement getWireTypegatecat2021-04-301-1/+18
* interchange: Handle disconnected/missing cell pinsgatecat2021-04-191-0/+53
* clangformatgatecat2021-04-121-9/+10
* interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
* [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-061-6/+0
* [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-061-0/+11
* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-061-5/+22
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-4/+35
* [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-011-1/+6
* [interchange] Fix site pip check for drivers.Keith Rothman2021-03-301-7/+22
* Implement debugging tools for site router.Keith Rothman2021-03-251-0/+30
* Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-251-98/+35
* Fixup some of the re-mapping logic.Keith Rothman2021-03-251-24/+74
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-20/+95
* Merge pull request #643 from litghost/id_constantsgatecat2021-03-231-4/+25
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| * [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-231-4/+25
* | Initial version of inverter logic.Keith Rothman2021-03-231-0/+31
* | Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-231-41/+5
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* Initial lookahead for FPGA interchange.Keith Rothman2021-03-231-13/+39
* Merge pull request #637 from litghost/refine_site_routergatecat2021-03-221-2/+30
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| * Rework FPGA interchange site router.Keith Rothman2021-03-221-2/+30
* | Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-221-2/+2
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* Add pseudo pip data to chipdb (with schema bump).Keith Rothman2021-03-221-5/+127
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-191-9/+285
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-151-1/+1
* clangformatgatecat2021-03-031-1/+2
* Initial LUT rotation logic.Keith Rothman2021-02-261-1/+196
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-85/+158
* Finish dedicated interconnect implementation.Keith Rothman2021-02-231-9/+36
* Working FF example now that constant merging is done.Keith Rothman2021-02-231-5/+182
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-0/+5
* Remove some signedness warnings.Keith Rothman2021-02-231-1/+1
* Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-231-1/+1
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-1/+1