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synth
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synth-disp_vhdl.adb
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Age
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*
synth-disp_vhdl: fix out conversion. Fix #2145
Tristan Gingold
2022-07-28
1
-21
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+29
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In the case the width of a vector is only 1 bit
*
synth-disp_vhdl: improve output for unsigned. Fix #2139
Tristan Gingold
2022-07-27
1
-2
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+17
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*
elab-vhdl_objtypes: use value_offsets for record elements offset.
Tristan Gingold
2022-05-24
1
-2
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+4
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*
synth: merge value for type_vector and type_array
Tristan Gingold
2022-05-22
1
-6
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+6
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*
synth: use unidimentional arrays in type_acc. Factorize code.
Tristan Gingold
2022-05-22
1
-2
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+2
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*
synth: put direction into port desc
Tristan Gingold
2021-11-17
1
-2
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+2
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*
synth: use a global table for instances attributes
Tristan Gingold
2021-11-17
1
-1
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+0
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*
synth: do not display black boxes
Tristan Gingold
2021-11-12
1
-1
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+6
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*
synth: do full elaboration before synthesis
Tristan Gingold
2021-11-01
1
-2
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+2
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*
synth: expand ports for record. Fix #1675
Tristan Gingold
2021-03-27
1
-10
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+70
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update license headers
umarcor
2021-02-05
1
-5
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+3
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*
synth-disp_vhdl: extend vector conversions (for any range). For #1460
Tristan Gingold
2020-09-20
1
-2
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+20
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*
synth-disp_vhdl: minor output indentation fix.
Tristan Gingold
2020-08-06
1
-1
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+1
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*
netlists: disp attributes in vhdl output (as comments). For #1318
Tristan Gingold
2020-05-23
1
-0
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+1
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*
types: introduce Direction_Type, which replaces Iir_Direction.
Tristan Gingold
2020-04-20
1
-4
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+4
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Global renaming.
*
synth: extract synth.objtypes from synth.values.
Tristan Gingold
2020-04-09
1
-1
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+1
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*
synth: add value_memory and use it to store objects value.
Tristan Gingold
2020-04-06
1
-2
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+2
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*
synth: rework - use valtyp for expressions.
Tristan Gingold
2020-04-02
1
-2
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+2
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*
synth-disp_vhdl: do not wrap inout ports. For #1166
Tristan Gingold
2020-03-22
1
-3
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+12
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*
synth: improve support of 0-width nets and gates. Fix #1113
Tristan Gingold
2020-01-25
1
-2
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+8
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*
synth-disp_vhdl: handle conversion from signed integers.
Tristan Gingold
2020-01-01
1
-1
/
+5
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*
synth: rework the sname API.
Tristan Gingold
2019-11-28
1
-1
/
+1
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*
introduce package utils_io.
Tristan Gingold
2019-11-21
1
-0
/
+1
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*
synth-disp_vhdl: handle arrays for in-converters.
Tristan Gingold
2019-11-12
1
-1
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+20
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*
synth-disp_vhdl: fix incorrect code for record of width
Tristan Gingold
2019-10-08
1
-1
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+3
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*
synth-disp_vhdl: handle array/record of 1 element.
Tristan Gingold
2019-10-08
1
-3
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+11
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*
synth-disp_vhdl: handle enum of width 1 for
Tristan Gingold
2019-10-07
1
-2
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+6
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*
synth-disp_vhdl: handle in conversions from bitvector. Fix #940
Tristan Gingold
2019-09-25
1
-0
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+5
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*
synth-disp_vhdl: handle disp conversion with bits (and boolean).
Tristan Gingold
2019-09-25
1
-5
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+17
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*
synth-disp_vhdl: improve support of boolean, suv.
Tristan Gingold
2019-09-15
1
-17
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+16
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*
synth: improve support of negative integer values.
Tristan Gingold
2019-09-11
1
-1
/
+6
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*
synth: Add width field in type_type record.
Tristan Gingold
2019-09-11
1
-4
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+4
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*
synth-disp_vhdl: handle arrays in disp_out_converter.
Tristan Gingold
2019-09-05
1
-1
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+19
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*
synth-disp_vhdl: handle records for outputs.
Tristan Gingold
2019-09-04
1
-42
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+76
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*
synth-disp_vhdl: handle record for input ports.
Tristan Gingold
2019-09-03
1
-29
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+91
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*
initial support for reduce and/or (#900)
Pepijn de Vos
2019-08-20
1
-1
/
+2
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*
synth: handle integers for displaying vhdl ports.
Tristan Gingold
2019-08-16
1
-0
/
+10
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*
add synthesis support for logic operators on numeric types (#893)
Pepijn de Vos
2019-08-15
1
-0
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+11
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* add logic operators on unsigned * handle signed too * handle unary not
*
synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.
Tristan Gingold
2019-08-08
1
-3
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+12
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*
synth: handle more conversions in disp_vhdl
Tristan Gingold
2019-07-29
1
-1
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+44
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*
synth: use original entity to display netlist.
Tristan Gingold
2019-07-23
1
-0
/
+231