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* synth-disp_vhdl: fix out conversion. Fix #2145Tristan Gingold2022-07-281-21/+29
* synth-disp_vhdl: improve output for unsigned. Fix #2139Tristan Gingold2022-07-271-2/+17
* elab-vhdl_objtypes: use value_offsets for record elements offset.Tristan Gingold2022-05-241-2/+4
* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-221-6/+6
* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-221-2/+2
* synth: put direction into port descTristan Gingold2021-11-171-2/+2
* synth: use a global table for instances attributesTristan Gingold2021-11-171-1/+0
* synth: do not display black boxesTristan Gingold2021-11-121-1/+6
* synth: do full elaboration before synthesisTristan Gingold2021-11-011-2/+2
* synth: expand ports for record. Fix #1675Tristan Gingold2021-03-271-10/+70
* update license headersumarcor2021-02-051-5/+3
* synth-disp_vhdl: extend vector conversions (for any range). For #1460Tristan Gingold2020-09-201-2/+20
* synth-disp_vhdl: minor output indentation fix.Tristan Gingold2020-08-061-1/+1
* netlists: disp attributes in vhdl output (as comments). For #1318Tristan Gingold2020-05-231-0/+1
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-4/+4
* synth: extract synth.objtypes from synth.values.Tristan Gingold2020-04-091-1/+1
* synth: add value_memory and use it to store objects value.Tristan Gingold2020-04-061-2/+2
* synth: rework - use valtyp for expressions.Tristan Gingold2020-04-021-2/+2
* synth-disp_vhdl: do not wrap inout ports. For #1166Tristan Gingold2020-03-221-3/+12
* synth: improve support of 0-width nets and gates. Fix #1113Tristan Gingold2020-01-251-2/+8
* synth-disp_vhdl: handle conversion from signed integers.Tristan Gingold2020-01-011-1/+5
* synth: rework the sname API.Tristan Gingold2019-11-281-1/+1
* introduce package utils_io.Tristan Gingold2019-11-211-0/+1
* synth-disp_vhdl: handle arrays for in-converters.Tristan Gingold2019-11-121-1/+20
* synth-disp_vhdl: fix incorrect code for record of widthTristan Gingold2019-10-081-1/+3
* synth-disp_vhdl: handle array/record of 1 element.Tristan Gingold2019-10-081-3/+11
* synth-disp_vhdl: handle enum of width 1 forTristan Gingold2019-10-071-2/+6
* synth-disp_vhdl: handle in conversions from bitvector. Fix #940Tristan Gingold2019-09-251-0/+5
* synth-disp_vhdl: handle disp conversion with bits (and boolean).Tristan Gingold2019-09-251-5/+17
* synth-disp_vhdl: improve support of boolean, suv.Tristan Gingold2019-09-151-17/+16
* synth: improve support of negative integer values.Tristan Gingold2019-09-111-1/+6
* synth: Add width field in type_type record.Tristan Gingold2019-09-111-4/+4
* synth-disp_vhdl: handle arrays in disp_out_converter.Tristan Gingold2019-09-051-1/+19
* synth-disp_vhdl: handle records for outputs.Tristan Gingold2019-09-041-42/+76
* synth-disp_vhdl: handle record for input ports.Tristan Gingold2019-09-031-29/+91
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-201-1/+2
* synth: handle integers for displaying vhdl ports.Tristan Gingold2019-08-161-0/+10
* add synthesis support for logic operators on numeric types (#893)Pepijn de Vos2019-08-151-0/+11
* synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.Tristan Gingold2019-08-081-3/+12
* synth: handle more conversions in disp_vhdlTristan Gingold2019-07-291-1/+44
* synth: use original entity to display netlist.Tristan Gingold2019-07-231-0/+231