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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-21 21:21:22 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-22 07:09:22 +0200 |
| commit | 9ee5974eb73b553de30a64e635c328f92b2296a3 (patch) | |
| tree | da5aa0fffffe925908ecbb06053e78e073dbac24 /src/synth/synth-disp_vhdl.adb | |
| parent | 8538537c96f380c7822c6101435b1ebfea58f9a9 (diff) | |
| download | ghdl-9ee5974eb73b553de30a64e635c328f92b2296a3.tar.gz ghdl-9ee5974eb73b553de30a64e635c328f92b2296a3.tar.bz2 ghdl-9ee5974eb73b553de30a64e635c328f92b2296a3.zip | |
synth: use unidimentional arrays in type_acc. Factorize code.
Diffstat (limited to 'src/synth/synth-disp_vhdl.adb')
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 8a5f4f863..dfb4a78d6 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -196,7 +196,7 @@ package body Synth.Disp_Vhdl is else -- Any array. declare - Bnd : Bound_Type renames Typ.Abounds.D (1); + Bnd : Bound_Type renames Typ.Abound; El_Type : constant Node := Get_Element_Subtype (Ptype); El_W : constant Width := Get_Type_Width (Typ.Arr_El); Idx : Int32; @@ -375,7 +375,7 @@ package body Synth.Disp_Vhdl is Put_Line (");"); else declare - Bnd : Bound_Type renames Typ.Abounds.D (1); + Bnd : Bound_Type renames Typ.Abound; El_Type : constant Node := Get_Element_Subtype (Ptype); El_W : constant Width := Get_Type_Width (Typ.Arr_El); Idx : Int32; |