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| author | Tristan Gingold <tgingold@free.fr> | 2021-11-17 21:43:10 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-11-17 21:43:10 +0100 |
| commit | 29b56efcbdaea0002b4f71e229ee44c1ebe75a08 (patch) | |
| tree | 5d9792f5a8a3532f695a83f20b3e4cf54fc71b5e /src/synth/synth-disp_vhdl.adb | |
| parent | d6f1c6a47fb8df07fca517fb68078c324c761a97 (diff) | |
| download | ghdl-29b56efcbdaea0002b4f71e229ee44c1ebe75a08.tar.gz ghdl-29b56efcbdaea0002b4f71e229ee44c1ebe75a08.tar.bz2 ghdl-29b56efcbdaea0002b4f71e229ee44c1ebe75a08.zip | |
synth: put direction into port desc
Diffstat (limited to 'src/synth/synth-disp_vhdl.adb')
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 58f7989e7..8a5f4f863 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -63,7 +63,7 @@ package body Synth.Disp_Vhdl is end loop; for I in 1 .. Get_Nbr_Outputs (M) loop Desc := Get_Output_Desc (M, I - 1); - if not Desc.Is_Inout then + if Desc.Dir /= Port_Inout then -- inout ports are not prefixed, so they must not be declared -- as signals. Disp_Signal (Desc); @@ -518,7 +518,7 @@ package body Synth.Disp_Vhdl is Pfx_Wrap := New_Sname_User (Name_Wrap, No_Sname); for P of Ports_Desc (Main) loop -- INOUT ports are handled specially. - if not P.Is_Inout then + if P.Dir /= Port_Inout then Pfx := Get_Sname_Prefix (P.Name); if Pfx = No_Sname then -- Normal port, without a prefix. |