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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-02 07:35:01 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-02 07:35:01 +0200 |
| commit | fbbdd1e3aeac3adcfa073f3953027972f36e2c82 (patch) | |
| tree | 6770feccb72bf9c6f4f0900a8ddfd0fada205f79 /src/synth/synth-disp_vhdl.adb | |
| parent | c23324b6b718eda1b34302ea497e0f65fca1a9e1 (diff) | |
| download | ghdl-fbbdd1e3aeac3adcfa073f3953027972f36e2c82.tar.gz ghdl-fbbdd1e3aeac3adcfa073f3953027972f36e2c82.tar.bz2 ghdl-fbbdd1e3aeac3adcfa073f3953027972f36e2c82.zip | |
synth: rework - use valtyp for expressions.
Diffstat (limited to 'src/synth/synth-disp_vhdl.adb')
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index c60a65e59..436ba938a 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -230,7 +230,7 @@ package body Synth.Disp_Vhdl is Port_Name : constant String := Name_Table.Image (Get_Identifier (Port)); Port_Type : constant Node := Get_Type (Port); - Typ : constant Type_Acc := Get_Value_Type (Inst, Port_Type); + Typ : constant Type_Acc := Get_Subtype_Object (Inst, Port_Type); begin Disp_In_Converter (Port_Name, Port_Name, 0, Port_Type, Typ, True); end Disp_Input_Port_Converter; @@ -386,7 +386,7 @@ package body Synth.Disp_Vhdl is Port_Name : constant String := Name_Table.Image (Get_Identifier (Port)); Port_Type : constant Node := Get_Type (Port); - Typ : constant Type_Acc := Get_Value_Type (Inst, Port_Type); + Typ : constant Type_Acc := Get_Subtype_Object (Inst, Port_Type); begin Disp_Out_Converter (Port_Name, Port_Name, 0, Port_Type, Typ, True); end Disp_Output_Port_Converter; |