diff options
| author | Tristan Gingold <tgingold@free.fr> | 2022-05-22 09:09:14 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-22 09:09:14 +0200 |
| commit | 946320e0984df406f0e3c50cd3db0fb49df5ec9b (patch) | |
| tree | 97d51eff8e649cacf5ad081f7dd9258553ddb2b2 /src/synth/synth-disp_vhdl.adb | |
| parent | c56080fed0b46083cf138962c5bb125ea08bfa0e (diff) | |
| download | ghdl-946320e0984df406f0e3c50cd3db0fb49df5ec9b.tar.gz ghdl-946320e0984df406f0e3c50cd3db0fb49df5ec9b.tar.bz2 ghdl-946320e0984df406f0e3c50cd3db0fb49df5ec9b.zip | |
synth: merge value for type_vector and type_array
Diffstat (limited to 'src/synth/synth-disp_vhdl.adb')
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index dfb4a78d6..8243a89ff 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -157,7 +157,7 @@ package body Synth.Disp_Vhdl is when Iir_Kind_Array_Type_Definition => if Btype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Vector_Type then -- Nothing to do. - W := Typ.Vbound.Len; + W := Typ.Abound.Len; Disp_In_Lhs (Mname, Off, W, Full); Put (Pfx); if W = 1 then @@ -167,7 +167,7 @@ package body Synth.Disp_Vhdl is end if; Put_Line (";"); elsif Is_Std_Logic_Array (Btype) then - W := Typ.Vbound.Len; + W := Typ.Abound.Len; Disp_In_Lhs (Mname, Off, W, Full); if W > 1 then if Full then @@ -189,7 +189,7 @@ package body Synth.Disp_Vhdl is end if; Put_Line (";"); elsif Btype = Vhdl.Std_Package.Bit_Vector_Type_Definition then - W := Typ.Vbound.Len; + W := Typ.Abound.Len; Disp_In_Lhs (Mname, Off, W, Full); Put ("to_stdlogicvector (" & Pfx & ")"); Put_Line (";"); @@ -340,7 +340,7 @@ package body Synth.Disp_Vhdl is when Iir_Kind_Array_Type_Definition => if Btype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Vector_Type then -- Nothing to do. - W := Typ.Vbound.Len; + W := Typ.Abound.Len; Put (" " & Pfx); if W = 1 then Put (" (" & Pfx & "'left)"); @@ -350,7 +350,7 @@ package body Synth.Disp_Vhdl is Put_Line (";"); elsif Btype = Vhdl.Std_Package.Bit_Vector_Type_Definition then -- Nothing to do. - W := Typ.Vbound.Len; + W := Typ.Abound.Len; Put (" " & Pfx & " <= "); if W = 1 then -- This is an array of length 1. A scalar is used in the @@ -366,7 +366,7 @@ package body Synth.Disp_Vhdl is Put_Line (");"); elsif Is_Std_Logic_Array (Btype) then -- unsigned, signed or a compatible array. - W := Typ.Vbound.Len; + W := Typ.Abound.Len; Put (" " & Pfx & " <= "); Put (Name_Table.Image (Get_Identifier (Get_Type_Declarator (Btype)))); |