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| author | Tristan Gingold <tgingold@free.fr> | 2021-11-01 19:50:19 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-11-01 21:11:10 +0100 |
| commit | 86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b (patch) | |
| tree | e34bdcf719bdc08cb22a65e04ad67b57b0c06879 /src/synth/synth-disp_vhdl.adb | |
| parent | 74043fa1aa40c375c7f299e6b5f1b6ea9150580e (diff) | |
| download | ghdl-86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b.tar.gz ghdl-86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b.tar.bz2 ghdl-86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b.zip | |
synth: do full elaboration before synthesis
Diffstat (limited to 'src/synth/synth-disp_vhdl.adb')
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index c920e0ae5..bc1642c07 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -27,11 +27,11 @@ with Vhdl.Ieee.Std_Logic_1164; with Vhdl.Errors; use Vhdl.Errors; with Vhdl.Utils; use Vhdl.Utils; +with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes; + with Netlists.Iterators; use Netlists.Iterators; with Netlists.Disp_Vhdl; use Netlists.Disp_Vhdl; -with Synth.Objtypes; use Synth.Objtypes; - package body Synth.Disp_Vhdl is procedure Disp_Signal (Desc : Port_Desc) is begin |