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author | Tristan Gingold <tgingold@free.fr> | 2021-11-12 18:51:28 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-11-12 18:52:58 +0100 |
commit | b5a0a2bbd7110f105f7d8370b7d8773ec4a463ab (patch) | |
tree | 6012260c28b70f4266cfafa9ab3a85d37e2f464f /src/synth/synth-disp_vhdl.adb | |
parent | fbe600e08c0f08d7789ca8e504759af5f1edc00f (diff) | |
download | ghdl-b5a0a2bbd7110f105f7d8370b7d8773ec4a463ab.tar.gz ghdl-b5a0a2bbd7110f105f7d8370b7d8773ec4a463ab.tar.bz2 ghdl-b5a0a2bbd7110f105f7d8370b7d8773ec4a463ab.zip |
synth: do not display black boxes
Diffstat (limited to 'src/synth/synth-disp_vhdl.adb')
-rw-r--r-- | src/synth/synth-disp_vhdl.adb | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index bc1642c07..cbded9008 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -473,6 +473,7 @@ package body Synth.Disp_Vhdl is M : Module; Num : Natural; begin + -- Count number of modules. Num := 0; M := Get_Next_Sub_Module (Main); while M /= No_Module loop @@ -482,6 +483,7 @@ package body Synth.Disp_Vhdl is M := Get_Next_Sub_Module (M); end loop; + -- Fill array of modules, display. declare type Module_Array is array (1 .. Num) of Module; Modules : Module_Array; @@ -497,7 +499,10 @@ package body Synth.Disp_Vhdl is end loop; for I in reverse Modules'Range loop - Netlists.Disp_Vhdl.Disp_Vhdl (Modules (I), False); + -- Skip blackboxes. + if Get_Self_Instance (Modules (I)) /= No_Instance then + Netlists.Disp_Vhdl.Disp_Vhdl (Modules (I), False); + end if; end loop; end; end; |