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path: root/src/synth/netlists-disp_vhdl.adb
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* netlists-disp_vhdl: handle conversion from std_logic to signed/unsigned.Tristan Gingold2019-12-241-2/+12
* netlists-disp_vhdl: handle 1-bit add/sub.Tristan Gingold2019-12-051-4/+12
* netlists-disp_vhdl: handle more ROMs.Tristan Gingold2019-12-051-2/+12
* netlists-disp_vhdl: handle id_mem_rd_syncTristan Gingold2019-12-051-0/+15
* netlists-disp_vhdl: handle unconnected outputs. Fix #1050Tristan Gingold2019-12-041-10/+10
* netlists-disp_vhdl: force conversion for mux2Tristan Gingold2019-11-281-1/+2
* netlists: remove port API (make it easier to interface).Tristan Gingold2019-11-281-18/+27
* netlists: remove port_inout.Tristan Gingold2019-11-281-2/+0
* netlists-disp_vhdl: handle UB32 in Disp_Const_Bit. Fix #1039Tristan Gingold2019-11-271-0/+8
* introduce package utils_io.Tristan Gingold2019-11-211-20/+1
* netlists: initial support of net of width 0.Tristan Gingold2019-11-121-1/+0
* netlists: expand dyn_insert_enTristan Gingold2019-11-111-0/+1
* netlists: add more support for dyn_insert_enTristan Gingold2019-11-111-6/+17
* netlists-disp_vhdl: handle truncate to width 1.Tristan Gingold2019-11-051-2/+7
* netlists-disp_vhdl: prefix of strunc/utrunc cannot be a constant.Tristan Gingold2019-10-281-1/+3
* synth: generate cover for assertion precedent.Tristan Gingold2019-10-211-0/+4
* netlists-disp_vhdl: display memory initialization value.Tristan Gingold2019-10-201-2/+46
* netlists-disp_vhdl: display memories.Tristan Gingold2019-10-171-1/+97
* netlists-disp_vhdl: fix pasto on id_asr.Tristan Gingold2019-10-101-5/+5
* netlists-disp_vhdl: handle const_SB32Tristan Gingold2019-10-091-1/+2
* netlists: remove get_parent renaming for input.Tristan Gingold2019-10-061-2/+2
* netlists: remove renaming of Get_Parent for Net.Tristan Gingold2019-10-061-4/+5
* netlists: remove get_name renaming for modules.Tristan Gingold2019-10-061-4/+4
* netlists: Remove Get_Name renaming for instances.Tristan Gingold2019-10-061-2/+2
* netlists-disp_vhdl: handle lsl, rol, asr, nand, nor.Tristan Gingold2019-10-041-0/+18
* netlists-disp_vhdl: add qualification when needed for =Tristan Gingold2019-10-041-5/+24
* netlists-disp_vhdl: handle empty operand for concat2, addTristan Gingold2019-10-041-1/+30
* netlists-disp_vhdl: handle id_negTristan Gingold2019-10-041-0/+2
* netlists: rename id_memidx1 to id_memidxTristan Gingold2019-10-031-1/+1
* synth: replace memidx2 by addidx; handle some 2d arrays.Tristan Gingold2019-10-031-3/+28
* synth: simplify dyn_insert.Tristan Gingold2019-10-021-3/+3
* synth: simplify id_dyn_extract.Tristan Gingold2019-10-021-8/+1
* synth: introduce memidx1Tristan Gingold2019-10-021-0/+15
* netlists-disp_vhdl: handle Const_Log, add comments, fix assertion.Tristan Gingold2019-10-021-1/+22
* netlists-disp_vhdl: display constant signals connected to user submodules.Tristan Gingold2019-10-011-0/+2
* synth: add support for integer rem.Tristan Gingold2019-10-011-0/+6
* netlists-disp_vhdl: improve disp_x_lit.Tristan Gingold2019-09-281-3/+9
* netlists-disp_vhdl: handle id_edge.Tristan Gingold2019-09-281-0/+3
* synth: fix handling of single-bit memories.Tristan Gingold2019-09-261-4/+11
* netlists-disp_vhdl: handle lsr.Tristan Gingold2019-09-211-0/+4
* synth: use constant for constant values.Tristan Gingold2019-09-211-30/+62
* synth: Add support for PSL cover directive (#930)T. Meissner2019-09-191-0/+4
* synth: minor refactoring about const gates.Tristan Gingold2019-09-151-36/+22
* synth: add const_x gate.Tristan Gingold2019-09-111-1/+5
* synth: introduce slice type.Tristan Gingold2019-09-111-0/+4
* synth: add const_sb32, add smul/umul.Tristan Gingold2019-09-071-1/+1
* synth: handle const_bit in disp_constant_inline.Tristan Gingold2019-09-041-0/+4
* synth: remove insert gate.Tristan Gingold2019-08-311-22/+0
* netlists-disp_vhdl: do not used literals for prefixes.Tristan Gingold2019-08-271-12/+53
* synth: set name to assert/assume gates.Tristan Gingold2019-08-201-2/+8
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