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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-06 13:10:00 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-06 13:10:00 +0200 |
| commit | 7748a70eb1aa9da5b8033a8955d8827385893075 (patch) | |
| tree | 85738f420b4b0255b229bba96b01bbfad215527e /src/synth/netlists-disp_vhdl.adb | |
| parent | 3d35074b10658634d0e1a280575fa6af0b08730f (diff) | |
| download | ghdl-7748a70eb1aa9da5b8033a8955d8827385893075.tar.gz ghdl-7748a70eb1aa9da5b8033a8955d8827385893075.tar.bz2 ghdl-7748a70eb1aa9da5b8033a8955d8827385893075.zip | |
netlists: remove get_parent renaming for input.
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 6bf6701a5..154f9f361 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -256,7 +256,7 @@ package body Netlists.Disp_Vhdl is begin I := Get_First_Sink (O); if I /= No_Input then - O_Inst := Get_Parent (I); + O_Inst := Get_Input_Parent (I); else O_Inst := No_Instance; end if; @@ -410,7 +410,7 @@ package body Netlists.Disp_Vhdl is begin I := Get_First_Sink (Get_Output (Inst, 0)); while I /= No_Input loop - if Need_Name (Get_Parent (I)) then + if Need_Name (Get_Input_Parent (I)) then return True; end if; I := Get_Next_Sink (I); |