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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-04 20:10:02 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-04 20:10:02 +0200 |
| commit | 79ea1b76dd0e80972684fada63a8affc53887c81 (patch) | |
| tree | 441f9790f6047eb2bb362e69a028adbf17d43c40 /src/synth/netlists-disp_vhdl.adb | |
| parent | 42a6039733c0bd897d5b8d185704e8aee2e14e41 (diff) | |
| download | ghdl-79ea1b76dd0e80972684fada63a8affc53887c81.tar.gz ghdl-79ea1b76dd0e80972684fada63a8affc53887c81.tar.bz2 ghdl-79ea1b76dd0e80972684fada63a8affc53887c81.zip | |
netlists-disp_vhdl: handle empty operand for concat2, add
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 9464eba5d..edda84605 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -782,7 +782,19 @@ package body Netlists.Disp_Vhdl is when Id_Xor => Disp_Template (" \o0 <= \i0 xor \i1;" & NL, Inst); when Id_Concat2 => - Disp_Template (" \o0 <= \i0 & \i1;" & NL, Inst); + declare + Wd : constant Width := Get_Width (Get_Output (Inst, 0)); + begin + if Wd = 1 then + if Get_Width (Get_Input_Net (Inst, 0)) = 0 then + Disp_Template (" \o0 <= \i1; -- concat" & NL, Inst); + else + Disp_Template (" \o0 <= \i0; -- concat" & NL, Inst); + end if; + else + Disp_Template (" \o0 <= \i0 & \i1;" & NL, Inst); + end if; + end; when Id_Concat3 => Disp_Template (" \o0 <= \i0 & \i1 & \i2;" & NL, Inst); when Id_Concat4 => @@ -813,6 +825,23 @@ package body Netlists.Disp_Vhdl is Put ((1 .. Natural (Ow - Iw) => '0')); Disp_Template (""" & \i0; -- uext" & NL, Inst); end; + when Id_Sextend => + declare + Ow : constant Width := Get_Width (Get_Output (Inst, 0)); + Iw : constant Width := Get_Width (Get_Input_Net (Inst, 0)); + begin + pragma Assert (Iw > 0); + pragma Assert (Ow > Iw); + Disp_Template (" \o0 <= ", Inst); + if Iw = 1 then + Disp_Template ("(\n0 downto 0 => \i0); -- sext" & NL, + Inst, (0 => Ow)); + else + Disp_Template + ("std_logic_vector (resize (\si0, \n0)); -- sext" & NL, + Inst, (0 => Ow)); + end if; + end; when Id_Lsr => Disp_Template (" \o0 <= std_logic_vector " |