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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-04 20:10:13 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-04 20:10:13 +0200 |
| commit | b8fc71301c28d18aa8b8c15c49f4c67103afedc2 (patch) | |
| tree | b93869cd704bab95b8de60cdd08d96b2602c6915 /src/synth/netlists-disp_vhdl.adb | |
| parent | 79ea1b76dd0e80972684fada63a8affc53887c81 (diff) | |
| download | ghdl-b8fc71301c28d18aa8b8c15c49f4c67103afedc2.tar.gz ghdl-b8fc71301c28d18aa8b8c15c49f4c67103afedc2.tar.bz2 ghdl-b8fc71301c28d18aa8b8c15c49f4c67103afedc2.zip | |
netlists-disp_vhdl: add qualification when needed for =
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 29 |
1 files changed, 24 insertions, 5 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index edda84605..a1126a852 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -418,7 +418,7 @@ package body Netlists.Disp_Vhdl is return False; end Need_Signal; - type Conv_Type is (Conv_None, Conv_Unsigned, Conv_Signed); + type Conv_Type is (Conv_None, Conv_Slv, Conv_Unsigned, Conv_Signed); procedure Disp_Net_Expr (N : Net; Inst : Instance; Conv : Conv_Type) is @@ -437,6 +437,14 @@ package body Netlists.Disp_Vhdl is case Conv is when Conv_None => Disp_Constant_Inline (Net_Inst); + when Conv_Slv => + if Get_Width (N) = 1 then + Put ("std_logic'("); + else + Put ("std_logic_vector'("); + end if; + Disp_Constant_Inline (Net_Inst); + Put (")"); when Conv_Unsigned => Put ("unsigned'("); Disp_Constant_Inline (Net_Inst); @@ -448,7 +456,8 @@ package body Netlists.Disp_Vhdl is end case; else case Conv is - when Conv_None => + when Conv_None + | Conv_Slv => Disp_Net_Name (N); when Conv_Unsigned => Put ("unsigned ("); @@ -467,6 +476,11 @@ package body Netlists.Disp_Vhdl is type Uns32_Array is array (Natural range <>) of Uns32; No_Uns32_Arr : constant Uns32_Array := (1 .. 0 => 0); + -- Template: + -- \[C]AN + -- C: conversion u: unsigned, s: signed, f: force logic + -- A: argument o: output, i: input, n: value, p: parameter, l: label + -- N: argument number (0-9) procedure Disp_Template (S : String; Inst : Instance; Val : Uns32_Array := No_Uns32_Arr) is @@ -490,6 +504,9 @@ package body Netlists.Disp_Vhdl is elsif S (I) = 's' then Conv := Conv_Signed; I := I + 1; + elsif S (I) = 'f' then + Conv := Conv_Slv; + I := I + 1; else Conv := Conv_None; end if; @@ -509,7 +526,8 @@ package body Netlists.Disp_Vhdl is V := Get_Param_Uns32 (Inst, Param_Idx (Idx)); case Conv is when Conv_None - | Conv_Unsigned => + | Conv_Unsigned + | Conv_Slv => Put_Uns32 (V); when Conv_Signed => Put_Int32 (To_Int32 (V)); @@ -771,9 +789,10 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= '1' when \si0 >= \si1 else '0';" & NL, Inst); when Id_Eq => - Disp_Template (" \o0 <= '1' when \i0 = \i1 else '0';" & NL, Inst); + Disp_Template (" \o0 <= '1' when \fi0 = \i1 else '0';" & NL, + Inst); when Id_Ne => - Disp_Template (" \o0 <= '1' when \i0 /= \i1 else '0';" & NL, + Disp_Template (" \o0 <= '1' when \fi0 /= \i1 else '0';" & NL, Inst); when Id_Or => Disp_Template (" \o0 <= \i0 or \i1;" & NL, Inst); |