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authorTristan Gingold <tgingold@free.fr>2019-11-28 18:31:14 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-28 18:40:27 +0100
commite2ae03c3582edcd71382f6d93f70208af500807d (patch)
treec477b8212d07eca29ad4a4756221c78149f182fc /src/synth/netlists-disp_vhdl.adb
parent8d3c6df5e62e38deac016c116e903ebec6bdb080 (diff)
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netlists-disp_vhdl: force conversion for mux2
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
-rw-r--r--src/synth/netlists-disp_vhdl.adb3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index 847deab34..e99974431 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -865,7 +865,8 @@ package body Netlists.Disp_Vhdl is
" end if;" & NL &
" end process;" & NL, Inst);
when Id_Mux2 =>
- Disp_Template (" \o0 <= \i1 when \i0 = '0' else \i2;" & NL, Inst);
+ Disp_Template
+ (" \o0 <= \i1 when \fi0 = '0' else \i2;" & NL, Inst);
when Id_Mux4 =>
Disp_Template (" with \i0 select \o0 <=" & NL &
" \i1 when ""00""," & NL &