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author | Tristan Gingold <tgingold@free.fr> | 2019-09-26 07:44:53 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-26 07:44:53 +0200 |
commit | d07137710b5a1ff9a0d50341c2fa0432f9c7d4b0 (patch) | |
tree | 1b8288f49830cf6a71922f5dcac0ac526568252c /src/synth/netlists-disp_vhdl.adb | |
parent | decc588e1858cca6f6447a11c7669ac697964805 (diff) | |
download | ghdl-d07137710b5a1ff9a0d50341c2fa0432f9c7d4b0.tar.gz ghdl-d07137710b5a1ff9a0d50341c2fa0432f9c7d4b0.tar.bz2 ghdl-d07137710b5a1ff9a0d50341c2fa0432f9c7d4b0.zip |
synth: fix handling of single-bit memories.
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
-rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 4681dabec..6e12f4876 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -611,12 +611,19 @@ package body Netlists.Disp_Vhdl is Disp_Template (" begin" & NL & " \o0 <= \i0;" & NL & - " \o0 (" & - "to_integer (\ui2) * \p0 + (\sp1 + \n0)" & NL & - " downto to_integer (\ui2) * \p0 + (\sp1))" & + " \o0 (", + Inst); + if Iw > 1 then + Disp_Template + ("to_integer (\ui2) * \p0 + (\sp1 + \n0)" & NL & + " downto ", + Inst, (0 => Iw - 1)); + end if; + Disp_Template + ("to_integer (\ui2) * \p0 + (\sp1))" & " <= \i1;" & NL & " end process;" & NL, - Inst, (0 => Iw - 1)); + Inst); end; when Id_Const_UB32 | Id_Const_UL32 |