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authorTristan Gingold <tgingold@free.fr>2019-11-12 20:06:28 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-12 20:36:03 +0100
commit97c875c15734f991e1c7b190385def8f0b587538 (patch)
treeea0a837dc526d2bc147da536c62544220c94c6ea /src/synth/netlists-disp_vhdl.adb
parent159ba3c92b646fa66a484514078d154068fa5d43 (diff)
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netlists: initial support of net of width 0.
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
-rw-r--r--src/synth/netlists-disp_vhdl.adb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index f673a69de..992f0bf5e 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -1007,7 +1007,6 @@ package body Netlists.Disp_Vhdl is
Ow : constant Width := Get_Width (Get_Output (Inst, 0));
Iw : constant Width := Get_Width (Get_Input_Net (Inst, 0));
begin
- pragma Assert (Iw > 0);
pragma Assert (Ow > Iw);
Disp_Template (" \o0 <= """, Inst);
Put ((1 .. Natural (Ow - Iw) => '0'));