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path: root/src/simul/simul-vhdl_simul.adb
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* simul: improve support of PSL endpointsTristan Gingold2023-02-081-8/+1
* simul: handle signal assignment to procedure individual associationsTristan Gingold2023-02-081-8/+19
* synth: use same layout for records in memory as translateTristan Gingold2023-02-081-1/+1
* simul: refactoring, expose more subprogramsTristan Gingold2023-02-041-34/+27
* ghdlsimul: extract simul-main from simul-vhdl_simulTristan Gingold2023-01-311-94/+8
* simul: use same packing order for nets and for values.Tristan Gingold2023-01-301-26/+24
* simul: handle PSL endpointsTristan Gingold2023-01-181-7/+25
* simul: fix last_value for post vhdl 87Tristan Gingold2023-01-181-103/+143
* simul: disable --trace-signalsTristan Gingold2023-01-151-0/+4
* synth: handle protected functions in conversion functionsTristan Gingold2023-01-121-1/+2
* simul: handle PSL abortsTristan Gingold2023-01-121-0/+45
* simul: avoid a crash after an error in a conditionTristan Gingold2023-01-111-1/+6
* simul: allow function calls in signal association by valueTristan Gingold2023-01-111-0/+2
* simul: add sensitivity for psl processesTristan Gingold2023-01-111-4/+7
* simul: improve assertion messages for pslTristan Gingold2023-01-111-5/+15
* simul: add debug command 'run -s'Tristan Gingold2023-01-111-2/+5
* simul: handle array element resolutionTristan Gingold2023-01-111-1/+6
* simul: enable all debug features during elaborationTristan Gingold2023-01-101-1/+3
* synth: handle indexes in arrays conversionTristan Gingold2023-01-101-2/+2
* simul: handle inertial assignmentsTristan Gingold2023-01-101-2/+14
* simul: set assertion hook before elaborationTristan Gingold2023-01-091-3/+3
* simul-vhdl_simul: fix effective value writesTristan Gingold2023-01-091-1/+20
* simul: handle PSL coverTristan Gingold2023-01-091-1/+2
* simul: handle force/release signal assignmentsTristan Gingold2023-01-031-0/+174
* synth: introduce type_array_unboundedTristan Gingold2023-01-031-0/+2
* simul: handle driving and driving_value attributesTristan Gingold2022-12-261-6/+39
* simul: handle transaction attributeTristan Gingold2022-12-261-3/+4
* simul: handle aggregate is guarded signal assignment targetTristan Gingold2022-12-261-7/+29
* vhdl-canon: handle unaffectedTristan Gingold2022-12-261-0/+5
* synth: add value_sig_val to handle individual signal associationsTristan Gingold2022-12-261-28/+166
* vhdl: fix some compiler warningsTristan Gingold2022-11-081-2/+0
* simul: handle delayed attributeTristan Gingold2022-10-141-6/+55
* simul: handle last_event and last_activeTristan Gingold2022-10-131-4/+98
* simul-vhdl_simul: keep default value of collapsed signalsTristan Gingold2022-10-131-1/+10
* simul: fix a crash due to missing strideTristan Gingold2022-10-131-5/+7
* simul: handle guarded concurrent assignmentsTristan Gingold2022-10-101-14/+32
* simul: complete concurrent procedure callsTristan Gingold2022-10-061-27/+38
* simul: fix initial value of record signalsTristan Gingold2022-10-061-2/+2
* simul: handle suspendable procedure call from sensitized process.Tristan Gingold2022-10-051-3/+7
* simul: finalize empty proceduresTristan Gingold2022-10-011-9/+11
* simul: minor rewriteTristan Gingold2022-10-011-3/+2
* simul: finalize declarations of procedure callsTristan Gingold2022-10-011-0/+4
* simul: handle stable attributeTristan Gingold2022-09-301-5/+33
* synth: factorize codeTristan Gingold2022-09-301-0/+8
* simul: create disconnectionsTristan Gingold2022-09-301-1/+42
* simul: handle quiet attributeTristan Gingold2022-09-291-7/+43
* simul: factorize code, add sub_signal_typeTristan Gingold2022-09-291-11/+11
* simul: support guarded signal assignments (WIP)Tristan Gingold2022-09-291-8/+79
* simul: handle last_value attributeTristan Gingold2022-09-281-1/+23
* simul: fix handling of labels in next/exit statementsTristan Gingold2022-09-281-4/+13
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