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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-08 10:24:08 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-09 06:40:18 +0100 |
| commit | 38a2afee9e3c5a35d353cb0c6f3e65dc1ac41303 (patch) | |
| tree | c2cbd4604083df5ed67cb8c88abd340bb9406e2f /src/simul/simul-vhdl_simul.adb | |
| parent | d51d0111c4ce057fd30b03370249dac8ac61f627 (diff) | |
| download | ghdl-38a2afee9e3c5a35d353cb0c6f3e65dc1ac41303.tar.gz ghdl-38a2afee9e3c5a35d353cb0c6f3e65dc1ac41303.tar.bz2 ghdl-38a2afee9e3c5a35d353cb0c6f3e65dc1ac41303.zip | |
simul-vhdl_simul: fix effective value writes
Diffstat (limited to 'src/simul/simul-vhdl_simul.adb')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 90156b763..3bc859f41 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2510,7 +2510,26 @@ package body Simul.Vhdl_Simul is when Write_Signal_Driving_Value => S.Driving_Value := To_Ghdl_Value (Val); when Write_Signal_Effective_Value => - S.Value_Ptr.all := To_Ghdl_Value (Val); + case Val.Typ.Kind is + when Type_Bit => + S.Value_Ptr.B1 := Ghdl_B1'Val (Read_U8 (Val.Mem)); + when Type_Logic => + S.Value_Ptr.E8 := Read_U8 (Val.Mem); + when Type_Discrete => + if Val.Typ.Sz = 1 then + S.Value_Ptr.E8 := Read_U8 (Val.Mem); + elsif Val.Typ.Sz = 4 then + S.Value_Ptr.I32 := Read_I32 (Val.Mem); + elsif Val.Typ.Sz = 8 then + S.Value_Ptr.I64 := Read_I64 (Val.Mem); + else + raise Internal_Error; + end if; + when Type_Float => + S.Value_Ptr.F64 := Ghdl_F64 (Read_Fp64 (Val.Mem)); + when others => + raise Internal_Error; + end case; end case; when Type_Vector | Type_Array => |