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* synth: handle null-range loopsTristan Gingold2022-09-281-4/+3
* simul: handle null signal assignmentsTristan Gingold2022-09-271-12/+36
* synth: handle attributes in configurationsTristan Gingold2022-09-261-1/+1
* synth: rework error procedure, always pass the instanceTristan Gingold2022-09-251-1/+1
* simul: gather disconnection specifications, create guard signalTristan Gingold2022-09-251-4/+94
* simul: handle empty proceduresTristan Gingold2022-09-251-1/+9
* synth: rework association conversionsTristan Gingold2022-09-251-34/+11
* simul: reuse drivers extraction from elaborationTristan Gingold2022-09-251-71/+19
* synth-vhdl_stmts: minor renamingTristan Gingold2022-09-181-2/+2
* simul: handle type conversions in port associationsTristan Gingold2022-09-181-11/+17
* simul: fix resolved associationTristan Gingold2022-09-171-1/+1
* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-171-2/+2
* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-171-1/+1
* simul: handle active attributeTristan Gingold2022-09-161-10/+49
* simul: improve support of concurrent procedure callTristan Gingold2022-09-161-1/+20
* simul: handle more signals typesTristan Gingold2022-09-151-23/+125
* simul: factorize code for conversion functionsTristan Gingold2022-09-121-19/+6
* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-121-0/+1
* simul: move assertions (not to trigger in case of errors)Tristan Gingold2022-09-111-3/+3
* simul: optimize resolution call only for std_logicTristan Gingold2022-09-111-5/+11
* synth: fix and add checks for memory management.Tristan Gingold2022-09-101-6/+17
* simul: add support for protected objectsTristan Gingold2022-09-081-1/+9
* elab-vhdl_values: factorize codeTristan Gingold2022-09-071-2/+2
* simul: do not propagate errors from resolution functionTristan Gingold2022-09-071-0/+3
* synth: handle generics in blocksTristan Gingold2022-09-061-1/+3
* simul: add an hook to display report/assert messageTristan Gingold2022-09-061-14/+50
* synth: use areapoolsTristan Gingold2022-09-021-84/+105
* synth: factorize code for tracing statements executionTristan Gingold2022-09-021-3/+7
* simul-vhdl_simul: simplify procedure connectTristan Gingold2022-08-261-41/+22
* simul: handle connections of recordsTristan Gingold2022-08-251-1/+18
* simul: improve support of float signalsTristan Gingold2022-08-241-3/+7
* simul: handle conversions and associations with constantsTristan Gingold2022-08-241-43/+373
* simul: simplify codeTristan Gingold2022-08-231-16/+4
* simul: factorize code to compute number of sourcesTristan Gingold2022-08-231-119/+3
* simul: add extra drivers for ports without sourcesTristan Gingold2022-08-231-4/+65
* simul-vhdl_simul: handle waveforms in signal assignmentsTristan Gingold2022-08-211-40/+47
* simul: rework assertions execution and error handlingTristan Gingold2022-08-211-3/+4
* simul: handle concurrent procedure calls (WIP)Tristan Gingold2022-08-211-15/+95
* simul: handle after clauses in signal assignmentTristan Gingold2022-08-211-70/+93
* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-201-10/+252
* simul: handle resolved signals (WIP)Tristan Gingold2022-08-191-42/+295
* ghdlsimul: add an option to debug before elaborationTristan Gingold2022-08-181-3/+3
* simul: handle individual associationsTristan Gingold2022-08-171-2/+9
* simul: add create_connectsTristan Gingold2022-08-171-1/+92
* simul: create terminals (WIP)Tristan Gingold2022-08-171-6/+49
* src/simul: rewrite of ghdl/simul based on synthTristan Gingold2022-07-241-0/+1992
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