diff options
| author | Tristan Gingold <tgingold@free.fr> | 2023-02-08 11:31:04 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-02-08 16:04:34 +0100 |
| commit | 99dbf1376808a1bffb6886811d1585e34673b078 (patch) | |
| tree | ea7b786be0ec52ac6c9501aaa813317ff60470af /src/simul/simul-vhdl_simul.adb | |
| parent | 410f08aa700ee3c4cee834de2266ee9a09fd27bf (diff) | |
| download | ghdl-99dbf1376808a1bffb6886811d1585e34673b078.tar.gz ghdl-99dbf1376808a1bffb6886811d1585e34673b078.tar.bz2 ghdl-99dbf1376808a1bffb6886811d1585e34673b078.zip | |
synth: use same layout for records in memory as translate
Diffstat (limited to 'src/simul/simul-vhdl_simul.adb')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 53afa715c..5626813a2 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2742,7 +2742,7 @@ package body Simul.Vhdl_Simul is -- Create the type. Bnd := Elab.Vhdl_Types.Create_Bounds_From_Length (R.Idx_Typ.Drange, Len); - Arr_Typ := Create_Array_Type (Bnd, True, El_Typ); + Arr_Typ := Create_Array_Type (Bnd, False, True, El_Typ); -- Allocate the array. Arr := Create_Memory (Arr_Typ); |