simul: set assertion hook before elaboration

1 files changed, 3 insertions, 3 deletions

diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index 3bc859f41..5764fe5e3 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -4048,6 +4048,9 @@ package body Simul.Vhdl_Simul is
          Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
       end if;
 
+      Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout);
+      Assertion_Report_Handler := Assertion_Report_Msg'Access;
+
       Status := Grt.Main.Run_Through_Longjump
         (Grt.Processes.Simulation_Init'Access);
 
@@ -4056,9 +4059,6 @@ package body Simul.Vhdl_Simul is
             Grt.Analog_Solver.Start;
          end if;
 
-         Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout);
-         Assertion_Report_Handler := Assertion_Report_Msg'Access;
-
          pragma Assert (Areapools.Is_Empty (Expr_Pool));
          pragma Assert (Areapools.Is_Empty (Process_Pool));