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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-12 18:45:24 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-12 18:45:24 +0100 |
| commit | 42ff36a81d8ce42cb2fb3f2edbc628447e58ee92 (patch) | |
| tree | 0f300762a7605c0a76e63d87a95a8da7bcaf623b /src/simul/simul-vhdl_simul.adb | |
| parent | 768c62a76be455d299a065e5516fb8b7a917c019 (diff) | |
| download | ghdl-42ff36a81d8ce42cb2fb3f2edbc628447e58ee92.tar.gz ghdl-42ff36a81d8ce42cb2fb3f2edbc628447e58ee92.tar.bz2 ghdl-42ff36a81d8ce42cb2fb3f2edbc628447e58ee92.zip | |
synth: handle protected functions in conversion functions
Diffstat (limited to 'src/simul/simul-vhdl_simul.adb')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 14f50fad7..7d1a4312a 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2715,7 +2715,8 @@ package body Simul.Vhdl_Simul is end loop; -- Call resolution function - Res := Exec_Resolution_Call (R.Inst, R.Func, Create_Value_Memtyp (Arr)); + Res := Exec_Resolution_Call + (R.Inst, R.Func, Null_Node, Create_Value_Memtyp (Arr)); -- Set driving value. Exec_Write_Signal (R.Sig, (Res.Typ, Res.Val.Mem), |