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| author | Tristan Gingold <tgingold@free.fr> | 2022-12-26 09:10:02 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-12-26 10:25:20 +0100 |
| commit | 9d4d4c09883d373f01861f827e793d754aeaa7d7 (patch) | |
| tree | bae91ab9a1876abe8259bde0a1659d747df93c69 /src/simul/simul-vhdl_simul.adb | |
| parent | 8a6be3328e812256abd7b01e965ac60630a70888 (diff) | |
| download | ghdl-9d4d4c09883d373f01861f827e793d754aeaa7d7.tar.gz ghdl-9d4d4c09883d373f01861f827e793d754aeaa7d7.tar.bz2 ghdl-9d4d4c09883d373f01861f827e793d754aeaa7d7.zip | |
vhdl-canon: handle unaffected
Diffstat (limited to 'src/simul/simul-vhdl_simul.adb')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 6e3d62e88..1ec6500d2 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -944,6 +944,11 @@ package body Simul.Vhdl_Simul is Aft : Node; Rej : Node; begin + -- Nothing to assign. + if Get_Kind (Waveform) = Iir_Kind_Unaffected_Waveform then + return; + end if; + Rej := Get_Reject_Time_Expression (Stmt); if Rej /= Null_Node then raise Internal_Error; |