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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/README23
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/a2d_nbit.vhd84
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/dac_10_bit.vhd57
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/index-ams.txt53
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/switch_dig_2in.vhd63
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_2in_switch.vhd74
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd2458
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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/DC_Motor.vhd46
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain.vhd33
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain_e.vhd39
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gear_rv_r.vhd41
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/index-ams.txt77
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag.vhd41
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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd527
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd902
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd817
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams.vhd56
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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/buck_sw.vhd40
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/capacitor.vhd46
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/comp_2p2z.vhd53
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/index-ams.txt32
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd66
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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/switch_dig.vhd54
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_BuckConverter.vhd59
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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CalcBuckParams.vhd66
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/MeasFreq.vhd45
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/PLL.vhd72
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk.vhd61
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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_PLL.vhd639
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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/amp_lim.vhd53
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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd990
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd1974
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/bounded_buffer_adt.vhd114
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/index-ams.txt30
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_01.vhd73
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_02a.vhd59
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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_search.vhd80
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_traversal.vhd66
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/ordered_collection_adt.vhd163
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/receiver.vhd62
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/stimulus_types-1.vhd42
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/tb_bounded_buffer_adt.vhd100
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/access-types/test_bench-1.vhd224
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller.vhd47
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd83
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/aliases/controller_system.vhd65
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/aliases/function_plus.vhd59
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/aliases/index-ams.txt28
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_01a.vhd42
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-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd43
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/aliases/tb_function_plus.vhd44
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd42
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd48
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd56
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd39
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd33
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd50
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd45
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd33
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd50
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd54
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/index-ams.txt84
-rw-r--r--testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd33
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diff --git a/testsuite/vests/vhdl-ams/ashenden/README b/testsuite/vests/vhdl-ams/ashenden/README
new file mode 100644
index 000000000..de7180cbf
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/README
@@ -0,0 +1,23 @@
+
+This directory contains copies of the VHDL files from The Designer's Guild
+to VHDL-AMS written by Peter Ashenden, Gregory D. Peterson, and Darrell
+A. Teegarden and published by Morgan Kaufmann Publishers, Inc in 2002.
+Morgan Kaufmann has given the University of Cincinnati permission to
+release these files under the GNU Public License.
+
+In many cases the original figures contained incomplete VHDL. We have
+added additional VHDL constructs we believed necessary to make the VHDL
+complete and processable by a VHDL-AMS compliant analyzer. As we made
+changes to the examples, comments were inserted to demarcate the changes
+we made.
+
+If you find errors or corrections to these files, please submit them to
+us at vests@cliftonlabs.com. Thank you.
+
+------------------------------------------------------------------------
+Philip A. Wilsey
+The University of Cincinnati
+vests@cliftonlabs.com
+------------------------------------------------------------------------
+Last Revised: November 3, 2003
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/a2d_nbit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/a2d_nbit.vhd
new file mode 100644
index 000000000..3bc693b2d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/a2d_nbit.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity a2d_nbit is
+ port ( signal start : in std_ulogic; -- Start signal
+ signal clk : in std_ulogic; -- Strobe clock
+ terminal ain : electrical; -- Analog input terminal
+ signal eoc : out std_ulogic := '0'; -- End of conversion pin
+ signal dout : out std_ulogic_vector(9 downto 0) ); -- Digital output signal
+end entity a2d_nbit;
+
+----------------------------------------------------------------
+
+architecture sar of a2d_nbit is
+
+ constant Vmax : real := 5.0; -- ADC's maximum range
+ constant delay : time := 10 us; -- ADC's conversion time
+
+ type states is (input, convert); -- Two states of A2D Conversion
+ constant bit_range : integer := 9; -- Bit range for dtmp and dout
+
+ quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
+
+begin
+
+ sa_adc: process is
+
+ variable thresh : real := Vmax; -- Threshold to test input voltage against
+ variable Vtmp : real := Vin; -- Snapshot of input voltage
+ -- when conversion starts
+ variable dtmp : std_ulogic_vector(bit_range downto 0); -- Temp. output data
+ variable status : states := input; -- Begin with "input" case
+ variable bit_cnt : integer := bit_range;
+
+ begin
+ case status is
+ when input => -- Read input voltages when start goes high
+ wait on start until start = '1' or start = 'H';
+ bit_cnt := bit_range; -- Reset bit_cnt for conversion
+ thresh := Vmax;
+ Vtmp := Vin; -- Variable to hold input comparison voltage
+ eoc <= '0'; -- Reset end of conversion
+ status := convert; -- Go to convert state
+ when convert => -- Begin successive approximation conversion
+ wait on clk until clk = '1' or clk = 'H';
+ thresh := thresh / 2.0; -- Get value of MSB
+ if Vtmp > thresh then
+ dtmp(bit_cnt) := '1'; -- Store '1' in dtmp variable vector
+ Vtmp := Vtmp - thresh; -- Prepare for next comparison
+ else
+ dtmp(bit_cnt) := '0'; -- Store '0' in dtmp variable vector
+ end if;
+ if bit_cnt > 0 then
+ bit_cnt := bit_cnt - 1; -- Decrement the bit count
+ else
+ dout <= dtmp; -- Put contents of dtmp on output pins
+ eoc <= '1' after delay; -- Signal end of conversion
+ status := input; -- Go to input state
+ end if;
+ end case;
+ end process sa_adc;
+
+ Iin == 0.0; -- Ideal input draws no current
+
+end architecture sar;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/dac_10_bit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/dac_10_bit.vhd
new file mode 100644
index 000000000..7f2226f49
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/dac_10_bit.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity dac_10_bit is
+ port ( signal bus_in : in std_ulogic_vector(9 downto 0);
+ signal clk : in std_ulogic;
+ terminal analog_out : electrical );
+end entity dac_10_bit;
+
+----------------------------------------------------------------
+
+architecture behavioral of dac_10_bit is
+
+ constant v_max : real := 5.0;
+ signal s_out : real := 0.0;
+ quantity v_out across i_out through analog_out to electrical_ref;
+
+begin
+
+ convert : process is
+ variable v_sum : real;
+ variable delta_v : real;
+ begin
+ wait until clk'event and (clk = '1' or clk = 'H');
+ v_sum := 0.0;
+ delta_v := v_max;
+ for i in bus_in'range loop
+ delta_v := delta_v / 2.0;
+ if bus_in(i) = '1' or bus_in(i) = 'H' then
+ v_sum := v_sum + delta_v;
+ end if;
+ end loop;
+ s_out <= v_sum;
+ end process convert;
+
+ v_out == s_out'ramp(100.0E-9);
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/index-ams.txt
new file mode 100644
index 000000000..c262df9e0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/index-ams.txt
@@ -0,0 +1,53 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 8 - Case Study 1: Mixed Signal Focus
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+switch_dig_2in.vhd entity switch_dig_2in ideal Figure 8-6
+a2d_nbit.vhd entity a2d_nbit sar Figure 8-7
+dac_10_bit.vhd entity dac_10_bit behavioral Figure 8-12
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_2in_switch.vhd entity tb_2in_switch TB_2in_switch switch_dig_2in.vhd
+tb_a2d_d2a.vhd entity tb_a2d_d2a TB_a2d_d2a a2d_nbit.vhd, dac_10_bit.vhd
+tb_CS1.vhd entity switch_dig_2in ideal Case Study 1
+-- entity clock ideal
+-- entity clock_duty ideal
+-- entity rc_clk rc_clk
+-- entity bit_cnt behavioral
+-- entity state_mach1 state_diagram
+-- entity sm_cnt sm_cnt
+-- entity a2d_nbit sar
+-- entity shift_reg behavioral
+-- entity frame_gen simple
+-- entity xor2 ideal
+-- entity level_set_tri ideal
+-- entity buffer_tri ideal
+-- entity d2a_bit ideal
+-- entity parity_gen parity_gen
+-- entity tdm_encoder tdm_encoder
+-- entity Digitize_Encode Digitize_Encode
+-- entity stick ideal
+-- entity and2 ideal
+-- entity d_latch_n_edge_rst behav
+-- entity counter_12 counter_12
+-- entity a2d_bit ideal
+-- entity clock_en ideal
+-- entity inverter ideal
+-- entity or2 ideal
+-- entity d2a_nbit behavioral
+-- entity pw2ana pw2ana
+-- entity dig_cmp simple
+-- entity sr_ff simple
+-- entity state_mach_rcvr state_diagram
+-- entity sm_cnt_rcvr sm_cnt_rcvr
+-- entity level_set ideal
+-- entity ser2par a1
+-- entity frame_det simple
+-- entity parity_det parity_det
+-- entity TDM_Demux_dbg TDM_Demux_dbg
+-- entity Decode_PW Decode_PW
+-- entity tb_CS1 TB_CS1
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/switch_dig_2in.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/switch_dig_2in.vhd
new file mode 100644
index 000000000..3793e191a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/switch_dig_2in.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity switch_dig_2in is
+ port ( sw_state : in std_ulogic; -- Digital control input
+ terminal p_in1, p_in2, p_out : electrical ); -- Analog output
+end entity switch_dig_2in;
+
+----------------------------------------------------------------
+
+architecture ideal of switch_dig_2in is
+
+ constant r_open : resistance := 1.0e6; -- Open switch resistance
+ constant r_closed : resistance := 0.001; -- Closed switch resistance
+ constant trans_time : real := 0.00001; -- Transition time to each position
+
+ signal r_sig1 : resistance := r_closed; -- Closed switch resistance variable
+ signal r_sig2 : resistance := r_open; -- Open switch resistance variable
+
+ quantity v1 across i1 through p_in1 to p_out; -- V & I for in1 to out
+ quantity v2 across i2 through p_in2 to p_out; -- V & I for in2 to out
+ quantity r1 : resistance; -- Time-varying resistance for in1 to out
+ quantity r2 : resistance; -- Time-varying resistance for in2 to out
+
+begin
+
+ process (sw_state) is -- Sensitivity to digital control input
+ begin
+ if sw_state = '0' or sw_state = 'L' then -- Close sig1, open sig2
+ r_sig1 <= r_closed;
+ r_sig2 <= r_open;
+ elsif sw_state = '1' or sw_state = 'H' then -- Open sig1, close sig2
+ r_sig1 <= r_open;
+ r_sig2 <= r_closed;
+ end if;
+ end process;
+
+ r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
+ r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
+
+ v1 == r1 * i1; -- Apply Ohm's law to in1
+ v2 == r2 * i2; -- Apply Ohm's law to in2
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_2in_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_2in_switch.vhd
new file mode 100644
index 000000000..89c37df23
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_2in_switch.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE; use IEEE.std_logic_1164.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_2in_switch is
+end tb_2in_switch;
+
+architecture TB_2in_switch of tb_2in_switch is
+ -- Component declarations
+ -- Signal declarations
+ terminal p_in1, p_in2, p_out : electrical;
+ signal ctl_ulogic : std_ulogic;
+ signal ctl_logic : std_logic;
+begin
+ -- Signal assignments
+ ctl_ulogic <= To_X01(ctl_logic); -- Convert X01Z to X01
+ -- Component instances
+ vdc1 : entity work.v_constant(ideal)
+ generic map(
+ level => 1.0
+ )
+ port map(
+ pos => p_in1,
+ neg => ELECTRICAL_REF
+ );
+ vdc2 : entity work.v_constant(ideal)
+ generic map(
+ level => 3.0
+ )
+ port map(
+ pos => p_in2,
+ neg => ELECTRICAL_REF
+ );
+ Clk1 : entity work.clock(ideal)
+ generic map(
+ period => 10.0ms
+ )
+ port map(
+ clk_out => ctl_logic
+ );
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 100.0
+ )
+ port map(
+ p1 => p_out,
+ p2 => electrical_ref
+ );
+ swtch : entity work.switch_dig_2in(ideal)
+ port map(
+ p_in1 => p_in1,
+ p_in2 => p_in2,
+ p_out => p_out,
+ sw_state => ctl_ulogic
+ );
+end TB_2in_switch;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd
new file mode 100644
index 000000000..f18d88bed
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd
@@ -0,0 +1,2458 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- Simple Digital-Controlled Two-position Switch Model
+-- Switch position 1 ('0') or switch position 2 ('1')
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY switch_dig_2in is
+ GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
+ r_closed : RESISTANCE := 0.001; -- Closed switch resistance
+ trans_time : real := 0.00001); -- Transition time to each position
+
+ PORT (sw_state : in std_logic; -- Digital control input
+ TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
+
+END ENTITY switch_dig_2in;
+
+
+ARCHITECTURE ideal OF switch_dig_2in IS
+
+ SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
+ SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
+ QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
+ QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
+ QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
+ QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
+
+BEGIN
+
+ PROCESS (sw_state) -- Sensitivity to digital control input
+ BEGIN
+ IF (sw_state = '0') THEN -- Close sig1, open sig2
+ r_sig1 <= r_closed;
+ r_sig2 <= r_open;
+ ELSIF (sw_state = '1') THEN -- Open sig1, close sig2
+ r_sig1 <= r_open;
+ r_sig2 <= r_closed;
+ END IF;
+ END PROCESS;
+
+ r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
+ r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
+ v1 == r1*i1; -- Apply Ohm's law to in1
+ v2 == r2*i2; -- Apply Ohm's law to in2
+
+END ARCHITECTURE ideal;
+--
+
+-- Digital clock with 50% duty cycle
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock IS
+ GENERIC (
+ period : time); -- Clock period
+
+ PORT (
+ clk_out : OUT std_logic);
+
+END ENTITY clock;
+
+ARCHITECTURE ideal OF clock IS
+
+BEGIN
+
+-- clock process
+ process
+ begin
+ clk_out <= '0';
+ wait for period/2;
+ clk_out <= '1';
+ wait for period/2;
+ end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- This digital clock allows user to specify the duty cycle using
+-- the parameters "on_time" and "off_time"
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY clock_duty IS
+
+ GENERIC (
+ on_time : time := 20 us;
+ off_time : time := 19.98 ms
+ );
+
+ PORT (
+ clock_out : OUT std_logic := '0');
+
+END ENTITY clock_duty;
+
+ARCHITECTURE ideal OF clock_duty IS
+
+BEGIN
+
+-- clock process
+ process
+ begin
+ clock_out <= '1';
+ wait for on_time;
+ clock_out <= '0';
+ wait for off_time;
+ end process;
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rc_clk is
+ port(
+ clk_100k : out std_logic;
+ clk_6K : out std_logic;
+ clk_50 : out std_logic
+ );
+end rc_clk;
+
+architecture rc_clk of rc_clk is
+ -- Component declarations
+ -- Signal declarations
+begin
+ -- Signal assignments
+ -- Component instances
+ XCMP1 : entity work.clock(ideal)
+ generic map(
+ period => 10us
+ )
+ port map(
+ CLK_OUT => clk_100k
+ );
+ XCMP2 : entity work.clock(ideal)
+ generic map(
+ period => 150us
+ )
+ port map(
+ CLK_OUT => clk_6K
+ );
+ clk_50Hz : entity work.clock_duty(ideal)
+ generic map(
+ on_time => 20 us,
+ off_time => 19.98 ms
+ )
+ port map(
+ CLOCK_OUT => clk_50
+ );
+end rc_clk;
+--
+
+-- This model counts the number of input clock transitions and outputs
+-- a '1' when this number equals the value of the user-defined constant 'count'
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity bit_cnt is
+ generic (
+ count : integer -- User-defined value to count up to
+ );
+port
+(
+ bit_in : in std_logic ;
+ clk : in std_logic ;
+ dly_out : out std_logic
+);
+end bit_cnt;
+
+architecture behavioral of bit_cnt is
+begin
+ serial_clock : process is
+ begin
+ wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
+ FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
+ wait until clk'event AND (clk = '1' OR clk = 'H');
+ END LOOP ;
+ dly_out <= '1'; -- After count is reached, set output high
+ wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
+ dly_out <= '0'; -- Reset output to '0' on next clock input
+ end process serial_clock;
+end;
+--
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+
+ENTITY state_mach1 IS
+ PORT (
+ a2d_eoc : IN std_logic;
+ clk_50 : IN std_logic;
+ clk_100k : IN std_logic;
+ clk_6k : IN std_logic;
+ ser_done : IN std_logic;
+ ch_sel : OUT std_logic;
+ frm_gen : OUT std_logic;
+ a2d_oe : OUT std_logic;
+ a2d_start : OUT std_logic;
+ p2s_oe : OUT std_logic;
+ p2s_load : OUT std_logic;
+ parity_oe : OUT std_logic;
+ ser_cnt : OUT std_logic;
+ p2s_clr : OUT std_logic);
+
+END state_mach1;
+
+ARCHITECTURE state_diagram OF state_mach1 IS
+
+ ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+ TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
+ , load, ad_ch2, delay);
+ SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
+
+ SIGNAL FB_frm_gen : std_logic;
+ SIGNAL FB_p2s_load : std_logic;
+ SIGNAL FB_ch_sel : std_logic;
+
+BEGIN
+ frm_gen <= FB_frm_gen ;
+ p2s_load <= FB_p2s_load ;
+ ch_sel <= FB_ch_sel ;
+
+sm1:
+ PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel)
+ BEGIN
+
+ CASE CS_state_mach1_sm1 IS
+ WHEN V_begin =>
+ FB_frm_gen <= ('1');
+ a2d_start <= ('0');
+ a2d_oe <= ('0');
+ FB_p2s_load <= ('0');
+ p2s_clr <= ('0');
+ p2s_oe <= ('0');
+ FB_ch_sel <= ('0');
+ parity_oe <= ('0');
+ ser_cnt <= ('0');
+
+ IF ((FB_frm_gen = '1')) THEN
+ NS_state_mach1_sm1 <= frm_rd;
+ ELSE
+ NS_state_mach1_sm1 <= V_begin;
+ END IF;
+
+ WHEN frm_rd =>
+ FB_p2s_load <= ('1');
+
+ IF ((FB_p2s_load = '1')) THEN
+ NS_state_mach1_sm1 <= ser_oe;
+ ELSE
+ NS_state_mach1_sm1 <= frm_rd;
+ END IF;
+
+ WHEN ser_oe =>
+ p2s_oe <= ('1');
+ FB_frm_gen <= ('0');
+ FB_p2s_load <= ('0');
+ ser_cnt <= ('1');
+
+ IF ((ser_done = '1')) THEN
+ NS_state_mach1_sm1 <= ch1;
+ ELSE
+ NS_state_mach1_sm1 <= ser_oe;
+ END IF;
+
+ WHEN ch1 =>
+ p2s_oe <= ('0');
+ FB_ch_sel <= ('0');
+ a2d_start <= ('1');
+ ser_cnt <= ('0');
+
+ IF ((a2d_eoc = '1')) THEN
+ NS_state_mach1_sm1 <= data_en;
+ ELSE
+ NS_state_mach1_sm1 <= ch1;
+ END IF;
+
+ WHEN data_en =>
+ a2d_start <= ('0');
+ a2d_oe <= ('1');
+ parity_oe <= ('1');
+ NS_state_mach1_sm1 <= load;
+
+ WHEN tdm_oe =>
+ a2d_oe <= ('0');
+ parity_oe <= ('0');
+ p2s_oe <= ('1');
+ FB_p2s_load <= ('0');
+ ser_cnt <= ('1');
+
+ IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
+ NS_state_mach1_sm1 <= ch2;
+ ELSE
+ NS_state_mach1_sm1 <= tdm_oe;
+ END IF;
+
+ WHEN ch2 =>
+ p2s_oe <= ('0');
+ ser_cnt <= ('0');
+ FB_ch_sel <= ('1');
+ NS_state_mach1_sm1 <= delay;
+
+ WHEN load =>
+ FB_p2s_load <= ('1');
+ NS_state_mach1_sm1 <= tdm_oe;
+
+ WHEN ad_ch2 =>
+ a2d_start <= ('1');
+
+ IF ((a2d_eoc = '1')) THEN
+ NS_state_mach1_sm1 <= data_en;
+ ELSE
+ NS_state_mach1_sm1 <= ad_ch2;
+ END IF;
+
+ WHEN delay =>
+ NS_state_mach1_sm1 <= ad_ch2;
+
+ END CASE;
+
+ END PROCESS;
+
+sm1_CTL:
+ PROCESS (clk_100k, clk_50)
+ BEGIN
+
+ IF (clk_100k'event AND clk_100k='1') THEN
+ IF (clk_50= '1' ) THEN
+ CS_state_mach1_sm1 <= V_begin;
+ ELSE
+ CS_state_mach1_sm1 <= NS_state_mach1_sm1;
+ END IF;
+ END IF;
+
+ END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt is
+ port(
+ a2d_eoc : in std_logic;
+ clk_50 : in std_logic;
+ clk_100k : in std_logic;
+ clk_6k : in std_logic;
+ p2s_load : out std_logic;
+ p2s_oe : out std_logic;
+ parity_oe : out std_logic;
+ a2d_start : out std_logic;
+ a2d_oe : out std_logic;
+ frm_gen : out std_logic;
+ ch_sel : out std_logic;
+ p2s_clr : out std_logic
+ );
+end sm_cnt;
+
+architecture sm_cnt of sm_cnt is
+ -- Component declarations
+ -- Signal declarations
+ signal serial_cnt : std_logic;
+ signal XSIG010022 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ bit_cnt1 : entity work.bit_cnt(behavioral)
+ generic map(
+ count => 15
+ )
+ port map(
+ bit_in => serial_cnt,
+ clk => clk_6k,
+ dly_out => XSIG010022
+ );
+ state_mach16 : entity work.state_mach1
+ port map(
+ ser_cnt => serial_cnt,
+ ch_sel => ch_sel,
+ frm_gen => frm_gen,
+ a2d_oe => a2d_oe,
+ a2d_start => a2d_start,
+ parity_oe => parity_oe,
+ p2s_oe => p2s_oe,
+ p2s_load => p2s_load,
+ p2s_clr => p2s_clr,
+ clk_6k => clk_6k,
+ clk_100k => clk_100k,
+ clk_50 => clk_50,
+ a2d_eoc => a2d_eoc,
+ ser_done => XSIG010022
+ );
+end sm_cnt;
+--
+
+--This is a VHDL-AMS model of a simple analog to digital converter. The model
+--describes the general behavior of A/D converters for system level design and
+--verification.
+--The format of the digital output is binary coding.
+--
+--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
+--
+
+-- Use IEEE natures and packages
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity a2d_nbit is
+ generic (
+ Vmax: REAL := 5.0 ; -- ADC's maximum range
+ Nbits: INTEGER := 10 ; -- number bits in ADC's output
+ delay: TIME := 10 us -- ADC's conversion time
+ );
+
+port (
+ signal start: in std_logic ; -- Start signal
+ signal clk: in std_logic ; -- Strobe clock
+ signal oe: in std_logic ; -- Output enable
+ terminal ain: ELECTRICAL ; -- ADC's analog input terminal
+ signal eoc: out std_logic := '0' ; -- End Of Conversion pin
+ signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
+end entity a2d_nbit;
+
+architecture sar of a2d_nbit is
+
+ type states is (input, convert, output) ; -- Three states of A2D Conversion
+ constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
+ quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
+
+begin
+
+ sa_adc: process
+
+ variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
+ variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
+ variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
+ variable status: states := input ; -- Begin with "input" CASE
+ variable bit_cnt: integer := Nbits -1 ;
+
+ begin
+ CASE status is
+ when input => -- Read input voltages when start goes high
+ wait on start until start = '1' or start = 'H' ;
+ thresh := Vmax ;
+ Vtmp := Vin ;
+ eoc <= '0' ;
+ status := convert ; -- Go to convert state
+ when convert => -- Begin successive approximation conversion
+ thresh := thresh / 2.0 ; -- Get value of MSB
+ wait on clk until clk = '1' OR clk = 'H';
+ if Vtmp > thresh then
+ dtmp(bit_cnt) := '1' ;
+ Vtmp := Vtmp - thresh ;
+ else
+ dtmp(bit_cnt) := '0' ;
+ end if ;
+ if bit_cnt < 1 then
+ status := output ; -- Go to output state
+ end if;
+ bit_cnt := bit_cnt - 1 ;
+ when output => -- Wait for output enable, then put data on output pins
+ eoc <= '1' after delay ;
+ wait on oe until oe = '1' OR oe = 'H' ;
+ dout <= dtmp ;
+ wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
+ dout <= (others => 'Z') ;
+ bit_cnt := bit_range ;
+ status := input ; -- Set up for next conversion
+ END CASE ;
+ end process sa_adc ;
+
+ Iin == 0.0 ; -- Ideal input draws no current
+
+end architecture sar ;
+--
+
+-- Parallel input/serial output shift register
+-- With 4 trailing zeros
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity shift_reg is
+generic ( td : time := 0 ns);
+
+port
+(
+ bus_in : in std_logic_vector ; -- Input bus
+ clk : in std_logic ; -- Shift clock
+ oe : in std_logic ; -- Output enable
+ ser_out : out std_logic := '0'; -- Output port
+ load : in std_logic ; -- Parallel input load
+ clr : in std_logic -- Clear register
+);
+
+end entity shift_reg;
+
+architecture behavioral of shift_reg is
+begin
+
+control_proc : process
+ VARIABLE bit_val : std_logic_vector(11 downto 0); -- Default 12-bit input
+ begin
+
+ IF (clr = '1' OR clr = 'H') then
+ bit_val := "000000000000"; -- Set all input bits to zero
+ ELSE
+ wait until load'event AND (load = '1' OR load = 'H');
+ FOR i IN bus_in'high DOWNTO bus_in'low LOOP
+ bit_val(i) := bus_in(i) ; -- Transfer input data to variable
+ END LOOP ;
+ END IF;
+
+ wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
+ FOR i IN bit_val'high DOWNTO bit_val'low LOOP
+ wait until clk'event AND (clk = '1' OR clk = 'H');
+ ser_out <= bit_val(i) ;
+ END LOOP ;
+
+ FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros
+ wait until clk'event AND (clk = '1' OR clk = 'H');
+ ser_out <= '0';
+ END LOOP;
+
+END process;
+
+end architecture behavioral;
+--
+
+-- This model generates a 12-bit data frame synchronization code
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_gen is
+port
+(
+ oe : in std_logic := '0';
+ sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
+
+end entity frame_gen;
+
+architecture simple of frame_gen is
+begin
+ enbl: PROCESS
+ BEGIN
+ WAIT ON OE;
+ IF OE = '1' THEN
+ sync_out <= "010101010101"; -- Sync code
+ ELSE
+ sync_out <= "ZZZZZZZZZZZZ";
+ END IF;
+ END PROCESS;
+end architecture simple;
+--
+
+-- Two input XOR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY xor2 IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ in1, in2 : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY xor2;
+
+ARCHITECTURE ideal OF xor2 IS
+BEGIN
+ output <= in1 XOR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- level_set_tri.vhd
+-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
+-- If OE = '0' set output to high impedance
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set_tri IS
+
+ GENERIC (
+ logic_val : std_logic := 'Z');
+
+ PORT (
+ OE : IN std_logic;
+ level : OUT std_logic := 'Z');
+
+END ENTITY level_set_tri;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set_tri IS
+BEGIN
+ oe_ctl: PROCESS
+ BEGIN
+ WAIT ON OE;
+ IF OE = '1' THEN
+ level <= logic_val;
+ ELSE
+ level <= 'Z';
+ END IF;
+ END PROCESS;
+
+END ARCHITECTURE ideal;
+
+--
+
+-- Simple Tri-state Buffer with delay time
+-- If OE = 1, output = input after delay
+-- If OE /= 1, output = Z after delay
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY buffer_tri IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ input : IN std_logic;
+ OE : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY buffer_tri;
+
+ARCHITECTURE ideal OF buffer_tri IS
+BEGIN
+ oe_ctl: PROCESS
+ BEGIN
+ WAIT ON OE, input;
+ IF OE = '1' THEN
+ output <= input AFTER delay;
+ ELSE
+ output <= 'Z' AFTER delay;
+ END IF;
+ END PROCESS;
+END ARCHITECTURE ideal;
+--
+
+-- ideal one bit D/A converter
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY d2a_bit IS
+ GENERIC (vlow : real :=0.0; -- output high voltage
+ vhigh : real :=5.0); -- output low voltage
+ PORT (D : IN std_logic; -- digital (std_logic) intout
+ TERMINAL A : electrical); -- analog (electrical) output
+END ENTITY d2a_bit;
+
+ARCHITECTURE ideal OF d2a_bit IS
+ QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
+ SIGNAL vin : real := 0.0;
+
+ BEGIN
+ vin <= vhigh WHEN D = '1' ELSE vlow;
+ -- Use 'RAMP for discontinuous signal
+ vout == vin'RAMP(1.0e-9);
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_gen is
+ port(
+ parity : in std_logic_vector(1 to 10);
+ oe : in std_logic;
+ parity_out : out std_logic_vector(0 to 11)
+ );
+end parity_gen;
+
+architecture parity_gen of parity_gen is
+ -- Component declarations
+ -- Signal declarations
+ terminal par_bit_gen_a : electrical;
+ signal XSIG010002 : std_logic;
+ signal XSIG010003 : std_logic;
+ signal XSIG010004 : std_logic;
+ signal XSIG010005 : std_logic;
+ signal XSIG010006 : std_logic;
+ signal XSIG010007 : std_logic;
+ signal XSIG010008 : std_logic;
+ signal XSIG010009 : std_logic;
+ signal XSIG010098 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ XCMP1 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(1),
+ in2 => parity(2),
+ output => XSIG010002
+ );
+ XCMP2 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(3),
+ in2 => parity(4),
+ output => XSIG010003
+ );
+ XCMP3 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(5),
+ in2 => parity(6),
+ output => XSIG010004
+ );
+ XCMP4 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(7),
+ in2 => parity(8),
+ output => XSIG010005
+ );
+ XCMP5 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(9),
+ in2 => parity(10),
+ output => XSIG010008
+ );
+ XCMP6 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010002,
+ in2 => XSIG010003,
+ output => XSIG010006
+ );
+ XCMP7 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010004,
+ in2 => XSIG010005,
+ output => XSIG010007
+ );
+ XCMP8 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010006,
+ in2 => XSIG010007,
+ output => XSIG010009
+ );
+ XCMP9 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010009,
+ in2 => XSIG010008,
+ output => XSIG010098
+ );
+ XCMP18 : entity work.level_set_tri(ideal)
+ generic map(
+ logic_val => '1'
+ )
+ port map(
+ level => parity_out(11),
+ oe => oe
+ );
+ XCMP19 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(1),
+ output => parity_out(1),
+ oe => oe
+ );
+ XCMP20 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(2),
+ output => parity_out(2),
+ oe => oe
+ );
+ XCMP21 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(3),
+ output => parity_out(3),
+ oe => oe
+ );
+ XCMP22 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(4),
+ output => parity_out(4),
+ oe => oe
+ );
+ XCMP23 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(5),
+ output => parity_out(5),
+ oe => oe
+ );
+ XCMP24 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(6),
+ output => parity_out(6),
+ oe => oe
+ );
+ XCMP25 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(7),
+ output => parity_out(7),
+ oe => oe
+ );
+ XCMP26 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(8),
+ output => parity_out(8),
+ oe => oe
+ );
+ XCMP27 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(9),
+ output => parity_out(9),
+ oe => oe
+ );
+ XCMP28 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(10),
+ output => parity_out(10),
+ oe => oe
+ );
+ XCMP29 : entity work.buffer_tri(ideal)
+ port map(
+ input => XSIG010098,
+ output => parity_out(0),
+ oe => oe
+ );
+ XCMP30 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010098,
+ A => par_bit_gen_a
+ );
+end parity_gen;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tdm_encoder is
+ port(
+ clk : in std_logic;
+ p2s_oe : in std_logic;
+ p2s_load : in std_logic;
+ frm_gen : in std_logic;
+ parity_oe : in std_logic;
+ tdm_out : out std_logic;
+ p2s_clr : in std_logic;
+ a2d_data : in std_logic_vector(1 to 10)
+ );
+end tdm_encoder;
+
+architecture tdm_encoder of tdm_encoder is
+ -- Component declarations
+ -- Signal declarations
+ signal sync_par : std_logic_vector(0 to 11);
+begin
+ -- Signal assignments
+ -- Component instances
+ p2s1 : entity work.shift_reg(behavioral)
+ port map(
+ bus_in => sync_par,
+ clk => clk,
+ oe => p2s_oe,
+ ser_out => tdm_out,
+ load => p2s_load,
+ clr => p2s_clr
+ );
+ sync_gen1 : entity work.frame_gen(simple)
+ port map(
+ oe => frm_gen,
+ sync_out => sync_par
+ );
+ par_gen1 : entity work.parity_gen
+ port map(
+ parity => a2d_data,
+ parity_out => sync_par,
+ oe => parity_oe
+ );
+end tdm_encoder;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Digitize_Encode is
+ port(
+ tdm_out : out std_logic;
+ terminal ch1_in : electrical;
+ terminal ch2_in : electrical
+ );
+end Digitize_Encode;
+
+architecture Digitize_Encode of Digitize_Encode is
+ -- Component declarations
+ -- Signal declarations
+ terminal a2d_ana_in : electrical;
+ signal a2d_oe : std_logic;
+ signal ch_bus : std_logic_vector(1 to 10);
+ signal frm_gen_ctl : std_logic;
+ signal p2s_clr : std_logic;
+ signal p2s_load : std_logic;
+ signal p2s_oe : std_logic;
+ signal par_oe : std_logic;
+ signal start_a2d1 : std_logic;
+ signal sw_ctl : std_logic;
+ signal XSIG010091 : std_logic;
+ signal XSIG010173 : std_logic;
+ signal XSIG010180 : std_logic;
+ signal XSIG010181 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ A_SWITCH1 : entity work.switch_dig_2in(ideal)
+ port map(
+ p_in1 => ch1_in,
+ p_out => a2d_ana_in,
+ sw_state => sw_ctl,
+ p_in2 => ch2_in
+ );
+ rc_clk2 : entity work.rc_clk
+ port map(
+ clk_50 => XSIG010180,
+ clk_6K => XSIG010173,
+ clk_100k => XSIG010181
+ );
+ sm_xmtr1 : entity work.sm_cnt
+ port map(
+ clk_100k => XSIG010181,
+ a2d_start => start_a2d1,
+ a2d_eoc => XSIG010091,
+ p2s_oe => p2s_oe,
+ p2s_load => p2s_load,
+ ch_sel => sw_ctl,
+ frm_gen => frm_gen_ctl,
+ parity_oe => par_oe,
+ a2d_oe => a2d_oe,
+ clk_50 => XSIG010180,
+ clk_6k => XSIG010173,
+ p2s_clr => p2s_clr
+ );
+ a2d1 : entity work.a2d_nbit(sar)
+ generic map(
+ Vmax => 4.8
+ )
+ port map(
+ dout => ch_bus,
+ ain => a2d_ana_in,
+ clk => XSIG010181,
+ start => start_a2d1,
+ eoc => XSIG010091,
+ oe => a2d_oe
+ );
+ tdm_enc1 : entity work.tdm_encoder
+ port map(
+ clk => XSIG010173,
+ p2s_oe => p2s_oe,
+ tdm_out => tdm_out,
+ p2s_load => p2s_load,
+ a2d_data => ch_bus,
+ frm_gen => frm_gen_ctl,
+ parity_oe => par_oe,
+ p2s_clr => p2s_clr
+ );
+end Digitize_Encode;
+--
+
+-- Electrical sinusoidal voltage source (stick.vhd)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+
+ENTITY stick IS
+
+-- Initialize parameters
+ GENERIC (
+ freq : real; -- frequency, [Hertz]
+ amplitude : real; -- amplitude, [Volt]
+ phase : real := 0.0; -- initial phase, [Degree]
+ offset : real := 0.0; -- DC value, [Volt]
+ df : real := 0.0; -- damping factor, [1/second]
+ ac_mag : real := 1.0; -- AC magnitude, [Volt]
+ ac_phase : real := 0.0); -- AC phase, [Degree]
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL v_out : ELECTRICAL);
+
+END ENTITY stick;
+
+-- Ideal Architecture
+ARCHITECTURE ideal OF stick IS
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
+-- Declare Quantity for Phase in radians (calculated below)
+ QUANTITY phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+ QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+-- Convert phase to radians
+ phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+ IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
+ v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+ ELSE
+ v == ac_spec; -- used for Frequency (AC) analysis
+ END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-- Two input AND gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY and2 IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ in1, in2 : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY and2;
+
+ARCHITECTURE ideal OF and2 IS
+BEGIN
+ output <= in1 AND in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- D Flip Flop with reset (negative edge triggered)
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY d_latch_n_edge_rst IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ data, clk : IN std_logic;
+ q : OUT std_logic := '0';
+ qn : OUT std_logic := '1';
+ rst : IN std_logic := '0'); -- reset
+
+END ENTITY d_latch_n_edge_rst ;
+
+ARCHITECTURE behav OF d_latch_n_edge_rst IS
+BEGIN
+
+ data_in : PROCESS(clk, rst) IS
+
+ BEGIN
+ IF clk = '0' AND clk'event AND rst /= '1' THEN
+ q <= data AFTER delay;
+ qn <= NOT data AFTER delay;
+ ELSIF rst = '1' THEN
+ q <= '0';
+ qn <= '1';
+ END IF;
+
+ END PROCESS data_in; -- End of process data_in
+
+END ARCHITECTURE behav;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity counter_12 is
+ port(
+ cnt : out std_logic_vector(0 to 11);
+ reset : in std_logic;
+ enable : in std_logic;
+ clk : in std_logic
+ );
+end counter_12;
+
+architecture counter_12 of counter_12 is
+ -- Component declarations
+ -- Signal declarations
+ signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
+ signal XSIG010078 : std_logic;
+ signal XSIG010081 : std_logic;
+ signal XSIG010083 : std_logic;
+ signal XSIG010085 : std_logic;
+ signal XSIG010087 : std_logic;
+ signal XSIG010101 : std_logic;
+ signal XSIG010102 : std_logic;
+ signal XSIG010103 : std_logic;
+ signal XSIG010104 : std_logic;
+ signal XSIG010115 : std_logic;
+ signal XSIG010116 : std_logic;
+ signal XSIG010117 : std_logic;
+ signal XSIG010132 : std_logic;
+begin
+ -- Signal assignments
+ cnt(0) <= cdb2vhdl_tmp_1(0);
+ cnt(1) <= cdb2vhdl_tmp_1(1);
+ cnt(2) <= cdb2vhdl_tmp_1(2);
+ cnt(3) <= cdb2vhdl_tmp_1(3);
+ cnt(4) <= cdb2vhdl_tmp_1(4);
+ cnt(5) <= cdb2vhdl_tmp_1(5);
+ cnt(6) <= cdb2vhdl_tmp_1(6);
+ cnt(7) <= cdb2vhdl_tmp_1(7);
+ cnt(8) <= cdb2vhdl_tmp_1(8);
+ cnt(9) <= cdb2vhdl_tmp_1(9);
+ cnt(10) <= cdb2vhdl_tmp_1(10);
+ cnt(11) <= cdb2vhdl_tmp_1(11);
+ -- Component instances
+ XCMP92 : entity work.and2(ideal)
+ port map(
+ in1 => clk,
+ in2 => enable,
+ output => XSIG010132
+ );
+ XCMP93 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => XSIG010132,
+ DATA => XSIG010078,
+ QN => XSIG010078,
+ Q => cdb2vhdl_tmp_1(0),
+ RST => reset
+ );
+ XCMP94 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(0),
+ DATA => XSIG010081,
+ QN => XSIG010081,
+ Q => cdb2vhdl_tmp_1(1),
+ RST => reset
+ );
+ XCMP95 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(1),
+ DATA => XSIG010083,
+ QN => XSIG010083,
+ Q => cdb2vhdl_tmp_1(2),
+ RST => reset
+ );
+ XCMP96 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(2),
+ DATA => XSIG010085,
+ QN => XSIG010085,
+ Q => cdb2vhdl_tmp_1(3),
+ RST => reset
+ );
+ XCMP97 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(3),
+ DATA => XSIG010087,
+ QN => XSIG010087,
+ Q => cdb2vhdl_tmp_1(4),
+ RST => reset
+ );
+ XCMP98 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(4),
+ DATA => XSIG010101,
+ QN => XSIG010101,
+ Q => cdb2vhdl_tmp_1(5),
+ RST => reset
+ );
+ XCMP99 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(5),
+ DATA => XSIG010102,
+ QN => XSIG010102,
+ Q => cdb2vhdl_tmp_1(6),
+ RST => reset
+ );
+ XCMP100 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(6),
+ DATA => XSIG010103,
+ QN => XSIG010103,
+ Q => cdb2vhdl_tmp_1(7),
+ RST => reset
+ );
+ XCMP101 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(7),
+ DATA => XSIG010104,
+ QN => XSIG010104,
+ Q => cdb2vhdl_tmp_1(8),
+ RST => reset
+ );
+ XCMP102 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(8),
+ DATA => XSIG010115,
+ QN => XSIG010115,
+ Q => cdb2vhdl_tmp_1(9),
+ RST => reset
+ );
+ XCMP103 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(9),
+ DATA => XSIG010116,
+ QN => XSIG010116,
+ Q => cdb2vhdl_tmp_1(10),
+ RST => reset
+ );
+ XCMP104 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(10),
+ DATA => XSIG010117,
+ QN => XSIG010117,
+ Q => cdb2vhdl_tmp_1(11),
+ RST => reset
+ );
+end counter_12;
+--
+
+-- ideal one bit A/D converter
+
+LIBRARY IEEE;
+USE IEEE.math_real.ALL;
+USE IEEE.std_logic_1164.ALL;
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY a2d_bit IS
+
+ GENERIC (
+ thres : real := 2.5); -- Threshold to determine logic output
+
+ PORT (
+ TERMINAL a : electrical; -- analog input
+ SIGNAL d : OUT std_logic); -- digital (std_logic) output
+
+END ENTITY a2d_bit;
+
+
+ARCHITECTURE ideal OF a2d_bit IS
+
+ QUANTITY vin ACROSS a;
+
+ BEGIN -- threshold
+-- Process needed to detect threshold crossing and assign output (d)
+ PROCESS (vin'ABOVE(thres)) IS
+ BEGIN -- PROCESS
+ IF vin'ABOVE(thres) THEN
+ d <= '1';
+ ELSE
+ d <= '0';
+ END IF;
+ END PROCESS;
+
+END ideal;
+
+
+-- Digital clock with 50% duty cycle and enable pin
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock_en IS
+ GENERIC (
+ pw : time); -- Clock pulse width
+
+ PORT (
+ enable : IN std_logic ;
+ clock_out : INOUT std_logic := '0');
+
+END ENTITY clock_en;
+
+ARCHITECTURE ideal OF clock_en IS
+
+BEGIN
+
+-- clock process
+ process (clock_out, enable) is
+ begin
+ if clock_out = '0' AND enable = '1' THEN
+ clock_out <= '1' after pw, '0' after 2*pw;
+ end if;
+ end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- Inverter
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY inverter IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ input : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY inverter;
+
+ARCHITECTURE ideal OF inverter IS
+BEGIN
+ output <= NOT input AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- Two input OR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY or2 IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ in1, in2 : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY or2;
+
+ARCHITECTURE ideal OF or2 IS
+BEGIN
+ output <= in1 OR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY d2a_nbit IS
+
+ GENERIC (
+ vmax : real := 5.0; -- High output
+ vmin : real := 0.0; -- Low output
+ high_bit : integer := 9; -- High end of bit range for D/A
+ low_bit : integer := 0); -- Low end of bit range for D/A
+
+ PORT (
+ SIGNAL bus_in : IN STD_LOGIC_VECTOR; -- variable width vector input
+ SIGNAL latch : IN STD_LOGIC;
+ TERMINAL ana_out : electrical); -- analog output
+
+END ENTITY d2a_nbit ;
+
+ARCHITECTURE behavioral OF d2a_nbit IS
+
+ SIGNAL sout : real := 0.0;
+ QUANTITY vout across iout through ana_out TO electrical_ref;
+
+BEGIN -- ARCHITECTURE behavioral
+
+ proc : PROCESS
+
+ VARIABLE v_sum : real; -- Sum of voltage contribution from each bit
+ VARIABLE delt_v : real; -- Represents the voltage value of each bit
+
+ BEGIN
+ WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
+ v_sum := vmin;
+ delt_v := vmax - vmin;
+
+ FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
+ delt_v := delt_v / 2.0;
+ IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
+ v_sum := v_sum + delt_v;
+ END IF;
+ END LOOP;
+
+ sout <= v_sum;
+ END PROCESS;
+
+ vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
+
+END ARCHITECTURE behavioral;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pw2ana is
+ port(
+ terminal ana_out : electrical;
+ terminal pw_in : electrical
+ );
+end pw2ana;
+
+architecture pw2ana of pw2ana is
+ -- Component declarations
+ -- Signal declarations
+ signal bus_servo : std_logic_vector(0 to 11);
+ signal XSIG010008 : std_logic;
+ signal XSIG010013 : std_logic;
+ signal XSIG010019 : std_logic;
+ signal XSIG010020 : std_logic;
+ signal XSIG010021 : std_logic;
+ signal XSIG010022 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ counter_rudder : entity work.counter_12
+ port map(
+ enable => XSIG010022,
+ cnt => bus_servo,
+ reset => XSIG010021,
+ clk => XSIG010008
+ );
+ XCMP3 : entity work.a2d_bit(ideal)
+ port map(
+ D => XSIG010022,
+ A => pw_in
+ );
+ clk_en_rudder : entity work.clock_en(ideal)
+ generic map(
+ pw => 500ns
+ )
+ port map(
+ CLOCK_OUT => XSIG010008,
+ enable => XSIG010022
+ );
+ XCMP5 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => XSIG010022,
+ output => XSIG010013
+ );
+ XCMP8 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => XSIG010020,
+ output => XSIG010021
+ );
+ XCMP9 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => XSIG010022,
+ output => XSIG010019
+ );
+ or_rudder : entity work.or2(ideal)
+ port map(
+ in1 => XSIG010022,
+ in2 => XSIG010019,
+ output => XSIG010020
+ );
+ DA1 : entity work.d2a_nbit(behavioral)
+ generic map(
+ vmax => 4.8,
+ high_bit => 9,
+ low_bit => 0
+ )
+ port map(
+ bus_in => bus_servo,
+ ana_out => ana_out,
+ latch => XSIG010013
+ );
+end pw2ana;
+--
+
+-- 12-bit digital comparator model
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+entity dig_cmp is
+port
+(
+ eq : out std_logic := '0';
+ in1 : in std_logic_vector (0 to 11);
+ in2 : in std_logic_vector (0 to 11);
+ latch_in1 : in std_logic := '0'; -- Currently unused
+ latch_in2 : in std_logic := '0';
+ cmp : in std_logic := '0';
+ clk : in std_logic
+ );
+
+end entity dig_cmp ;
+
+architecture simple of dig_cmp is
+
+begin
+
+ compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
+ variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
+ BEGIN
+ if latch_in2 = '1' then -- in2 data is latched and stored
+ in2_hold := in2;
+ end if;
+ if cmp = '1' then
+ if in1 = in2_hold then -- latched in2 checked against current in1
+ eq <= '0';
+ else eq <= '1';
+ end if;
+ end if;
+ END PROCESS;
+end architecture simple;
+
+-- Set/reset flip flop
+-- When S goes high, Q is set high until reset
+-- When R goes high, Q is set low until set
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sr_ff is
+port
+(
+ S : in std_logic ;
+ R : in std_logic ;
+ Q : out std_logic
+);
+
+end sr_ff ;
+
+architecture simple of sr_ff is
+begin
+
+ set_reset: PROCESS(S, R) IS
+
+ BEGIN
+-- assert S='1' nand R='1' -- Warning if both inputs are high
+-- report "S and R are both active. Use with caution"
+-- severity warning;
+ if S'event AND S = '1' then
+ Q <= '1';
+ end if;
+ if R'event AND R = '1' then
+ Q <= '0';
+ end if;
+ END PROCESS set_reset;
+
+end;
+--
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+
+ENTITY state_mach_rcvr IS
+ PORT (
+ clk_50 : IN std_logic;
+ clk_100k : IN std_logic;
+ ser_done : IN std_logic;
+ par_det : IN std_logic;
+ frm_det : IN std_logic;
+ clk_6k : IN std_logic;
+ start_pulse : IN std_logic;
+ dly_done : IN std_logic;
+ s2p_rst : OUT std_logic;
+ s2p_en : OUT std_logic;
+ cnt1_en : OUT std_logic;
+ cnt1_rst : OUT std_logic;
+ cmp1_ltch1 : OUT std_logic;
+ cmp1_ltch2 : OUT std_logic;
+ cnt2_en : OUT std_logic;
+ cnt2_rst : OUT std_logic;
+ cmp2_ltch1 : OUT std_logic;
+ cmp2_ltch2 : OUT std_logic;
+ da_latch : OUT std_logic;
+ ser_cnt : OUT std_logic;
+ dly_cnt : OUT std_logic;
+ par_oe : OUT std_logic);
+
+END state_mach_rcvr;
+
+ARCHITECTURE state_diagram OF state_mach_rcvr IS
+
+ ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+ TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
+ , s_bit, par1, par2);
+ SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
+
+
+BEGIN
+
+sm1:
+ PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det)
+ BEGIN
+
+ CASE CS_state_mach_rcvr_sm1 IS
+ WHEN V_begin =>
+ cnt1_en <= ('0');
+ cnt1_rst <= ('1');
+ cmp1_ltch1 <= ('0');
+ cmp1_ltch2 <= ('0');
+ cnt2_en <= ('0');
+ cnt2_rst <= ('1');
+ cmp2_ltch1 <= ('0');
+ cmp2_ltch2 <= ('0');
+ s2p_en <= ('1');
+ s2p_rst <= ('0');
+ da_latch <= ('0');
+ ser_cnt <= ('0');
+ dly_cnt <= ('0');
+ par_oe <= ('0');
+
+ IF ((frm_det = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= s_bit;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= V_begin;
+ END IF;
+
+ WHEN cnt =>
+ ser_cnt <= ('1');
+ cnt1_rst <= ('0');
+ cnt2_rst <= ('0');
+
+ IF ((ser_done = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= par1;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= cnt;
+ END IF;
+
+ WHEN ch1 =>
+ cmp1_ltch2 <= ('1');
+ ser_cnt <= ('0');
+ dly_cnt <= ('1');
+
+ IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
+ NS_state_mach_rcvr_sm1 <= rst1;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= ch1;
+ END IF;
+
+ WHEN rst1 =>
+ cmp1_ltch2 <= ('0');
+ ser_cnt <= ('1');
+ dly_cnt <= ('0');
+ par_oe <= ('0');
+
+ IF ((ser_done = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= par2;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= rst1;
+ END IF;
+
+ WHEN ch2 =>
+ cmp2_ltch2 <= ('1');
+ ser_cnt <= ('0');
+ da_latch <= ('1');
+ NS_state_mach_rcvr_sm1 <= rst2;
+
+ WHEN rst2 =>
+ cmp2_ltch2 <= ('0');
+ s2p_en <= ('0');
+ par_oe <= ('0');
+ da_latch <= ('0');
+ NS_state_mach_rcvr_sm1 <= cnt_cmp;
+
+ WHEN cnt_cmp =>
+ cnt1_en <= ('1');
+ cmp1_ltch1 <= ('1');
+ cnt2_en <= ('1');
+ cmp2_ltch1 <= ('1');
+ NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+ WHEN rst_cnt =>
+ cnt1_en <= ('0');
+ cmp1_ltch1 <= ('0');
+ cnt2_en <= ('0');
+ cmp2_ltch1 <= ('0');
+ NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+ WHEN s_bit =>
+
+ IF ((start_pulse = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= cnt;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= s_bit;
+ END IF;
+
+ WHEN par1 =>
+ par_oe <= ('1');
+
+ IF ((par_det = '0')) THEN
+ NS_state_mach_rcvr_sm1 <= ch1;
+ ELSIF ((par_det = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= rst1;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= par1;
+ END IF;
+
+ WHEN par2 =>
+ par_oe <= ('1');
+
+ IF ((par_det = '0')) THEN
+ NS_state_mach_rcvr_sm1 <= ch2;
+ ELSIF ((par_det = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= rst2;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= par2;
+ END IF;
+
+ END CASE;
+
+ END PROCESS;
+
+sm1_CTL:
+ PROCESS (clk_100k, clk_50)
+ BEGIN
+
+ IF (clk_100k'event AND clk_100k='1') THEN
+ IF (clk_50= '1' ) THEN
+ CS_state_mach_rcvr_sm1 <= V_begin;
+ ELSE
+ CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
+ END IF;
+ END IF;
+
+ END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt_rcvr is
+ port(
+ cmp1_ltch1 : out std_logic;
+ cmp2_ltch1 : out std_logic;
+ s2p_en : out std_logic;
+ s2p_rst : out std_logic;
+ frm_det : in std_logic;
+ par_det : in std_logic;
+ clk_100k : in std_logic;
+ clk_6k : in std_logic;
+ clk_50 : in std_logic;
+ start_pulse : in std_logic;
+ cnt1_en : out std_logic;
+ cnt1_rst : out std_logic;
+ cmp1_ltch2 : out std_logic;
+ cnt2_en : out std_logic;
+ cnt2_rst : out std_logic;
+ cmp2_ltch2 : out std_logic;
+ da_latch : out std_logic;
+ par_oe : out std_logic
+ );
+end sm_cnt_rcvr;
+
+architecture sm_cnt_rcvr of sm_cnt_rcvr is
+ -- Component declarations
+ -- Signal declarations
+ signal ser_cnt : std_logic;
+ signal XSIG010002 : std_logic;
+ signal XSIG010145 : std_logic;
+ signal XSIG010146 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ bit_cnt3 : entity work.bit_cnt(behavioral)
+ generic map(
+ count => 2
+ )
+ port map(
+ bit_in => XSIG010145,
+ clk => clk_6k,
+ dly_out => XSIG010146
+ );
+ bit_cnt4 : entity work.bit_cnt(behavioral)
+ generic map(
+ count => 10
+ )
+ port map(
+ bit_in => ser_cnt,
+ clk => clk_6k,
+ dly_out => XSIG010002
+ );
+ state_mach_rcvr8 : entity work.state_mach_rcvr
+ port map(
+ clk_100k => clk_100k,
+ clk_50 => clk_50,
+ s2p_rst => s2p_rst,
+ s2p_en => s2p_en,
+ cnt1_en => cnt1_en,
+ cnt1_rst => cnt1_rst,
+ cmp1_ltch1 => cmp1_ltch1,
+ cmp1_ltch2 => cmp1_ltch2,
+ cnt2_en => cnt2_en,
+ cnt2_rst => cnt2_rst,
+ cmp2_ltch1 => cmp2_ltch1,
+ cmp2_ltch2 => cmp2_ltch2,
+ da_latch => da_latch,
+ ser_cnt => ser_cnt,
+ ser_done => XSIG010002,
+ par_det => par_det,
+ frm_det => frm_det,
+ clk_6k => clk_6k,
+ start_pulse => start_pulse,
+ dly_done => XSIG010146,
+ dly_cnt => XSIG010145,
+ par_oe => par_oe
+ );
+end sm_cnt_rcvr;
+--
+-- level_set.vhd
+-- Set digital output "level" with parameter "logic_val" (default is '1')
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set IS
+
+ GENERIC (
+ logic_val : std_logic := '1');
+
+ PORT (
+ level : OUT std_logic);
+
+END ENTITY level_set;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set IS
+
+BEGIN
+
+ level <= logic_val;
+
+END ARCHITECTURE ideal;
+
+--
+-- Serial to parallel data converter
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity ser2par is
+port
+(
+ par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
+ clk : in std_logic ;
+ load_en : in std_logic ;
+ ser_in : in std_logic ;
+ reset : in std_logic
+);
+
+begin
+
+end ser2par;
+
+architecture a1 of ser2par is
+BEGIN
+ sr_sm: PROCESS (load_en, clk, reset, ser_in)
+ BEGIN
+ if (reset = '1' and load_en = '1') then
+ par_out <= "000000000000"; -- Reset the parallel data out
+
+ elsif (reset = '0' and load_en = '1') then
+ if (clk'event and clk = '1') then
+
+ -- The register will shift when load is enabled
+ -- and will shift at rising edge of clock
+
+ par_out(0) <= ser_in; -- Input data shifts into bit 0
+ par_out(1) <= par_out(0);
+ par_out(2) <= par_out(1);
+ par_out(3) <= par_out(2);
+ par_out(4) <= par_out(3);
+ par_out(5) <= par_out(4);
+ par_out(6) <= par_out(5);
+ par_out(7) <= par_out(6);
+ par_out(8) <= par_out(7);
+ par_out(9) <= par_out(8);
+ par_out(10) <= par_out(9);
+ par_out(11) <= par_out(10);
+
+ end if;
+
+ else
+ par_out <= "ZZZZZZZZZZZZ"; -- No change in output. Tri-state if load_en = 0.
+ end if;
+ END PROCESS;
+end;
+
+--
+-- This model ouputs a '1' when a specific bit pattern is encountered
+-- Otherwise, it outputs a zero
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_det is
+port
+(
+ bus_in : in std_logic_vector (0 to 11);
+ clk : in std_logic;
+ frm_bit : out std_logic := '0' -- Initialize output to zero
+ );
+
+end entity frame_det;
+
+architecture simple of frame_det is
+begin
+ enbl: PROCESS (bus_in, clk) -- Sensitivity list
+ BEGIN
+ if bus_in = "010101010101" then -- This is the pre-defined bit pattern
+ if clk'event AND clk = '0' then -- Output updated synchronously
+ frm_bit <= '1';
+ end if;
+ else frm_bit <= '0';
+ end if;
+ END PROCESS;
+end architecture simple;
+
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_det is
+ port(
+ bus_in : in std_logic_vector(0 to 11);
+ par_bit : out std_logic;
+ oe : in std_logic
+ );
+end parity_det;
+
+architecture parity_det of parity_det is
+ -- Component declarations
+ -- Signal declarations
+ signal XSIG010010 : std_logic;
+ signal XSIG010011 : std_logic;
+ signal XSIG010012 : std_logic;
+ signal XSIG010013 : std_logic;
+ signal XSIG010014 : std_logic;
+ signal XSIG010015 : std_logic;
+ signal XSIG010016 : std_logic;
+ signal XSIG010017 : std_logic;
+ signal XSIG010019 : std_logic;
+ signal XSIG010057 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ XCMP1 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(1),
+ in2 => bus_in(2),
+ output => XSIG010010
+ );
+ XCMP2 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(3),
+ in2 => bus_in(4),
+ output => XSIG010011
+ );
+ XCMP3 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(5),
+ in2 => bus_in(6),
+ output => XSIG010012
+ );
+ XCMP4 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(7),
+ in2 => bus_in(8),
+ output => XSIG010013
+ );
+ XCMP5 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(9),
+ in2 => bus_in(10),
+ output => XSIG010016
+ );
+ XCMP6 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010010,
+ in2 => XSIG010011,
+ output => XSIG010014
+ );
+ XCMP7 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010012,
+ in2 => XSIG010013,
+ output => XSIG010015
+ );
+ XCMP8 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010014,
+ in2 => XSIG010015,
+ output => XSIG010017
+ );
+ XCMP9 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010017,
+ in2 => XSIG010016,
+ output => XSIG010019
+ );
+ XCMP10 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010019,
+ in2 => bus_in(0),
+ output => XSIG010057
+ );
+ XCMP12 : entity work.and2(ideal)
+ port map(
+ in1 => oe,
+ in2 => XSIG010057,
+ output => par_bit
+ );
+end parity_det;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TDM_Demux_dbg is
+ port(
+ s2p_en : in std_logic;
+ tdm_in : in std_logic;
+ clk_6k : in std_logic;
+ s2p_rst : in std_logic;
+ par_det : out std_logic;
+ frm_det : out std_logic;
+ da_latch : in std_logic;
+ par_oe : in std_logic;
+ data_bus : out std_logic_vector(1 to 10);
+ start_bit : out std_logic
+ );
+end TDM_Demux_dbg;
+
+architecture TDM_Demux_dbg of TDM_Demux_dbg is
+ -- Component declarations
+ -- Signal declarations
+ terminal d2a_out : electrical;
+ signal rcvr_bus : std_logic_vector(0 to 11);
+begin
+ -- Signal assignments
+ data_bus(1) <= rcvr_bus(1);
+ data_bus(2) <= rcvr_bus(2);
+ data_bus(3) <= rcvr_bus(3);
+ data_bus(4) <= rcvr_bus(4);
+ data_bus(5) <= rcvr_bus(5);
+ data_bus(6) <= rcvr_bus(6);
+ data_bus(7) <= rcvr_bus(7);
+ data_bus(8) <= rcvr_bus(8);
+ data_bus(9) <= rcvr_bus(9);
+ data_bus(10) <= rcvr_bus(10);
+ start_bit <= rcvr_bus(0);
+ -- Component instances
+ s2p1 : entity work.ser2par(a1)
+ port map(
+ par_out => rcvr_bus,
+ clk => clk_6k,
+ load_en => s2p_en,
+ ser_in => tdm_in,
+ reset => s2p_rst
+ );
+ frm_det1 : entity work.frame_det(simple)
+ port map(
+ bus_in => rcvr_bus,
+ frm_bit => frm_det,
+ clk => clk_6k
+ );
+ par_det1 : entity work.parity_det
+ port map(
+ bus_in => rcvr_bus,
+ par_bit => par_det,
+ oe => par_oe
+ );
+ XCMP113 : entity work.d2a_nbit(behavioral)
+ generic map(
+ low_bit => 1,
+ high_bit => 10,
+ vmax => 4.8
+ )
+ port map(
+ bus_in => rcvr_bus(1 to 10),
+ ana_out => d2a_out,
+ latch => da_latch
+ );
+end TDM_Demux_dbg;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Decode_PW is
+ port(
+ bit_stream_in : in std_logic;
+ terminal ch1_pw : electrical;
+ terminal ch2_pw : electrical
+ );
+end Decode_PW;
+
+architecture Decode_PW of Decode_PW is
+ -- Component declarations
+ -- Signal declarations
+ signal cmp_bus : std_logic_vector(0 to 11);
+ signal cnt1 : std_logic_vector(0 to 11);
+ signal cnt2 : std_logic_vector(0 to 11);
+ signal rud_clk : std_logic;
+ signal rud_cmp : std_logic;
+ signal rud_eq : std_logic;
+ signal rud_ff_rst : std_logic;
+ signal rud_ff_set : std_logic;
+ signal rud_ltch1 : std_logic;
+ signal rud_ltch2 : std_logic;
+ signal XSIG010225 : std_logic;
+ signal XSIG010228 : std_logic;
+ signal XSIG010229 : std_logic;
+ signal XSIG010256 : std_logic;
+ signal XSIG010266 : std_logic;
+ signal XSIG010267 : std_logic;
+ signal XSIG010268 : std_logic;
+ signal XSIG010289 : std_logic;
+ signal XSIG010315 : std_logic;
+ signal XSIG010339 : std_logic;
+ signal XSIG010357 : std_logic;
+ signal XSIG010371 : std_logic;
+ signal XSIG010373 : std_logic;
+ signal XSIG010383 : std_logic;
+ signal XSIG010384 : std_logic;
+ signal XSIG010385 : std_logic;
+ signal XSIG010386 : std_logic;
+ signal XSIG010390 : std_logic;
+ signal XSIG010433 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ cntr1 : entity work.counter_12
+ port map(
+ enable => XSIG010384,
+ cnt => cnt1,
+ reset => XSIG010357,
+ clk => XSIG010433
+ );
+ cntr2 : entity work.counter_12
+ port map(
+ enable => rud_cmp,
+ cnt => cnt2,
+ reset => XSIG010385,
+ clk => rud_clk
+ );
+ cmp1 : entity work.dig_cmp(simple)
+ port map(
+ in1 => cnt1,
+ eq => XSIG010371,
+ clk => XSIG010433,
+ in2 => cmp_bus,
+ cmp => XSIG010384,
+ latch_in1 => XSIG010256,
+ latch_in2 => XSIG010383
+ );
+ cmp2 : entity work.dig_cmp(simple)
+ port map(
+ in1 => cnt2,
+ eq => rud_eq,
+ clk => rud_clk,
+ in2 => cmp_bus,
+ cmp => rud_cmp,
+ latch_in1 => rud_ltch1,
+ latch_in2 => rud_ltch2
+ );
+ clk_1M2 : entity work.clock_en(ideal)
+ generic map(
+ pw => 500 ns
+ )
+ port map(
+ CLOCK_OUT => rud_clk,
+ enable => rud_cmp
+ );
+ clk_1M1 : entity work.clock_en(ideal)
+ generic map(
+ pw => 500 ns
+ )
+ port map(
+ CLOCK_OUT => XSIG010433,
+ enable => XSIG010384
+ );
+ XCMP134 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010371,
+ A => ch1_pw
+ );
+ XCMP135 : entity work.d2a_bit(ideal)
+ port map(
+ D => rud_eq,
+ A => ch2_pw
+ );
+ XCMP137 : entity work.SR_FF(simple)
+ port map(
+ S => rud_ff_set,
+ R => rud_ff_rst,
+ Q => rud_cmp
+ );
+ XCMP138 : entity work.inverter(ideal)
+ port map(
+ input => rud_eq,
+ output => rud_ff_rst
+ );
+ XCMP139 : entity work.SR_FF(simple)
+ port map(
+ S => XSIG010373,
+ R => XSIG010339,
+ Q => XSIG010384
+ );
+ XCMP140 : entity work.inverter(ideal)
+ port map(
+ input => XSIG010371,
+ output => XSIG010339
+ );
+ rc_clk2 : entity work.rc_clk
+ port map(
+ clk_50 => XSIG010289,
+ clk_6K => XSIG010225,
+ clk_100k => XSIG010315
+ );
+ sm_rcvr1 : entity work.sm_cnt_rcvr
+ port map(
+ cnt1_en => XSIG010373,
+ cmp1_ltch1 => XSIG010256,
+ cnt2_rst => XSIG010385,
+ clk_100k => XSIG010315,
+ cnt1_rst => XSIG010357,
+ cnt2_en => rud_ff_set,
+ cmp2_ltch1 => rud_ltch1,
+ frm_det => XSIG010229,
+ par_det => XSIG010228,
+ s2p_en => XSIG010266,
+ s2p_rst => XSIG010267,
+ clk_6k => XSIG010225,
+ clk_50 => XSIG010289,
+ da_latch => XSIG010268,
+ cmp1_ltch2 => XSIG010383,
+ cmp2_ltch2 => rud_ltch2,
+ start_pulse => XSIG010390,
+ par_oe => XSIG010386
+ );
+ XCMP155 : entity work.level_set(ideal)
+ generic map(
+ logic_val => '0'
+ )
+ port map(
+ level => cmp_bus(11)
+ );
+ XCMP157 : entity work.TDM_Demux_dbg
+ port map(
+ data_bus => cmp_bus(0 to 9),
+ tdm_in => bit_stream_in,
+ clk_6k => XSIG010225,
+ s2p_en => XSIG010266,
+ s2p_rst => XSIG010267,
+ da_latch => XSIG010268,
+ frm_det => XSIG010229,
+ par_det => XSIG010228,
+ par_oe => XSIG010386,
+ start_bit => XSIG010390
+ );
+ XCMP172 : entity work.level_set(ideal)
+ generic map(
+ logic_val => '1'
+ )
+ port map(
+ level => cmp_bus(10)
+ );
+end Decode_PW;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CS1 is
+end tb_CS1;
+
+architecture TB_CS1 of tb_CS1 is
+ -- Component declarations
+ -- Signal declarations
+ terminal rudder : electrical;
+ terminal rudder_out : electrical;
+ terminal rudder_servo : electrical;
+ signal tdm_stream2 : std_logic;
+ terminal throttle : electrical;
+ terminal throttle_out : electrical;
+ terminal throttle_servo : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ Digitize_Encode1 : entity work.Digitize_Encode
+ port map(
+ ch2_in => rudder,
+ ch1_in => throttle,
+ tdm_out => tdm_stream2
+ );
+ throttle_1 : entity work.stick(ideal)
+ generic map(
+ freq => 1.0,
+ amplitude => 2.397,
+ phase => 0.0,
+ offset => 2.397
+ )
+ port map(
+ v_out => throttle
+ );
+ rudder_1 : entity work.stick(ideal)
+ generic map(
+ offset => 2.397,
+ phase => 90.0,
+ amplitude => 2.397,
+ freq => 1.0
+ )
+ port map(
+ v_out => rudder
+ );
+ pw2ana1 : entity work.pw2ana
+ port map(
+ ana_out => throttle_out,
+ pw_in => throttle_servo
+ );
+ pw2ana2 : entity work.pw2ana
+ port map(
+ ana_out => rudder_out,
+ pw_in => rudder_servo
+ );
+ Decode_PW10 : entity work.Decode_PW
+ port map(
+ bit_stream_in => tdm_stream2,
+ ch2_pw => rudder_servo,
+ ch1_pw => throttle_servo
+ );
+end TB_CS1;
+-- \ No newline at end of file
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_a2d_d2a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_a2d_d2a.vhd
new file mode 100644
index 000000000..0a9d3f78e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_a2d_d2a.vhd
@@ -0,0 +1,134 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_a2d_d2a is
+
+end tb_a2d_d2a;
+
+architecture TB_a2d_d2a of tb_a2d_d2a is
+ -- Component declarations
+ -- Signal declarations
+ terminal ana_out : electrical;
+ terminal analog_in : electrical;
+ signal clock : std_ulogic;
+ signal start : std_ulogic;
+ signal eoc : std_ulogic;
+ signal eoc_logic: std_logic;
+ signal oe : std_logic;
+ signal data_bus : std_ulogic_vector(0 to 9);
+ signal latch : std_ulogic;
+ signal latch_logic : std_logic;
+ signal nn_eoc : std_logic;
+ signal or_out : std_logic;
+ signal n_eoc : std_logic;
+begin
+ -- Signal assignments
+ eoc_logic <= To_X01Z(eoc); -- convert std_ulogic to std_logic
+ latch <= To_X01(latch_logic); -- convert std_logic to std_ulogic
+ -- Component instances
+ ad1 : entity work.a2d_nbit(sar)
+ port map(
+ dout => data_bus,
+ ain => analog_in,
+ clk => clock,
+ start => start,
+ eoc => eoc
+ );
+ v1 : entity work.v_sine(ideal)
+ generic map(
+ freq => 2.5,
+ amplitude => 2.5,
+ offset => 2.5,
+ phase => 0.0
+ )
+ port map(
+ pos => analog_in,
+ neg => ELECTRICAL_REF
+ );
+ inv1 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => or_out,
+ output => oe
+ );
+ inv2 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => n_eoc,
+ output => nn_eoc
+ );
+ or1 : entity work.or2(ideal)
+ port map(
+ in1 => n_eoc,
+ in2 => nn_eoc,
+ output => or_out
+ );
+ inv3 : entity work.inverter(ideal)
+ generic map(
+ delay => 0us
+ )
+ port map(
+ input => eoc_logic,
+ output => n_eoc
+ );
+ U2 : entity work.buff(ideal)
+ generic map(
+ delay => 250ns
+ )
+ port map(
+ input => oe,
+ output => latch_logic
+ );
+ da1 : entity work.dac_10_bit(behavioral)
+ port map(
+ bus_in => data_bus,
+ analog_out => ana_out,
+ clk => latch
+ );
+ -- clock
+ P_clock :
+ process
+ begin
+ clock <= '1';
+ wait for 50.0 us;
+ clock <= '0';
+ wait for 50.0 us;
+ end process P_clock;
+
+ -- start
+ P_start :
+ process
+ begin
+ start <= '0';
+ wait for 2.0 ms;
+ start <= '1';
+ wait for 0.2 ms;
+ start <= '0';
+ wait for 2.0 ms;
+ end process P_start;
+
+
+end TB_a2d_d2a;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/DC_Motor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/DC_Motor.vhd
new file mode 100644
index 000000000..c25cacdd1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/DC_Motor.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.mechanical_systems.all;
+use ieee_proposed.electrical_systems.all;
+
+entity DC_Motor is
+ generic ( r_wind : resistance; -- motor winding resistance [ohm]
+ kt : real; -- torque coefficient [N*m/amp]
+ l : inductance; -- winding inductance [henrys]
+ d : real; -- damping coefficient [N*m/(rad/sec)]
+ j : mmoment_i ); -- moment of inertia [kg*meter**2]
+ port ( terminal p1, p2 : electrical;
+ terminal shaft_rotv : rotational_v);
+end entity DC_Motor;
+
+----------------------------------------------------------------
+
+architecture basic of DC_Motor is
+
+ quantity v across i through p1 to p2;
+ quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+ torq == -1.0 * kt * i + d * w + j * w'dot;
+ v == kt * w + i * r_wind + l * i'dot;
+
+end architecture basic;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain.vhd
new file mode 100644
index 000000000..90f1f04bd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity gain is
+ generic ( k : real := 1.0 ); -- gain multiplier
+ port ( quantity input : in real;
+ quantity output : out real );
+end entity gain;
+
+----------------------------------------------------------------
+
+architecture simple of gain is
+begin
+
+ output == k * input;
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain_e.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain_e.vhd
new file mode 100644
index 000000000..7054f2bae
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain_e.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity gain_e is
+ generic ( k : real := 1.0); -- gain multiplier
+ port ( terminal input : electrical;
+ terminal output : electrical );
+end entity gain_e;
+
+----------------------------------------------------------------
+
+architecture simple of gain_e is
+
+ quantity vin across input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+
+begin
+
+ vout == k * vin;
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gear_rv_r.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gear_rv_r.vhd
new file mode 100644
index 000000000..39ac481b6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gear_rv_r.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+ generic ( ratio : real := 1.0 ); -- gear ratio (revs of shaft2 for 1 rev of shaft1)
+ -- note: can be negative, if shaft polarity changes
+ port ( terminal rotv1 : rotational_v; -- rotational velocity terminal
+ terminal rot2 : rotational ); -- rotational angle terminal
+end entity gear_rv_r;
+
+----------------------------------------------------------------
+
+architecture ideal of gear_rv_r is
+
+ quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+ quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+ theta == ratio * w1'integ; -- output is angle (integral of w1)
+ torq_vel == -1.0 * torq_ang * ratio; -- input torque as function of output angle
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/index-ams.txt
new file mode 100644
index 000000000..241855fcb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/index-ams.txt
@@ -0,0 +1,77 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 14 - Case Study 2: Mixed-Technology Focus
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+gain.vhd entity gain simple Figure 14-3
+gain_e.vhd entity gain_e simple Figure 14-4
+sum2.vhd entity sum2 simple Figure 14-6
+limiter.vhd entity limiter simple Figure 14-7
+lpf_1.vhd entity lpf_1 simple Figure 14-9
+lead_lag.vhd entity lead_lag simple Figure 14-18
+DC_Motor.vhd entity DC_Motor basic Figure 14-21
+gear_rv_r.vhd entity gear_rv_r ideal Figure 14-22
+stop_r.vhd entity stop_r ideal Fgiure 14-23
+lead_lag_ztf.vhd entity lead_lag_ztf simple Figure 14-27
+lead_lag_diff.vhd entity lead_lag_diff bhv Figure 14-30
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_CS2_Mech_Domain.vhd entity sum2_e simple
+-- entity gain_e simple
+-- entity lead_lag_e simple
+-- entity limiter_2_e simple
+-- entity rudder_servo rudder_servo
+-- entity gear_rv_r ideal
+-- entity rot2v bhv
+-- entity horn_r2t bhv
+-- entity horn_t2r bhv
+-- entity DC_Motor basic
+-- entity stop_r ideal
+-- entity tran_linkage a1
+-- entity rudder bhv
+-- entity v_sine ideal
+-- entity TB_CS2_Mech_Domain TB_CS2_Mech_Domain
+tb_CS2_S_Domain.vhd entity v_sine ideal
+-- entity sum2_e simple
+-- entity lead_lag_e simple
+-- entity gain_e simple
+-- entity limiter_2_e simple
+-- entity ctl_horn_e bhv
+-- entity rudder_horn_e bhv
+-- entity integ_1_e simple
+-- entity lpf_1_e simple
+-- entity TB_CS2_S_Domain TB_CS2_S_Domain
+tb_CS2_Z_Domain_Diff.vhd entity gear_rv_r ideal
+-- entity rot2v bhv
+-- entity horn_r2t bhv
+-- entity horn_t2r bhv
+-- entity DC_Motor basic
+-- entity stop_r ideal
+-- entity tran_linkage a1
+-- entity rudder bhv
+-- entity sum2_e simple
+-- entity gain_e simple
+-- entity limiter_2_e simple
+-- entity clock ideal
+-- entity lead_lag_diff bhv
+-- entity rudder_servo_z rudder_servo_z
+-- entity v_sine ideal
+-- entity TB_CS2_Z_Domain_Diff TB_CS2_Z_Domain_Diff
+tb_CS2_Z_Domain_ZTF.vhd entity gear_rv_r ideal
+-- entity rot2v bhv
+-- entity horn_r2t bhv
+-- entity horn_t2r bhv
+-- entity DC_Motor basic
+-- entity stop_r ideal
+-- entity tran_linkage a1
+-- entity rudder bhv
+-- entity sum2_e simple
+-- entity gain_e simple
+-- entity limiter_2_e simple
+-- entity lead_lag_ztf simple
+-- entity rudder_servo_ztf rudder_servo_ztf
+-- entity v_sine ideal
+-- entity TB_CS2_Z_Domain_ZTF TB_CS2_Z_Domain_ZTF
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag.vhd
new file mode 100644
index 000000000..53c27dc69
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+
+entity lead_lag is
+ generic ( k : real := 400.0; -- gain multiplier
+ f1 : real := 5.0; -- break frequency (zero)
+ f2 : real := 2000.0); -- break frequency (pole)
+ port ( quantity input : in real;
+ quantity output : out real);
+end entity lead_lag;
+
+----------------------------------------------------------------
+
+architecture simple of lead_lag is
+
+ constant num : real_vector := (f1 * math_2_pi, 1.0);
+ constant den : real_vector := (f2 * math_2_pi, 1.0);
+
+begin
+
+ output == k * input'ltf(num, den);
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_diff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_diff.vhd
new file mode 100644
index 000000000..8692420e2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_diff.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity lead_lag_diff is
+ port ( signal clk : in std_logic; -- clock
+ quantity input : in real;
+ quantity output : out real );
+end entity lead_lag_diff;
+
+----------------------------------------------------------------
+
+architecture bhv of lead_lag_diff is
+
+ constant k : real := 400.0; -- normalize gain
+ signal z_out : real := 0.0;
+
+begin
+
+ proc : process (clk)
+ variable zi_dly1 : real := 0.0; -- input delayed 1 clk cycle
+ variable zo_dly1 : real := 0.0; -- output delayed 1 clk cycle
+ variable z_new : real := 0.0; -- new output value this clk cycle
+ begin
+ zo_dly1 := z_out; -- store previous output value
+ z_new := 0.6163507 * input - 0.6144184 * zi_dly1 + 0.2307692 * zo_dly1;
+ zi_dly1 := input; -- store previous input value
+ z_out <= z_new;
+ end process;
+
+ output == k * z_out'ramp(100.0e-9); -- ensure continuous transitions on output
+
+end bhv;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd
new file mode 100644
index 000000000..aa4c9b571
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity lead_lag_ztf is
+
+ generic ( a1 : real := 2.003140;
+ a2 : real := -1.996860;
+ b1 : real := 3.250000;
+ b2 : real := -0.750000;
+ k : real := 400.0; -- normalizing gain
+ tsampl : real := 0.1e-3; -- sample period
+ init_delay : real := 0.0 ); -- optional delay
+
+ port ( quantity input : in real;
+ quantity output : out real );
+
+end entity lead_lag_ztf;
+
+----------------------------------------------------------------
+
+architecture simple of lead_lag_ztf is
+
+ constant num: real_vector := (a1, a2);
+ constant den: real_vector := (b1, b2);
+
+begin
+
+ output == k * input'ztf(num, den, tsampl, init_delay); -- implement transfer function
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd
new file mode 100644
index 000000000..19ed07a05
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity limiter is
+ generic ( limit_high : real := 4.8; -- upper limit
+ limit_low : real := -4.8 ); -- lower limit
+ port ( quantity input : in real;
+ quantity output : out real);
+end entity limiter;
+
+----------------------------------------------------------------
+
+architecture simple of limiter is
+ constant slope : real := 1.0e-4;
+begin
+
+ if input > limit_high use -- upper limit exceeded, so limit input signal
+ output == limit_high + slope*(input - limit_high);
+ elsif input < limit_low use -- lower limit exceeded, so limit input signal
+ output == limit_low + slope*(input - limit_low);
+ else -- no limit exceeded, so pass input signal as is
+ output == input;
+ end use;
+
+ break on input'above(limit_high), input'above(limit_low);
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lpf_1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lpf_1.vhd
new file mode 100644
index 000000000..4825ca2d8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lpf_1.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity lpf_1 is
+ generic ( fp : real; -- pole freq in hertz
+ gain : real := 1.0 ); -- filter gain
+ port ( quantity input : in real;
+ quantity output : out real);
+end entity lpf_1;
+
+----------------------------------------------------------------
+
+library ieee; use ieee.math_real.all;
+
+architecture simple of lpf_1 is
+
+ constant wp : real := math_2_pi*fp;
+ constant num : real_vector := (0 => wp * gain); -- "0 =>" is needed to give
+ -- vector index when only
+ -- a single element is used.
+ constant den : real_vector := (wp, 1.0);
+
+begin
+
+ output == input'ltf(num, den);
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd
new file mode 100644
index 000000000..4a6c037ca
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.mechanical_systems.all;
+
+entity stop_r is
+ generic ( k_stop : real := 1.0e6;
+ ang_max : real := 1.05;
+ ang_min : real := -1.05;
+ damp_stop : real := 1.0e2 );
+ port ( terminal ang1, ang2 : rotational );
+end entity stop_r;
+
+----------------------------------------------------------------
+
+architecture ideal of stop_r is
+
+ quantity velocity : velocity;
+ quantity ang across trq through ang1 to ang2;
+
+begin
+
+ velocity == ang'dot;
+
+ if ang > ang_max use -- Hit upper stop, generate opposing torque
+ trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+ elsif ang > ang_min use -- Between stops, no opposing torque
+ trq == 0.0;
+ else -- Hit lower stop, generate opposing torque
+ trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
+ end use;
+
+ break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/sum2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/sum2.vhd
new file mode 100644
index 000000000..b60cfed5e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/sum2.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity sum2 is
+ generic ( k1, k2 : real := 1.0 ); -- optional gain multipliers
+ port ( quantity in1, in2 : in real;
+ quantity output : out real );
+end entity sum2;
+
+----------------------------------------------------------------
+
+architecture simple of sum2 is
+begin
+
+ output == k1 * in1 + k2 * in2; -- sum of inputs (with optional gain)
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd
new file mode 100644
index 000000000..a8eca951f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd
@@ -0,0 +1,812 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+ generic (k1, k2: real := 1.0); -- Gain multipliers
+ port ( terminal in1, in2: electrical;
+ terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+ QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+ QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+ generic (
+ k: REAL := 1.0); -- Gain multiplier
+ port ( terminal input : electrical;
+ terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+-- Transfer Function:
+--
+-- (s + w1)
+-- H(s) = k * ----------
+-- (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lead_lag_e is
+ generic (
+ k: real := 1.0; -- Gain multiplier
+ f1: real := 10.0; -- First break frequency (zero)
+ f2: real := 100.0); -- Second break frequency (pole)
+ port ( terminal input: electrical;
+ terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ quantity vin_temp : real;
+ constant w1 : real := f1*math_2_pi;
+ constant w2 : real := f2*math_2_pi;
+ constant num : real_vector := (w1, 1.0);
+ constant den : real_vector := (w2, 1.0);
+begin
+ vin_temp == vin;
+ vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+ generic (
+ limit_high : real := 4.8; -- upper limit
+ limit_low : real := -4.8); -- lower limit
+ port (
+ terminal input: electrical;
+ terminal output: electrical);
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+ constant slope : real := 1.0e-4;
+begin
+ if vin > limit_high use -- Upper limit exceeded, so limit input signal
+ vout == limit_high + slope*(vin - limit_high);
+ elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
+ vout == limit_low + slope*(vin - limit_low);
+ else -- No limit exceeded, so pass input signal as is
+ vout == vin;
+ end use;
+ break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo is
+ port(
+ terminal servo_in : electrical;
+ terminal pos_fb : electrical;
+ terminal servo_out : electrical
+ );
+end rudder_servo;
+
+architecture rudder_servo of rudder_servo is
+ -- Component declarations
+ -- Signal declarations
+ terminal error : electrical;
+ terminal limit_in : electrical;
+ terminal ll_in : electrical;
+ terminal summer_fb : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ summer : entity work.sum2_e(simple)
+ port map(
+ in1 => servo_in,
+ in2 => summer_fb,
+ output => error
+ );
+ forward_gain : entity work.gain_e(simple)
+ generic map(
+ k => 100.0
+ )
+ port map(
+ input => error,
+ output => ll_in
+ );
+ lead_lag : entity work.lead_lag_e(simple)
+ generic map(
+ f2 => 2000.0,
+ f1 => 5.0,
+ k => 400.0
+ )
+ port map(
+ input => ll_in,
+ output => limit_in
+ );
+ fb_gain : entity work.gain_e(simple)
+ generic map(
+ k => -4.57
+ )
+ port map(
+ input => pos_fb,
+ output => summer_fb
+ );
+ XCMP21 : entity work.limiter_2_e(simple)
+ generic map(
+ limit_high => 4.8,
+ limit_low => -4.8
+ )
+ port map(
+ input => limit_in,
+ output => servo_out
+ );
+end rudder_servo;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : gear_rv_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/10/10 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+ generic(
+ ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+ -- Note: can be negative, if shaft polarity changes
+
+ port ( terminal rotv1 : rotational_v;
+ terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+ quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+ quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+ theta == ratio*w1'integ;
+ torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+
+ generic (
+ k : real := 1.0); -- optional gain
+
+ port (
+ terminal input : rotational; -- input terminal
+ terminal output : electrical); -- output terminal
+
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref; -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+ begin -- bhv
+ v_out == k*rot_in;
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- tran = R*sin(rot)
+--
+-- Where pos = output translational position,
+-- R = horn radius,
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+
+ generic (
+ R : real := 1.0); -- horn radius
+
+ port (
+ terminal theta : ROTATIONAL; -- input angular position port
+ terminal pos : TRANSLATIONAL); -- output translational position port
+
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+ begin -- bhv
+ tran == R*sin(rot); -- Convert angle in to translational out
+ tran_frc == -rot_tq/R; -- Convert torque in to force out
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- theta = arcsin(pos/R)
+--
+-- Where pos = input translational position,
+-- R = horn radius,
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+
+ generic (
+ R : real := 1.0); -- Rudder horn radius
+
+ port (
+ terminal pos : translational; -- input translational position port
+ terminal theta : rotational); -- output angular position port
+
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+ begin -- bhv
+ rot == arcsin(tran/R); -- Convert translational to angle
+ rot_tq == -tran_frc*R; -- Convert force to torque
+
+end bhv;
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : DC_Motor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+ generic (
+ r_wind : resistance; -- Motor winding resistance [Ohm]
+ kt : real; -- Torque coefficient [N*m/Amp]
+ l : inductance; -- Winding inductance [Henrys]
+ d : real; -- Damping coefficient [N*m/(rad/sec)]
+ j : mmoment_i); -- Moment of inertia [kg*meter**2]
+
+ port (terminal p1, p2 : electrical;
+ terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
+-- T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+ quantity v across i through p1 to p2;
+ quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+ torq == -1.0*kt*i + d*w + j*w'dot;
+ v == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : stop_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- library IEEE;
+-- use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+ generic (
+ k_stop : real;
+-- ang_max : angle;
+-- ang_min : angle := 0.0;
+ ang_max : real;
+ ang_min : real := 0.0;
+ damp_stop : real := 0.000000001
+ );
+
+ port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+ quantity velocity : velocity;
+ quantity ang across trq through ang1 to ang2;
+
+begin
+
+ velocity == ang'dot;
+
+ if ang > ang_max use
+ trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+ elsif ang > ang_min use
+ trq == 0.0;
+ else
+ trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
+ end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+ terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+ QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+ QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+ pos_2 == pos_1; -- Pass position
+ frc_2 == -frc_1; -- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+-- Transfer Function:
+--
+-- torq = -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+
+ generic (
+ k : real := 1.0; -- Spring constant
+ theta_0 : real := 0.0);
+
+ port (
+ terminal rot : rotational); -- input rotational angle
+
+end entity rudder;
+
+architecture bhv of rudder is
+
+ QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+ begin -- bhv
+
+ torq == k*(theta - theta_0); -- Convert force to torque
+
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : v_sine.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/07/03
+-------------------------------------------------------------------------------
+-- Description: Electrical sinusoidal voltage source
+-- Includes frequency domain settings
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-- 2001/07/03 1.1 Mentor Graphics Changed generics from real to
+-- voltage.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity v_sine is
+
+ generic (
+ freq : real; -- frequency [Hertz]
+ amplitude : voltage; -- amplitude [Volts]
+ phase : real := 0.0; -- initial phase [Degrees]
+ offset : voltage := 0.0; -- DC value [Volts]
+ df : real := 0.0; -- damping factor [1/second]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port (
+ terminal pos, neg : electrical);
+
+end entity v_sine;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_sine is
+-- Declare Branch Quantities
+ quantity v across i through pos to neg;
+-- Declare Quantity for Phase in radians (calculated below)
+ quantity phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+-- Convert phase to radians
+ phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+ if domain = quiescent_domain or domain = time_domain use
+ v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+ else
+ v == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TB_CS2_Mech_Domain is
+end TB_CS2_Mech_Domain;
+
+architecture TB_CS2_Mech_Domain of TB_CS2_Mech_Domain is
+ -- Component declarations
+ -- Signal declarations
+ terminal gear_out : rotational;
+ terminal link_in : translational;
+ terminal link_out : translational;
+ terminal mot_in : electrical;
+ terminal mot_out : rotational_v;
+ terminal pos_fb_v : electrical;
+ terminal rudder : rotational;
+ terminal src_in : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ rudder_servo1 : entity work.rudder_servo
+ port map(
+ servo_out => mot_in,
+ servo_in => src_in,
+ pos_fb => pos_fb_v
+ );
+ gear3 : entity work.gear_rv_r(ideal)
+ generic map(
+ ratio => 0.01
+ )
+ port map(
+ rotv1 => mot_out,
+ rot2 => gear_out
+ );
+ r2v : entity work.rot2v(bhv)
+ generic map(
+ k => 1.0
+ )
+ port map(
+ output => pos_fb_v,
+ input => gear_out
+ );
+ r2t : entity work.horn_r2t(bhv)
+ port map(
+ theta => gear_out,
+ pos => link_in
+ );
+ t2r : entity work.horn_t2r(bhv)
+ port map(
+ theta => rudder,
+ pos => link_out
+ );
+ motor1 : entity work.DC_Motor(basic)
+ generic map(
+ j => 168.0e-9,
+ d => 5.63e-6,
+ l => 2.03e-3,
+ kt => 3.43e-3,
+ r_wind => 2.2
+ )
+ port map(
+ p1 => mot_in,
+ p2 => ELECTRICAL_REF,
+ shaft_rotv => mot_out
+ );
+ stop1 : entity work.stop_r(ideal)
+ generic map(
+ ang_min => -1.05,
+ ang_max => 1.05,
+ k_stop => 1.0e6,
+ damp_stop => 1.0e2
+ )
+ port map(
+ ang1 => gear_out,
+ ang2 => ROTATIONAL_REF
+ );
+ XCMP35 : entity work.tran_linkage(a1)
+ port map(
+ p2 => link_out,
+ p1 => link_in
+ );
+ XCMP36 : entity work.rudder(bhv)
+ generic map(
+ k => 0.2
+ )
+ port map(
+ rot => rudder
+ );
+ v6 : entity work.v_sine(ideal)
+ generic map(
+ freq => 1.0,
+ amplitude => 4.8
+ )
+ port map(
+ pos => src_in,
+ neg => ELECTRICAL_REF
+ );
+end TB_CS2_Mech_Domain;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd
new file mode 100644
index 000000000..1bd3054b0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd
@@ -0,0 +1,527 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity v_sine is
+
+ generic (
+ freq : real; -- frequency [Hertz]
+ amplitude : voltage; -- amplitude [Volts]
+ phase : real := 0.0; -- initial phase [Degrees]
+ offset : voltage := 0.0; -- DC value [Volts]
+ df : real := 0.0; -- damping factor [1/second]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port (
+ terminal pos, neg : electrical);
+
+end entity v_sine;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_sine is
+-- Declare Branch Quantities
+ quantity v across i through pos to neg;
+-- Declare Quantity for Phase in radians (calculated below)
+ quantity phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+-- Convert phase to radians
+ phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+ if domain = quiescent_domain or domain = time_domain use
+ v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+ else
+ v == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity sum2_e is
+ generic (k1, k2: real := 1.0); -- Gain multipliers
+ port ( terminal in1, in2: electrical;
+ terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+ QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+ QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+-- Transfer Function:
+--
+-- (s + w1)
+-- H(s) = k * ----------
+-- (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE; use ieee.math_real.all;
+
+entity lead_lag_e is
+ generic (
+ k: real := 1.0; -- Gain multiplier
+ f1: real := 10.0; -- First break frequency (zero)
+ f2: real := 100.0); -- Second break frequency (pole)
+ port ( terminal input: electrical;
+ terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ quantity vin_temp : real;
+ constant w1 : real := f1*math_2_pi;
+ constant w2 : real := f2*math_2_pi;
+ constant num : real_vector := (w1, 1.0);
+ constant den : real_vector := (w2, 1.0);
+begin
+ vin_temp == vin;
+ vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+ generic (
+ k: REAL := 1.0); -- Gain multiplier
+ port ( terminal input : electrical;
+ terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k*vin;
+end architecture simple;
+--
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity limiter_2_e is
+ generic (
+ limit_high : real := 4.8; -- upper limit
+ limit_low : real := -4.8); -- lower limit
+ port (
+ terminal input: electrical;
+ terminal output: electrical);
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+ constant slope : real := 1.0e-4;
+begin
+ if vin > limit_high use -- Upper limit exceeded, so limit input signal
+ vout == limit_high + slope*(vin - limit_high);
+ elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
+ vout == limit_low + slope*(vin - limit_low);
+ else -- No limit exceeded, so pass input signal as is
+ vout == vin;
+ end use;
+ break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control
+--
+-- Transfer Function:
+--
+-- pos_t_out = R*sin(theta)
+--
+-- Where pos_t = output translational position,
+-- R = horn radius,
+-- theta_in = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity ctl_horn_e is
+
+ generic (
+ R : real := 1.0); -- horn radius
+
+ port (
+ terminal theta_in : electrical; -- input port
+ terminal pos_t_out : electrical); -- output port
+
+end entity ctl_horn_e;
+
+architecture bhv of ctl_horn_e is
+ quantity vin across theta_in to electrical_ref;
+ quantity vout across iout through pos_t_out to electrical_ref;
+
+ begin -- bhv
+ vout == R*sin(vin);
+end bhv;
+--
+-------------------------------------------------------------------------------
+-- Rudder Model
+--
+-- Transfer Function:
+--
+-- theta_out = arcsin(pos_t_in/R)
+--
+-- Where pos_t_in = input translational position,
+-- R = horn radius,
+-- theta_out = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+
+entity rudder_horn_e is
+
+ generic (
+ R : real := 1.0); -- Rudder horn radius
+
+ port (
+ terminal pos_t_in : electrical; -- input port
+ terminal theta_out : electrical); -- output port
+
+end entity rudder_horn_e;
+
+architecture bhv of rudder_horn_e is
+ quantity vin across pos_t_in to electrical_ref;
+ quantity vout across iout through theta_out to electrical_ref;
+
+ begin -- bhv
+ vout == arcsin(vin/R);
+end bhv;
+--
+-------------------------------------------------------------------------------
+-- Integrator
+--
+-- Transfer Function:
+--
+-- k
+-- H(s) = ---------
+-- s
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity integ_1_e is
+ generic (
+ k: real := 1.0; -- Gain
+ init: real := 0.0); -- Initial value of output
+ port (terminal input: electrical;
+ terminal output: electrical);
+end entity integ_1_e;
+
+architecture simple of integ_1_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ quantity vin_temp : real;
+begin
+ vin_temp == vin;
+ IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE
+ vout == init;
+ ELSE
+ vout == k*vin_temp'INTEG;
+
+ END USE;
+
+end architecture simple;
+--
+-------------------------------------------------------------------------------
+-- Second Order Lowpass filter
+--
+-- Transfer Function:
+--
+-- w1*w2
+-- H(s) = k * ----------------
+-- (s + w1)(s + w2)
+--
+-- DC Gain = k
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE; use ieee.math_real.all;
+
+entity lpf_1_e is
+ generic (
+ fp : real; -- pole freq
+ gain : real := 1.0); -- filter gain
+
+ port ( terminal input: electrical;
+ terminal output: electrical);
+end entity lpf_1_e;
+
+architecture simple of lpf_1_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ constant wp : real := math_2_pi*fp;
+ constant num : real_vector := (0 => wp*gain); -- 0=> is needed to give
+ -- index when only a single
+ -- element is used.
+ constant den : real_vector := (wp, 1.0);
+ quantity vin_temp : real;
+
+begin
+ vin_temp == vin; -- intermediate variable (vin) req'd for now
+ vout == vin_temp'ltf(num, den);
+end architecture simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TB_CS2_S_Domain is
+end TB_CS2_S_Domain;
+
+architecture TB_CS2_S_Domain of TB_CS2_S_Domain is
+ -- Component declarations
+ -- Signal declarations
+ terminal comp_in : electrical;
+ terminal ctl_horn_out : electrical;
+ terminal err_limit_in : electrical;
+ terminal error : electrical;
+ terminal gear_out : electrical;
+ terminal integ_out : electrical;
+ terminal load_trq : electrical;
+ terminal mtr_fb : electrical;
+ terminal mtr_gen_trq : electrical;
+ terminal mtr_in : electrical;
+ terminal mtr_out : electrical;
+ terminal pos_fb : electrical;
+ terminal rudder : electrical;
+ terminal rudder_in : electrical;
+ terminal src_in : electrical;
+ terminal XSIG010043 : electrical;
+ terminal XSIG010044 : electrical;
+ terminal XSIG010046 : electrical;
+ terminal XSIG010050 : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ v_source : entity work.v_sine(ideal)
+ generic map(
+ amplitude => 4.8,
+ freq => 1.0
+ )
+ port map(
+ pos => src_in,
+ neg => ELECTRICAL_REF
+ );
+ sum_pos : entity work.sum2_e(simple)
+ port map(
+ in1 => src_in,
+ in2 => pos_fb,
+ output => error
+ );
+ loop_comp : entity work.lead_lag_e(simple)
+ generic map(
+ f1 => 5.0,
+ k => 4000.0,
+ f2 => 20000.0
+ )
+ port map(
+ input => comp_in,
+ output => err_limit_in
+ );
+ pos_fb_gain : entity work.gain_e(simple)
+ generic map(
+ k => -4.57
+ )
+ port map(
+ input => rudder_in,
+ output => pos_fb
+ );
+ mech_limit : entity work.limiter_2_e(simple)
+ generic map(
+ limit_high => 1.05,
+ limit_low => -1.05
+ )
+ port map(
+ input => integ_out,
+ output => rudder_in
+ );
+ gear_box_horn : entity work.ctl_horn_e(bhv)
+ port map(
+ theta_in => rudder_in,
+ pos_t_out => ctl_horn_out
+ );
+ rudder_horn : entity work.rudder_horn_e(bhv)
+ port map(
+ pos_t_in => ctl_horn_out,
+ theta_out => rudder
+ );
+ mtr_Kt : entity work.gain_e(simple)
+ generic map(
+ k => 3.43e-3
+ )
+ port map(
+ input => XSIG010044,
+ output => mtr_gen_trq
+ );
+ gear_box : entity work.gain_e(simple)
+ generic map(
+ k => 0.01
+ )
+ port map(
+ input => mtr_out,
+ output => gear_out
+ );
+ mtr_Ke : entity work.gain_e(simple)
+ generic map(
+ k => -3.43e-3
+ )
+ port map(
+ input => mtr_out,
+ output => mtr_fb
+ );
+ sum_mtr_in : entity work.sum2_e(simple)
+ port map(
+ in1 => mtr_in,
+ in2 => mtr_fb,
+ output => XSIG010043
+ );
+ sum_load_trq : entity work.sum2_e(simple)
+ port map(
+ in1 => mtr_gen_trq,
+ in2 => load_trq,
+ output => XSIG010046
+ );
+ integrator : entity work.integ_1_e(simple)
+ generic map(
+ k => 1.0
+ )
+ port map(
+ input => gear_out,
+ output => integ_out
+ );
+ rudder_trq : entity work.gain_e(simple)
+ generic map(
+ k => -0.2
+ )
+ port map(
+ input => XSIG010050,
+ output => load_trq
+ );
+ trq_fb_gain : entity work.gain_e(simple)
+ generic map(
+ k => 0.01
+ )
+ port map(
+ input => rudder_in,
+ output => XSIG010050
+ );
+ mtr_elec_pole : entity work.lpf_1_e(simple)
+ generic map(
+ gain => 0.4545,
+ fp => 172.48
+ )
+ port map(
+ input => XSIG010043,
+ output => XSIG010044
+ );
+ mtr_mech_pole : entity work.lpf_1_e(simple)
+ generic map(
+ gain => 177.67e3,
+ fp => 5.33
+ )
+ port map(
+ input => XSIG010046,
+ output => mtr_out
+ );
+ loop_gain : entity work.gain_e(simple)
+ generic map(
+ k => 100.0
+ )
+ port map(
+ input => error,
+ output => comp_in
+ );
+ err_limit : entity work.limiter_2_e(simple)
+ generic map(
+ limit_high => 4.8,
+ limit_low => -4.8
+ )
+ port map(
+ input => err_limit_in,
+ output => mtr_in
+ );
+end TB_CS2_S_Domain;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd
new file mode 100644
index 000000000..aa65125ba
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd
@@ -0,0 +1,902 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : gear_rv_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/10/10 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+ generic(
+ ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+ -- Note: can be negative, if shaft polarity changes
+
+ port ( terminal rotv1 : rotational_v;
+ terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+ quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
+ quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+-- w2 == w1*ratio;
+ theta == ratio*w1'integ;
+ torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+
+ generic (
+ k : real := 1.0); -- optional gain
+
+ port (
+ terminal input : rotational; -- input terminal
+ terminal output : electrical); -- output terminal
+
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref; -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+ begin -- bhv
+ v_out == k*rot_in;
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- tran = R*sin(rot)
+--
+-- Where pos = output translational position,
+-- R = horn radius,
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+
+ generic (
+ R : real := 1.0); -- horn radius
+
+ port (
+ terminal theta : ROTATIONAL; -- input angular position port
+ terminal pos : TRANSLATIONAL); -- output translational position port
+
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+ begin -- bhv
+ tran == R*sin(rot); -- Convert angle in to translational out
+ tran_frc == -rot_tq/R; -- Convert torque in to force out
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- theta = arcsin(pos/R)
+--
+-- Where pos = input translational position,
+-- R = horn radius,
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+
+ generic (
+ R : real := 1.0); -- Rudder horn radius
+
+ port (
+ terminal pos : translational; -- input translational position port
+ terminal theta : rotational); -- output angular position port
+
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+ begin -- bhv
+ rot == arcsin(tran/R); -- Convert translational to angle
+ rot_tq == -tran_frc*R; -- Convert force to torque
+
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : DC_Motor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+ generic (
+ r_wind : resistance; -- Motor winding resistance [Ohm]
+ kt : real; -- Torque coefficient [N*m/Amp]
+ l : inductance; -- Winding inductance [Henrys]
+ d : real; -- Damping coefficient [N*m/(rad/sec)]
+ j : mmoment_i); -- Moment of inertia [kg*meter**2]
+
+ port (terminal p1, p2 : electrical;
+ terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
+-- T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+ quantity v across i through p1 to p2;
+ quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+ torq == -1.0*kt*i + d*w + j*w'dot;
+ v == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : stop_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- library IEEE;
+-- use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+ generic (
+ k_stop : real;
+-- ang_max : angle;
+-- ang_min : angle := 0.0;
+ ang_max : real;
+ ang_min : real := 0.0;
+ damp_stop : real := 0.000000001
+ );
+
+ port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+ quantity velocity : velocity;
+ quantity ang across trq through ang1 to ang2;
+
+begin
+
+ velocity == ang'dot;
+
+ if ang > ang_max use
+ trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+ elsif ang > ang_min use
+ trq == 0.0;
+ else
+ trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
+ end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+ terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+ QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+ QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+ pos_2 == pos_1; -- Pass position
+ frc_2 == -frc_1; -- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+-- Transfer Function:
+--
+-- torq = -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+
+ generic (
+ k : real := 1.0; -- Spring constant
+ theta_0 : real := 0.0);
+
+ port (
+ terminal rot : rotational); -- input rotational angle
+
+end entity rudder;
+
+architecture bhv of rudder is
+
+ QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+ begin -- bhv
+
+ torq == k*(theta - theta_0); -- Convert force to torque
+
+end bhv;
+--
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+ generic (k1, k2: real := 1.0); -- Gain multipliers
+ port ( terminal in1, in2: electrical;
+ terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+ QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+ QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+ generic (
+ k: REAL := 1.0); -- Gain multiplier
+ port ( terminal input : electrical;
+ terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+ generic (
+ limit_high : real := 4.8; -- upper limit
+ limit_low : real := -4.8); -- lower limit
+ port (
+ terminal input: electrical;
+ terminal output: electrical);
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+ constant slope : real := 1.0e-4;
+begin
+ if vin > limit_high use -- Upper limit exceeded, so limit input signal
+ vout == limit_high + slope*(vin - limit_high);
+ elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
+ vout == limit_low + slope*(vin - limit_low);
+ else -- No limit exceeded, so pass input signal as is
+ vout == vin;
+ end use;
+ break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : clock.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Digital clock with 50% duty cycle
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clock is
+ generic (
+ period : time); -- Clock period
+
+ port (
+ clk_out : out std_logic);
+
+end entity clock;
+
+architecture ideal of clock is
+
+begin
+ CreateClock: process
+ begin
+ clk_out <= '0';
+ wait for period/2;
+ clk_out <= '1';
+ wait for period/2;
+ end process CreateClock;
+
+end architecture ideal;
+
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Z-domain Lead Lag Filter
+--
+-- Z-Domain Transfer Function:
+--
+-- Y(z) a0(z) - a1(z-1)
+-- ---- = k * ---------------
+-- X(z) b0(z) - b1(z-1)
+--
+-- Normalizing Gain = k
+--
+-- Difference Equation:
+--
+-- Y(K) = AX(k) - BX(k-1) + CY(k-1)
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity lead_lag_diff is
+
+ port (
+ signal clk : in std_logic; -- clock
+ terminal input: electrical;
+ terminal output: electrical);
+end entity lead_lag_diff;
+
+architecture bhv of lead_lag_diff is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+ CONSTANT k : real := 400.0; -- Normalize gain
+
+signal z_out : real := 0.0;
+begin
+proc : process (clk)
+
+ variable zi_dly1 : real := 0.0; -- Input delayed 1 clk cycle
+ variable zo_dly1 : real := 0.0; -- Output delayed 1 clk cycle
+ variable z_new : real := 0.0; -- New output value this clk cycle
+
+ begin -- proc
+ zo_dly1 := z_out; -- Store previous output value
+ z_new := 0.6163507*vin - 0.6144184*zi_dly1 + 0.2307692*zo_dly1;
+ zi_dly1 := vin; -- Store previous input value
+ z_out <= z_new;
+ end process;
+ vout == k*z_out'ramp(100.0e-9); -- Ensure continuous transitions on output
+end bhv;
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo_z is
+ port(
+ terminal servo_in : electrical;
+ terminal pos_fb : electrical;
+ terminal servo_out : electrical
+ );
+end rudder_servo_z;
+
+architecture rudder_servo_z of rudder_servo_z is
+ -- Component declarations
+ -- Signal declarations
+ signal clk : std_logic;
+ terminal error : electrical;
+ terminal limit_in : electrical;
+ terminal ll_in : electrical;
+ terminal summer_fb : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ summer : entity work.sum2_e(simple)
+ port map(
+ in1 => servo_in,
+ in2 => summer_fb,
+ output => error
+ );
+ forward_gain : entity work.gain_e(simple)
+ generic map(
+ k => 100.0
+ )
+ port map(
+ input => error,
+ output => ll_in
+ );
+ fb_gain : entity work.gain_e(simple)
+ generic map(
+ k => -4.57
+ )
+ port map(
+ input => pos_fb,
+ output => summer_fb
+ );
+ XCMP21 : entity work.limiter_2_e(simple)
+ generic map(
+ limit_high => 4.8,
+ limit_low => -4.8
+ )
+ port map(
+ input => limit_in,
+ output => servo_out
+ );
+ clock1 : entity work.clock(ideal)
+ generic map(
+ period => 200us
+ )
+ port map(
+ CLK_OUT => clk
+ );
+ XCMP23 : entity work.lead_lag_diff(bhv)
+ port map(
+ input => ll_in,
+ output => limit_in,
+ clk => clk
+ );
+end rudder_servo_z;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : v_sine.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/07/03
+-------------------------------------------------------------------------------
+-- Description: Electrical sinusoidal voltage source
+-- Includes frequency domain settings
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-- 2001/07/03 1.1 Mentor Graphics Changed generics from real to
+-- voltage.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity v_sine is
+
+ generic (
+ freq : real; -- frequency [Hertz]
+ amplitude : voltage; -- amplitude [Volts]
+ phase : real := 0.0; -- initial phase [Degrees]
+ offset : voltage := 0.0; -- DC value [Volts]
+ df : real := 0.0; -- damping factor [1/second]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port (
+ terminal pos, neg : electrical);
+
+end entity v_sine;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_sine is
+-- Declare Branch Quantities
+ quantity v across i through pos to neg;
+-- Declare Quantity for Phase in radians (calculated below)
+ quantity phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+-- Convert phase to radians
+ phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+ if domain = quiescent_domain or domain = time_domain use
+ v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+ else
+ v == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TB_CS2_Z_Domain_Diff is
+end TB_CS2_Z_Domain_Diff;
+
+architecture TB_CS2_Z_Domain_Diff of TB_CS2_Z_Domain_Diff is
+ -- Component declarations
+ -- Signal declarations
+ terminal ctl_horn_in : rotational;
+ terminal fb_rot2v : electrical;
+ terminal gear_in : rotational_v;
+ terminal link_in : translational;
+ terminal link_out : translational;
+ terminal mot_in : electrical;
+ terminal rudder : rotational;
+ terminal src_in : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ gear1 : entity work.gear_rv_r(ideal)
+ generic map(
+ ratio => 0.01
+ )
+ port map(
+ rotv1 => gear_in,
+ rot2 => ctl_horn_in
+ );
+ gain_fb : entity work.rot2v(bhv)
+ generic map(
+ k => 1.0
+ )
+ port map(
+ output => fb_rot2v,
+ input => ctl_horn_in
+ );
+ gear_horn : entity work.horn_r2t(bhv)
+ port map(
+ theta => ctl_horn_in,
+ pos => link_in
+ );
+ rudder_horn : entity work.horn_t2r(bhv)
+ port map(
+ theta => rudder,
+ pos => link_out
+ );
+ motor1 : entity work.DC_Motor(basic)
+ generic map(
+ r_wind => 2.2,
+ kt => 3.43e-3,
+ l => 2.03e-3,
+ d => 5.63e-6,
+ j => 168.0e-9
+ )
+ port map(
+ p1 => mot_in,
+ p2 => ELECTRICAL_REF,
+ shaft_rotv => gear_in
+ );
+ stop1 : entity work.stop_r(ideal)
+ generic map(
+ damp_stop => 1.0e2,
+ k_stop => 1.0e6,
+ ang_max => 1.05,
+ ang_min => -1.05
+ )
+ port map(
+ ang1 => ctl_horn_in,
+ ang2 => ROTATIONAL_REF
+ );
+ \Linkage\ : entity work.tran_linkage(a1)
+ port map(
+ p2 => link_out,
+ p1 => link_in
+ );
+ XCMP5 : entity work.rudder(bhv)
+ generic map(
+ k => 0.2
+ )
+ port map(
+ rot => rudder
+ );
+ rudder_servo_z1 : entity work.rudder_servo_z
+ port map(
+ servo_out => mot_in,
+ servo_in => src_in,
+ pos_fb => fb_rot2v
+ );
+ v3 : entity work.v_sine(ideal)
+ generic map(
+ freq => 1.0,
+ amplitude => 4.8
+ )
+ port map(
+ pos => src_in,
+ neg => ELECTRICAL_REF
+ );
+end TB_CS2_Z_Domain_Diff;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd
new file mode 100644
index 000000000..e9f034643
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd
@@ -0,0 +1,817 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : gear_rv_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/10/10 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+ generic(
+ ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+ -- Note: can be negative, if shaft polarity changes
+
+ port ( terminal rotv1 : rotational_v;
+ terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+ quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
+ quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+-- w2 == w1*ratio;
+ theta == ratio*w1'integ;
+ torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+
+ generic (
+ k : real := 1.0); -- optional gain
+
+ port (
+ terminal input : rotational; -- input terminal
+ terminal output : electrical); -- output terminal
+
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref; -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+ begin -- bhv
+ v_out == k*rot_in;
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- tran = R*sin(rot)
+--
+-- Where pos = output translational position,
+-- R = horn radius,
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+
+ generic (
+ R : real := 1.0); -- horn radius
+
+ port (
+ terminal theta : ROTATIONAL; -- input angular position port
+ terminal pos : TRANSLATIONAL); -- output translational position port
+
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+ begin -- bhv
+ tran == R*sin(rot); -- Convert angle in to translational out
+ tran_frc == -rot_tq/R; -- Convert torque in to force out
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- theta = arcsin(pos/R)
+--
+-- Where pos = input translational position,
+-- R = horn radius,
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+
+ generic (
+ R : real := 1.0); -- Rudder horn radius
+
+ port (
+ terminal pos : translational; -- input translational position port
+ terminal theta : rotational); -- output angular position port
+
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+ begin -- bhv
+ rot == arcsin(tran/R); -- Convert translational to angle
+ rot_tq == -tran_frc*R; -- Convert force to torque
+
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : DC_Motor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+ generic (
+ r_wind : resistance; -- Motor winding resistance [Ohm]
+ kt : real; -- Torque coefficient [N*m/Amp]
+ l : inductance; -- Winding inductance [Henrys]
+ d : real; -- Damping coefficient [N*m/(rad/sec)]
+ j : mmoment_i); -- Moment of inertia [kg*meter**2]
+
+ port (terminal p1, p2 : electrical;
+ terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
+-- T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+ quantity v across i through p1 to p2;
+ quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+ torq == -1.0*kt*i + d*w + j*w'dot;
+ v == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : stop_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- library IEEE;
+-- use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+ generic (
+ k_stop : real;
+-- ang_max : angle;
+-- ang_min : angle := 0.0;
+ ang_max : real;
+ ang_min : real := 0.0;
+ damp_stop : real := 0.000000001
+ );
+
+ port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+ quantity velocity : velocity;
+ quantity ang across trq through ang1 to ang2;
+
+begin
+
+ velocity == ang'dot;
+
+ if ang > ang_max use
+ trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+ elsif ang > ang_min use
+ trq == 0.0;
+ else
+ trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
+ end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+ terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+ QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+ QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+ pos_2 == pos_1; -- Pass position
+ frc_2 == -frc_1; -- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+-- Transfer Function:
+--
+-- torq = -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+
+ generic (
+ k : real := 1.0; -- Spring constant
+ theta_0 : real := 0.0);
+
+ port (
+ terminal rot : rotational); -- input rotational angle
+
+end entity rudder;
+
+architecture bhv of rudder is
+
+ QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+ begin -- bhv
+
+ torq == k*(theta - theta_0); -- Convert force to torque
+
+end bhv;
+--
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+ generic (k1, k2: real := 1.0); -- Gain multipliers
+ port ( terminal in1, in2: electrical;
+ terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+ QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+ QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+ generic (
+ k: REAL := 1.0); -- Gain multiplier
+ port ( terminal input : electrical;
+ terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+ generic (
+ limit_high : real := 4.8; -- upper limit
+ limit_low : real := -4.8); -- lower limit
+ port (
+ terminal input: electrical;
+ terminal output: electrical);
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+ constant slope : real := 1.0e-4;
+begin
+ if vin > limit_high use -- Upper limit exceeded, so limit input signal
+ vout == limit_high + slope*(vin - limit_high);
+ elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
+ vout == limit_low + slope*(vin - limit_low);
+ else -- No limit exceeded, so pass input signal as is
+ vout == vin;
+ end use;
+ break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+--
+
+LIBRARY ieee;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY lead_lag_ztf IS
+
+ GENERIC (
+ a1, a2 : real;
+ b1, b2 : real;
+ k : real := 1.0;
+ tsampl: real;
+ init_delay: real := 0.0);
+
+ PORT (
+ TERMINAL input : electrical;
+ TERMINAL output : electrical);
+
+END ENTITY lead_lag_ztf ;
+
+ARCHITECTURE simple OF lead_lag_ztf IS
+
+ QUANTITY vin across input TO electrical_ref;
+ QUANTITY vout across iout through output TO electrical_ref;
+
+ constant num: real_vector := (a1, a2);
+ constant den: real_vector := (b1, b2);
+
+BEGIN -- ARCHITECTURE simple
+
+vout == k*vin'ztf(num, den, tsampl, init_delay);
+
+END ARCHITECTURE simple;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo_ztf is
+ port(
+ terminal servo_in : electrical;
+ terminal pos_fb : electrical;
+ terminal servo_out : electrical
+ );
+end rudder_servo_ztf;
+
+architecture rudder_servo_ztf of rudder_servo_ztf is
+ -- Component declarations
+ -- Signal declarations
+ terminal error : electrical;
+ terminal limit_in : electrical;
+ terminal ll_in : electrical;
+ terminal summer_fb : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ summer : entity work.sum2_e(simple)
+ port map(
+ in1 => servo_in,
+ in2 => summer_fb,
+ output => error
+ );
+ forward_gain : entity work.gain_e(simple)
+ generic map(
+ k => 100.0
+ )
+ port map(
+ input => error,
+ output => ll_in
+ );
+ fb_gain : entity work.gain_e(simple)
+ generic map(
+ k => -4.57
+ )
+ port map(
+ input => pos_fb,
+ output => summer_fb
+ );
+ XCMP21 : entity work.limiter_2_e(simple)
+ generic map(
+ limit_high => 4.8,
+ limit_low => -4.8
+ )
+ port map(
+ input => limit_in,
+ output => servo_out
+ );
+ ll_ztf : entity work.lead_lag_ztf(simple)
+ generic map(
+ a1 => 2.003140,
+ a2 => -1.996860,
+ b1 => 3.25000,
+ b2 => -0.75000,
+ k => 400.0,
+ tsampl => 0.0001
+ )
+ port map(
+ input => ll_in,
+ output => limit_in
+ );
+end rudder_servo_ztf;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : v_sine.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/07/03
+-------------------------------------------------------------------------------
+-- Description: Electrical sinusoidal voltage source
+-- Includes frequency domain settings
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-- 2001/07/03 1.1 Mentor Graphics Changed generics from real to
+-- voltage.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity v_sine is
+
+ generic (
+ freq : real; -- frequency [Hertz]
+ amplitude : voltage; -- amplitude [Volts]
+ phase : real := 0.0; -- initial phase [Degrees]
+ offset : voltage := 0.0; -- DC value [Volts]
+ df : real := 0.0; -- damping factor [1/second]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port (
+ terminal pos, neg : electrical);
+
+end entity v_sine;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_sine is
+-- Declare Branch Quantities
+ quantity v across i through pos to neg;
+-- Declare Quantity for Phase in radians (calculated below)
+ quantity phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+-- Convert phase to radians
+ phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+ if domain = quiescent_domain or domain = time_domain use
+ v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+ else
+ v == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity TB_CS2_Z_Domain_ZTF is
+end TB_CS2_Z_Domain_ZTF ;
+
+architecture TB_CS2_Z_Domain_ZTF of TB_CS2_Z_Domain_ZTF is
+ -- Component declarations
+ -- Signal declarations
+ terminal gear_out : rotational;
+ terminal link_in : translational;
+ terminal link_out : translational;
+ terminal mtr_in : electrical;
+ terminal mtr_out : rotational_v;
+ terminal pot_fb : electrical;
+ terminal rudder : rotational;
+ terminal src_in : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ gear5 : entity work.gear_rv_r(ideal)
+ generic map(
+ ratio => 0.01
+ )
+ port map(
+ rotv1 => mtr_out,
+ rot2 => gear_out
+ );
+ XCMP42 : entity work.rot2v(bhv)
+ generic map(
+ k => 1.0
+ )
+ port map(
+ output => pot_fb,
+ input => gear_out
+ );
+ XCMP43 : entity work.horn_r2t(bhv)
+ port map(
+ theta => gear_out,
+ pos => link_in
+ );
+ XCMP44 : entity work.horn_t2r(bhv)
+ port map(
+ theta => rudder,
+ pos => link_out
+ );
+ motor3 : entity work.DC_Motor(basic)
+ generic map(
+ r_wind => 2.2,
+ kt => 3.43e-3,
+ l => 2.03e-3,
+ d => 5.63e-6,
+ j => 168.0e-9
+ )
+ port map(
+ p1 => mtr_in,
+ p2 => ELECTRICAL_REF,
+ shaft_rotv => mtr_out
+ );
+ stop3 : entity work.stop_r(ideal)
+ generic map(
+ damp_stop => 1.0e2,
+ k_stop => 1.0e6,
+ ang_max => 1.05,
+ ang_min => -1.05
+ )
+ port map(
+ ang1 => gear_out,
+ ang2 => ROTATIONAL_REF
+ );
+ \linkage\ : entity work.tran_linkage(a1)
+ port map(
+ p2 => link_out,
+ p1 => link_in
+ );
+ XCMP46 : entity work.rudder(bhv)
+ generic map(
+ k => 0.2
+ )
+ port map(
+ rot => rudder
+ );
+ rudder_servo_zt1 : entity work.rudder_servo_ztf
+ port map(
+ servo_out => mtr_in,
+ servo_in => src_in,
+ pos_fb => pot_fb
+ );
+ v8 : entity work.v_sine(ideal)
+ generic map(
+ amplitude => 4.8,
+ freq => 1.0
+ )
+ port map(
+ pos => src_in,
+ neg => ELECTRICAL_REF
+ );
+end TB_CS2_Z_Domain_ZTF;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams.vhd
new file mode 100644
index 000000000..176837f01
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity CalcBuckParams is
+
+ generic ( Vin : voltage range 1.0 to 50.0 := 42.0; -- input voltage [volts]
+ Vout : voltage := 4.8; -- output voltage [volts]
+ Vd : voltage := 0.7; -- diode voltage [volts]
+ Imin : current := 15.0e-3; -- min output current [amps]
+ Vripple : voltage range 1.0e-6 to 100.0
+ := 100.0e-3 ); -- output voltage ripple [volts]
+
+ port ( quantity Fsw : in real range 1.0 to 1.0e6
+ := 2.0; -- switching frequency [Hz]
+ quantity Lmin : out inductance; -- minimum inductance [henries]
+ quantity Cmin : out capacitance ); -- minimum capacitance [farads]
+
+end entity CalcBuckParams;
+
+----------------------------------------------------------------
+
+architecture behavioral of CalcBuckParams is
+
+ constant D : real := (Vout + Vd) / Vin; -- duty cycle
+ quantity Ts : real; -- period
+ quantity Ton : real; -- on time
+
+begin
+
+ Ts == 1.0 / Fsw;
+
+ Ton == D * Ts;
+
+ Lmin == (Vin - Vout) * Ton / (2.0 * Imin);
+
+ Cmin == (2.0 * Imin) / (8.0 * Fsw * Vripple);
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams_wa.vhd
new file mode 100644
index 000000000..e568a63fd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams_wa.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity CalcBuckParams_wa is
+
+ generic ( Vin : voltage := 42.0; -- input voltage [Volts]
+ Vout : voltage := 4.8; -- output voltage [Volts]
+ Vd : voltage := 0.7; -- diode Voltage [Volts]
+ Imin : current := 15.0e-3; -- min output current [Amps]
+ Vripple : voltage := 100.0e-3; -- output voltage ripple [Volts]
+ Resr : resistance := 50.0e-3 );
+
+ port ( quantity Fsw : in real; -- switching frequency [Hz]
+ quantity Lmin : out inductance; -- minimum inductance [Henries]
+ quantity Cmin : out capacitance); -- minimum capacitance [Farads]
+
+end entity CalcBuckParams_wa ;
+
+----------------------------------------------------------------
+
+architecture ideal of CalcBuckParams_wa is
+
+ constant D : real := (Vout + Vd)/(Vin + 1.0e-9); -- Duty Cycle
+ quantity Ts : real; -- Period
+ quantity Ton : real; -- On Time
+
+ quantity Fxo, Fp1, Fp2, Fz : real;
+
+begin -- architecture behavioral
+
+ Ts == 1.0/(Fsw+1.0e-9);
+ Ton == D*Ts;
+ Lmin == (Vin - Vout) * Ton/(2.0*Imin);
+ Cmin == (2.0*Imin)/(8.0*Fsw*Vripple+1.0e-9);
+
+ -- Calculate compensator parameters
+ Fxo == Fsw/5.0; -- desired crossover frequency
+ Fp1 == Fxo * 1.5;
+ Fp2 == 1.0/(math_2_pi*Resr*Cmin*4.0+1.0e-9);
+ Fz == 1.0/(math_2_pi*sqrt(Lmin*Cmin*4.0)+1.0e-9);
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/buck_sw.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/buck_sw.vhd
new file mode 100644
index 000000000..6320e4cd2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/buck_sw.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity buck_sw is
+ generic ( Vd : voltage := 0.7; -- diode voltage
+ Vramp : voltage := 2.5 ); -- p-p amplitude of ramp voltage
+ port ( terminal input, output, ref, ctrl: electrical );
+end entity buck_sw;
+
+----------------------------------------------------------------
+
+architecture average of buck_sw is
+
+ quantity Vout across Iout through output to ref;
+ quantity Vin across input to ref;
+ quantity Vctrl across ctrl to ref;
+
+begin
+
+ Vout == Vctrl * Vin / Vramp - Vd; -- averaged equation
+
+end architecture average;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/capacitor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/capacitor.vhd
new file mode 100644
index 000000000..dd4a3ab70
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/capacitor.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity capacitor is
+ generic ( cap : capacitance;
+ r_esr : resistance := 0.0;
+ v_ic : voltage := real'low );
+ port ( terminal p1, p2 : electrical );
+end entity capacitor;
+
+----------------------------------------------------------------
+
+architecture esr of capacitor is
+
+ quantity v across i through p1 to p2;
+ quantity vc : voltage; -- Internal voltage across capacitor
+
+begin
+
+ if domain = quiescent_domain and v_ic /= real'low use
+ vc == v_ic;
+ i == 0.0;
+ else
+ vc == v - (i * r_esr);
+ i == cap * vc'dot;
+ end use;
+
+end architecture esr;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/comp_2p2z.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/comp_2p2z.vhd
new file mode 100644
index 000000000..20d353431
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/comp_2p2z.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity comp_2p2z is
+ generic ( gain : real := 100.0; -- high DC gain for good load regulation
+ fp1 : real := 7.5e3; -- pole location to achieve crossover frequency
+ fp2 : real := 531.0e3; -- pole location to cancel effect of ESR
+ fz1 : real := 403.0; -- zero locations to cancel L-C filter poles
+ fz2 : real := 403.0 );
+ port ( terminal input, output, ref : electrical );
+end entity comp_2p2z;
+
+----------------------------------------------------------------
+
+architecture ltf of comp_2p2z is
+
+ quantity vin across input to ref;
+ quantity vout across iout through output to ref;
+ constant wp1 : real := math_2_pi * fp1; -- Pole freq (in radians)
+ constant wp2 : real := math_2_pi * fp2;
+ constant wz1 : real := math_2_pi * fz1; -- Zero freq (in radians)
+ constant wz2 : real := math_2_pi * fz2;
+ constant num : real_vector := ( 1.0,
+ (wz1 + wz2) / (wz1 * wz2),
+ 1.0 / (wz1 * wz2) );
+ constant den : real_vector := ( 1.0e-9, 1.0,
+ (wp1 + wp2) / (wp1 * wp2),
+ 1.0 / (wp1 * wp2) );
+
+begin
+
+ vout == -1.0 * gain * vin'ltf(num, den);
+
+end architecture ltf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/index-ams.txt
new file mode 100644
index 000000000..7470b2643
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/index-ams.txt
@@ -0,0 +1,32 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 18 - Case Study 3: DC-DC Power Converter
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+tb_BuckConverter.vhd entity tb_BuckConverter tb_BuckConverter Figure 18-7
+capacitor.vhd entity capacitor esr Figure 18-9
+switch_dig.vhd entity switch_dig linear Figure 18-10
+buck_sw.vhd entity buck_sw average Figure 18-13
+sw_LoopCtrl.vhd entity sw_LoopCtrl ideal Figure 18-16
+sw_LoopCtrl_wa.vhd entity sw_LoopCtrl_wa ideal --
+comp_2p2z.vhd entity comp_2p2z ltf Figure 18-18
+pwl_load.vhd entity pwl_load ideal Figure 18-20
+pwl_load_wa.vhd entity pwl_load_wa ideal --
+CalcBuckParams.vhd entity CalcBuckParams behavioral Figure 18-23
+CalcBuckParams_wa.vhd entity CalcBuckParams_wa ideal --
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_CalcBuckParams.vhd entity tb_CalcBuckParams tb_CalcBuckParams CalcBuckParams.vhd
+tb_CS3_BuckConverter_average.vhd entity inductor ideal
+-- entity inductor ideal2
+-- entity capacitor esr
+-- entity v_constant ideal
+-- entity sw_LoopCtrl_wa ideal
+-- entity pwl_load_wa ideal
+-- entity v_pulse ideal
+-- entity buck_sw average
+-- entity comp_2p2z ltf
+-- entity TB_CS3_BuckConverter_average TB_CS3_BuckConverter_average
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd
new file mode 100644
index 000000000..073554d10
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity pwl_load is
+ generic ( load_enable : boolean := true;
+ res_init : resistance;
+ res1 : resistance;
+ t1 : time;
+ res2 : resistance;
+ t2 : time );
+ port ( terminal p1, p2 : electrical );
+end entity pwl_load;
+
+----------------------------------------------------------------
+
+architecture ideal of pwl_load is
+
+ quantity v across i through p1 to p2;
+ signal res_signal : resistance := res_init;
+
+begin
+
+ load_present : if load_enable generate
+
+ if domain = quiescent_domain or domain = frequency_domain use
+ v == i * res_init;
+ else
+ v == i * res_signal'ramp(1.0e-6, 1.0e-6);
+ end use;
+
+ create_event : process is
+ begin
+ wait for t1;
+ res_signal <= res1;
+ wait for t2 - t1;
+ res_signal <= res2;
+ wait;
+ end process create_event;
+
+ end generate load_present;
+
+ load_absent : if not load_enable generate
+
+ i == 0.0;
+
+ end generate load_absent;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load_wa.vhd
new file mode 100644
index 000000000..b9a0835d1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load_wa.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity pwl_load_wa is
+ generic ( load_enable : boolean := true;
+ res_init : resistance;
+ res1 : resistance;
+ t1 : time;
+ res2 : resistance;
+ t2 : time );
+ port ( terminal p1, p2 : electrical );
+end entity pwl_load_wa;
+
+----------------------------------------------------------------
+
+architecture ideal of pwl_load_wa is
+
+ quantity v across i through p1 to p2;
+ signal res_signal : resistance := res_init;
+
+begin
+
+ if load_enable use
+ if domain = quiescent_domain or domain = frequency_domain use
+ v == i * res_init;
+ else
+ v == i * res_signal'ramp(1.0e-6, 1.0e-6);
+ end use;
+ else
+ i == 0.0;
+ end use;
+
+ create_event: process is
+ begin
+ wait for t1;
+ res_signal <= res1;
+ wait for t2 - t1;
+ res_signal <= res2;
+ wait;
+ end process create_event;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl.vhd
new file mode 100644
index 000000000..69c4f17d5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity sw_LoopCtrl is
+ generic ( r_open : resistance := 1.0e6;
+ r_closed : resistance := 1.0e-3;
+ sw_state : integer range 1 to 2 := 1 );
+ port ( terminal c, p1, p2 : electrical );
+end entity sw_LoopCtrl;
+
+----------------------------------------------------------------
+
+architecture ideal of sw_LoopCtrl is
+
+ quantity v1 across i1 through c to p1;
+ quantity v2 across i2 through c to p2;
+ quantity r1, r2 : resistance;
+
+begin
+
+ sw1 : if sw_state = 1 generate
+ r1 == r_closed;
+ r2 == r_open;
+ end generate sw1;
+
+ sw2 : if sw_state = 2 generate
+ r1 == r_open;
+ r2 == r_closed;
+ end generate sw2;
+
+ v1 == r1 * i1;
+ v2 == r2 * i2;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl_wa.vhd
new file mode 100644
index 000000000..cc57a01a1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl_wa.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity sw_LoopCtrl_wa is
+ generic ( r_open : resistance := 1.0e6;
+ r_closed : resistance := 1.0e-3;
+ sw_state : integer := 1 );
+ port ( terminal c, p1, p2 : electrical );
+
+end entity sw_LoopCtrl_wa;
+
+----------------------------------------------------------------
+
+architecture ideal of sw_LoopCtrl_wa is
+
+ quantity v1 across i1 through c to p1;
+ quantity v2 across i2 through c to p2;
+ quantity r1, r2 : resistance;
+
+begin
+
+ if (sw_state = 2) use
+ r1 == r_open;
+ r2 == r_closed;
+ else
+ r1 == r_closed;
+ r2 == r_open;
+ end use;
+
+ v1 == r1 * i1;
+ v2 == r2 * i2;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/switch_dig.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/switch_dig.vhd
new file mode 100644
index 000000000..5fdd86315
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/switch_dig.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity switch_dig is
+ generic ( r_open : resistance := 1.0e6;
+ r_closed : resistance := 1.0e-3;
+ trans_time : real := 1.0e-9 );
+ port ( sw_state : in std_logic;
+ terminal p1, p2 : electrical );
+end entity switch_dig;
+
+----------------------------------------------------------------
+
+architecture linear of switch_dig is
+
+ signal r_sig : resistance := r_open;
+ quantity v across i through p1 to p2;
+ quantity r : resistance;
+
+begin
+
+ -- detect switch state and assign resistance value to r_sig
+ DetectState: process (sw_state)
+ begin
+ if (sw_state'event and sw_state = '0') then
+ r_sig <= r_open;
+ elsif (sw_state'event and sw_state = '1') then
+ r_sig <= r_closed;
+ end if;
+ end process DetectState;
+
+ r == r_sig'ramp(trans_time, trans_time);
+ v == r * i;
+
+end architecture linear;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_BuckConverter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_BuckConverter.vhd
new file mode 100644
index 000000000..7c87c4b65
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_BuckConverter.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity tb_BuckConverter is
+ port ( ctrl : std_logic );
+end tb_BuckConverter;
+
+----------------------------------------------------------------
+
+architecture tb_BuckConverter of tb_BuckConverter is
+
+ terminal vin : electrical;
+ terminal vmid : electrical;
+ terminal vout : electrical;
+
+begin
+
+ L1 : entity work.inductor(ideal)
+ generic map ( ind => 6.5e-3 )
+ port map ( p1 => vmid, p2 => vout );
+
+ C1 : entity work.capacitor(ideal)
+ generic map ( cap => 1.5e-6 )
+ port map ( p1 => vout, p2 => electrical_ref );
+
+ VinDC : entity work.v_constant(ideal)
+ generic map ( level => 42.0 )
+ port map ( pos => vin, neg => electrical_ref );
+
+ RLoad : entity work.resistor(ideal)
+ generic map ( res => 2.4 )
+ port map ( p1 => vout, p2 => electrical_ref );
+
+ D1 : entity work.diode(ideal)
+ port map ( p => electrical_ref, n => vmid );
+
+ sw1 : entity work.switch_dig(ideal)
+ port map ( sw_state => ctrl, p2 => vmid, p1 => vin );
+
+end architecture tb_BuckConverter;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd
new file mode 100644
index 000000000..161485b4c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd
@@ -0,0 +1,604 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : inductor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Electrical Inductor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity inductor is
+
+ generic (
+ ind : inductance; -- Nominal inductance
+ i_ic : real := real'low); -- Initial current (use IF statement below
+ -- to activate)
+
+ port (
+ terminal p1, p2 : electrical);
+
+end entity inductor;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture (V = L * di/dt)
+-- Includes initial condition
+-------------------------------------------------------------------------------
+architecture ideal of inductor is
+
+-- Declare Branch Quantities
+ quantity v across i through p1 to p2;
+
+begin
+
+ if domain = quiescent_domain and i_ic /= real'low use
+ i == i_ic;
+ else
+ v == ind * i'dot; -- characteristic equation
+ end use;
+
+end architecture ideal;
+
+architecture ideal2 of inductor is
+
+-- Declare Branch Quantities
+ quantity v across i through p1 to p2;
+
+begin
+
+ if domain = quiescent_domain and i_ic /= real'low use
+ i == i_ic;
+ else
+ v == ind * i'dot; -- characteristic equation
+ end use;
+
+end architecture ideal2;
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : capacitor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Electrical Capacitor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+entity capacitor is
+ generic ( cap : capacitance;
+ r_esr : resistance := 0.0;
+ v_ic : voltage := real'low );
+ port ( terminal p1, p2 : electrical );
+end entity capacitor;
+
+architecture esr of capacitor is
+ quantity v across i through p1 to p2;
+ quantity vc : voltage; -- Internal voltage across capacitor
+begin
+ if domain = quiescent_domain and v_ic /= real'low use
+ vc == v_ic;
+ i == 0.0;
+ else
+ vc == v - (i * r_esr);
+ i == cap * vc'dot;
+ end use;
+end architecture esr;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : v_constant.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/07/03
+-------------------------------------------------------------------------------
+-- Description: Constant Voltage Source
+-- Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_constant is
+
+ generic (
+ level : voltage; -- Constant voltage value [Volts]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port (
+ terminal pos, neg : electrical);
+
+end entity v_constant;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture (I = constant)
+-------------------------------------------------------------------------------
+architecture ideal of v_constant is
+
+-- Declare Branch Quantities
+ quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+ v == level;
+ else
+ v == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity sw_LoopCtrl_wa is
+ generic (r_open : resistance := 1.0e6;
+ r_closed : resistance := 1.0e-3;
+ sw_state : integer := 1);
+ port (terminal c, p1, p2 : electrical);
+
+end entity sw_LoopCtrl_wa;
+
+architecture ideal of sw_LoopCtrl_wa is
+ quantity v1 across i1 through c to p1;
+ quantity v2 across i2 through c to p2;
+ quantity r1, r2 : resistance;
+begin
+ if (sw_state = 2) use
+ r1 == r_open;
+ r2 == r_closed;
+ else
+ r1 == r_closed;
+ r2 == r_open;
+ end use;
+
+ v1 == r1*i1;
+ v2 == r2*i2;
+end architecture ideal;
+
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity pwl_load_wa is
+ generic (
+ load_enable: string := "yes";
+ res_init : resistance;
+ res1 : resistance;
+ t1 : time;
+ res2 : resistance;
+ t2 : time);
+ port (terminal p1, p2 : electrical);
+end entity pwl_load_wa;
+
+architecture ideal of pwl_load_wa is
+ quantity v across i through p1 to p2;
+ signal res_signal : resistance := res_init;
+begin
+
+ if load_enable = "yes" use
+ if domain = quiescent_domain or domain = frequency_domain use
+ v == i*res_init;
+ else
+ v == i*res_signal'ramp(1.0e-6, 1.0e-6);
+ end use;
+ else
+ i == 0.0;
+ end use;
+
+ -- purpose: Create Events to change resistance at specified times
+ -- type : combinational
+ -- inputs :
+ -- outputs: res
+CreateEvent: process is
+ begin -- process CreateEvent
+ wait for t1;
+ res_signal <= res1;
+ wait for (t2-t1);
+ res_signal <= res2;
+ wait;
+ end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : v_pulse.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/07/09
+-------------------------------------------------------------------------------
+-- Description: Voltage Pulse Source
+-- Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
+-- time. Uses time2real function.
+-- Pulsewidth no longer includes
+-- rise and fall times.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_pulse is
+
+ generic (
+ initial : voltage := 0.0; -- initial value [Volts]
+ pulse : voltage; -- pulsed value [Volts]
+ ti2p : time := 1ns; -- initial to pulse [Sec]
+ tp2i : time := 1ns; -- pulse to initial [Sec]
+ delay : time := 0ms; -- delay time [Sec]
+ width : time; -- duration of pulse [Sec]
+ period : time; -- period [Sec]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port (
+ terminal pos, neg : electrical);
+
+end entity v_pulse;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_pulse is
+
+-- Declare Through and Across Branch Quantities
+ quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+-- Signal used in CreateEvent process below
+ signal pulse_signal : voltage := initial;
+
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+-- Note: these lines gave an error during simulation. Had to use a
+-- function call instead.
+-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
+-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
+
+-- Function to convert numbers of type TIME to type REAL
+ function time2real(tt : time) return real is
+ begin
+ return time'pos(tt) * 1.0e-15;
+ end time2real;
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+ constant ri2p : real := time2real(ti2p);
+ constant rp2i : real := time2real(tp2i);
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+ v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
+ else
+ v == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+-- purpose: Create events to define pulse shape
+-- type : combinational
+-- inputs :
+-- outputs: pulse_signal
+CreateEvent : process
+begin
+ wait for delay;
+ loop
+ pulse_signal <= pulse;
+ wait for (width + ti2p);
+ pulse_signal <= initial;
+ wait for (period - width - ti2p);
+ end loop;
+end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity buck_sw is
+ generic (
+ Vd : voltage := 0.7; -- Diode Voltage
+ Vramp : voltage := 2.5); -- P-P amplitude of ramp voltage
+ port (terminal input, output, ref, ctrl: electrical);
+end entity buck_sw;
+
+architecture average of buck_sw is
+ quantity Vout across Iout through output to ref;
+ quantity Vin across input to ref;
+ quantity Vctrl across ctrl to ref;
+begin
+ Vout + Vd == Vctrl * Vin / Vramp; -- Averaged equation
+end architecture average;
+
+library IEEE;
+library IEEE_proposed;
+use ieee.math_real.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity comp_2p2z is
+ generic (
+ gain : real := 100.0; -- High DC gain for good load regulation
+ fp1 : real := 7.5e3; -- Pole location to achieve crossover frequency
+ fp2 : real := 531.0e3;-- Pole location to cancel effect of ESR
+ fz1 : real := 403.0; -- Zero locations to cancel LC filter poles
+ fz2 : real := 403.0);
+ port (terminal input, output, ref : electrical);
+end entity comp_2p2z;
+
+architecture ltf of comp_2p2z is
+ quantity vin across input to ref;
+ quantity vout across iout through output to ref;
+ constant wp1 : real := math_2_pi*fp1; -- Pole freq (in radians)
+ constant wp2 : real := math_2_pi*fp2;
+ constant wz1 : real := math_2_pi*fz1; -- Zero freq (in radians)
+ constant wz2 : real := math_2_pi*fz2;
+ constant num : real_vector := (1.0, (wz1+wz2)/(wz1*wz2), 1.0/(wz1*wz2));
+ constant den : real_vector := (1.0e-9, 1.0, (wp1+wp2)/(wp1*wp2), 1.0/(wp1*wp2));
+begin
+ vout == -1.0*gain*vin'ltf(num, den);
+end architecture ltf;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TB_CS3_BuckConverter_average is
+end TB_CS3_BuckConverter_average;
+
+architecture TB_CS3_BuckConverter_average of TB_CS3_BuckConverter_average is
+ -- Component declarations
+ -- Signal declarations
+ terminal vcomp_out : electrical;
+ terminal vctrl : electrical;
+ terminal vctrl_init : electrical;
+ terminal vin : electrical;
+ terminal vmid : electrical;
+ terminal vout : electrical;
+ terminal vref : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ L1 : entity work.inductor(ideal)
+ generic map(
+ ind => 6.5e-3
+ )
+ port map(
+ p1 => vmid,
+ p2 => vout
+ );
+ C1 : entity work.capacitor(ESR)
+ generic map(
+ cap => 6.0e-6,
+ r_esr => 50.0e-3
+ )
+ port map(
+ p1 => vout,
+ p2 => ELECTRICAL_REF
+ );
+ Vctrl_1 : entity work.v_constant(ideal)
+ generic map(
+ level => 0.327
+ )
+ port map(
+ pos => vctrl_init,
+ neg => ELECTRICAL_REF
+ );
+ Vref_1 : entity work.v_constant(ideal)
+ generic map(
+ level => 4.8
+ )
+ port map(
+ pos => vref,
+ neg => ELECTRICAL_REF
+ );
+ sw2 : entity work.sw_LoopCtrl_wa(ideal)
+ generic map(
+ sw_state => 1
+ )
+ port map(
+ p2 => vctrl_init,
+ c => vctrl,
+ p1 => vcomp_out
+ );
+ Electrical_Load6 : entity work.pwl_load_wa(ideal)
+ generic map(
+ t2 => 30 ms,
+ res2 => 5.0,
+ t1 => 5ms,
+ res1 => 1.0,
+ res_init => 2.4,
+ load_enable => "yes"
+ )
+ port map(
+ p1 => vout,
+ p2 => ELECTRICAL_REF
+ );
+ Vin_1 : entity work.v_pulse(ideal)
+ generic map(
+ initial => 42.0,
+ pulse => 42.0,
+ delay => 10ms,
+ width => 100ms,
+ period => 1000ms
+ )
+ port map(
+ pos => vin,
+ neg => ELECTRICAL_REF
+ );
+ buck_sw2 : entity work.buck_sw(average)
+ port map(
+ ctrl => vctrl,
+ input => vin,
+ ref => ELECTRICAL_REF,
+ output => vmid
+ );
+ comp_2p2z4 : entity work.comp_2p2z(ltf)
+ generic map(
+ fz1 => 403.0,
+ fz2 => 403.0,
+ gain => 100.0
+ )
+ port map(
+ input => vout,
+ output => vcomp_out,
+ ref => vref
+ );
+end TB_CS3_BuckConverter_average;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CalcBuckParams.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CalcBuckParams.vhd
new file mode 100644
index 000000000..296207c0d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CalcBuckParams.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CalcBuckParams is
+end tb_CalcBuckParams;
+
+architecture tb_CalcBuckParams of tb_CalcBuckParams is
+ -- Component declarations
+ -- Signal declarations
+ quantity Cmin : capacitance;
+ quantity freq_in : real;
+ quantity Lmin : inductance;
+begin
+ -- Signal assignments
+ -- Component instances
+ src1 : entity work.src_pulse(ideal)
+ generic map(
+ initial => 25.0e3,
+ pulse => 200.0e3,
+ ti2p => 1ms,
+ tp2i => 1ms,
+ delay => 1ms,
+ width => 100ms,
+ period => 1000ms
+ )
+ port map(
+ output => freq_in
+ );
+ CalcBuckParams1 : entity work.CalcBuckParams_wa(ideal)
+ generic map(
+ Vripple => 100.0e-3,
+ Vin => 42.0,
+ Vout => 4.8,
+ Vd => 0.7,
+ Imin => 15.0e-3,
+ Resr => 50.0e-3
+ )
+ port map(
+ Fsw => freq_in,
+ Lmin => Lmin,
+ Cmin => Cmin
+ );
+end tb_CalcBuckParams;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/MeasFreq.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/MeasFreq.vhd
new file mode 100644
index 000000000..ad51b8704
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/MeasFreq.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity MeasFreq is
+ generic ( thres : real := 0.0 );
+ port ( terminal input : electrical;
+ signal f_out : out real := 0.0 );
+end entity MeasFreq;
+
+----------------------------------------------------------------
+
+architecture ThresDetect of MeasFreq is
+
+ quantity vin across input;
+
+begin
+
+ detect : process ( vin'above(thres) ) is
+ variable t_old : real := real'low;
+ begin
+ if vin'above(thres) then
+ f_out <= 1.0 / (now - t_old);
+ t_old := now;
+ end if;
+ end process detect;
+
+end ThresDetect;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/PLL.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/PLL.vhd
new file mode 100644
index 000000000..62a2162d8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/PLL.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+library ieee; use ieee.math_real.all;
+
+entity PLL is
+
+ generic ( Fp : real := 20.0e3; -- loop filter pole freq [Hz]
+ Fz : real := 1.0e6; -- loop filter zero freq [Hz]
+ Kv : real := 100.0e3; -- VCO gain [Hz/V]
+ Fc : real := 1.0e6 ); -- VCO center freq [Hz]
+
+ port ( terminal input, lf_out, vco_out : electrical );
+
+end entity PLL;
+
+----------------------------------------------------------------
+
+architecture behavioral of PLL is
+
+ quantity v_in across input to electrical_ref;
+ quantity v_lf across i_lf through lf_out to electrical_ref;
+ quantity v_vco across i_vco through vco_out to electrical_ref;
+
+ -- internal quantities and constants
+
+ -- multiplier
+ quantity mult : real;
+
+ -- loop filter (Lag)
+ constant wp : real := math_2_pi * fp; -- pole freq in rad/s
+ constant wz : real := math_2_pi * fz; -- zero freq in rad/s
+ constant num : real_vector := (1.0, 1.0 / wz); -- numerator array
+ constant den : real_vector := (1.0, 1.0 / wp); -- denominator array
+
+ -- VCO
+ quantity phi : real; -- used in VCO equation
+ constant Kv_w : real := math_2_pi * Kv; -- change gain to (rad/s)/V
+ constant wc : real := math_2_pi * Fc; -- change freq to rad/s
+
+begin
+
+ if domain = quiescent_domain use
+ phi == 0.0; -- initialize phi
+ else
+ phi'dot == wc + Kv_w * (v_lf); -- calculate VCO frequency
+ end use;
+
+ mult == v_in * v_vco; -- multiplier output
+
+ v_lf == mult'ltf(num, den); -- loop filter output
+
+ v_vco == cos(phi); -- VCO output
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk.vhd
new file mode 100644
index 000000000..96cc54e42
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee, ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee.std_logic_1164.all;
+use ieee.math_real.all;
+
+entity bfsk is
+
+ generic ( fc : real := 1.0e6; -- mean carrier frequency
+ delta_f : real := 5.0e3; -- difference between low and high
+ -- carrier frequencies
+ amp : voltage := 1.0; -- amplitude of modulated signal
+ offset : voltage := 0.0 ); -- output offset voltage
+
+ port ( signal d_in : in std_logic; -- digital input
+ terminal a_out : electrical ); -- output terminal
+
+end entity bfsk;
+
+----------------------------------------------------------------
+
+architecture behavioral of bfsk is
+
+ quantity vout across iout through a_out; -- output branch
+ quantity phi : real; -- free quantity angle in radians
+ constant wc : real := math_2_pi * fc; -- convert fc to rad/s
+ constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
+
+begin
+
+ if To_X01(d_in) = '0' use
+ phi'dot == wc; -- set to carrier frequency
+ elsif To_X01(d_in) = '1' use
+ phi'dot == wc + delta_w; -- set to carrier frequency + delta
+ else
+ phi'dot == 0.0;
+ end use;
+
+ break on d_in;
+
+ vout == offset + amp * sin(phi); -- create sinusoidal output using phi
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk_wa.vhd
new file mode 100644
index 000000000..3a58538f2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk_wa.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee, ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee.std_logic_1164.all;
+use ieee.math_real.all;
+
+entity bfsk_wa is
+
+ generic ( fc : real := 455.0e3; -- mean carrier frequency
+ delta_f : real := 5.0e3; -- difference between low and high
+ -- carrier frequency
+ amp : voltage := 1.0; -- amplitude of modulated signal
+ offset : voltage := 0.0 ); -- output offset voltage
+
+ port ( signal d_in : in std_logic; -- digital input
+ terminal a_out : electrical ); -- output terminal
+
+end entity bfsk_wa;
+
+----------------------------------------------------------------
+
+architecture behavioral of bfsk_wa is
+
+ quantity vout across iout through a_out; -- output branch
+ quantity phi : real; -- free quantity angle in radians
+ constant wc : real := math_2_pi * fc; -- convert fc to rad/s
+ constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
+
+begin
+
+ if To_X01(d_in) = '0' use
+ phi'dot == wc; -- set to carrier frequency
+ elsif To_X01(d_in) = '1' use
+ phi'dot == wc + delta_w; -- set to carrier frequency + delta
+ else
+ phi'dot == 0.0;
+ end use;
+
+ vout == offset + amp * sin(phi); -- create sinusoidal output using phi
+
+end architecture behavioral;
+
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/index-ams.txt
new file mode 100644
index 000000000..d5ec2129a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/index-ams.txt
@@ -0,0 +1,37 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 23 - Case Study 4: Communications System
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+bfsk.vhd entity bfsk behavioral Figure 23-3
+bfsk_wa.vhd entity bfsk_wa behavioral --
+MeasFreq.vhd entity MeasFreq ThresDetect Figure 23-5
+v_BPF.vhd entity v_BPF behavioral Figure 23-8
+v_Sum.vhd entity v_Sum behavioral Figure 23-9
+PLL.vhd entity PLL behavioral Figure 23-12
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_pll.vhd entity tb_pll tb_pll PLL.vhd
+tb_CS4_CommSys_PLL.vhd entity VCOAnalog behavioral
+-- entity vLeadLag behavioral
+-- entity vMult behavioral
+-- entity PLL PLL
+-- entity bfsk behavioral
+-- entity vLPF_2nd behavioral
+-- entity MeasFreq ThresDetect
+-- entity a2d_bit ideal
+-- entity tb_CS4_CommSys_PLL TB_CS4_CommSys_PLL
+tb_CS4_CommSys_det.vhd entity capacitor ideal
+-- entity resistor ideal
+-- entity diode ideal
+-- entity EnvDetect EnvDetect
+-- entity bfsk behavioral
+-- entity vSum behavioral
+-- entity vLPF_2nd behavioral
+-- entity vBPF behavioral
+-- entity MeasFreq ThresDetect
+-- entity a2d_bit ideal
+-- entity tb_CS4_CommSys_det TB_CS4_CommSys_det
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_PLL.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_PLL.vhd
new file mode 100644
index 000000000..4009d133a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_PLL.vhd
@@ -0,0 +1,639 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : VCOAnalog.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/07/11
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Analog Voltage Controlled Oscillator
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/07/11 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity VCOAnalog is
+ generic (
+ Kv : real := 100.0e3; -- VCO Gain [Hz/Volt]
+ Fc : real := 1.0e6; -- center freq [Hz]
+ Vc : voltage := 2.5; -- input voltage that gives fc [Volts]
+ Vcmin : voltage := 0.0; -- control voltage mininum [Volts]
+ Vcmax : voltage := 5.0; -- control voltage maximum [Volts]
+ Vout_ampl : voltage := 1.0; -- amplitude of output [Volts]
+ Vout_offset : voltage := 0.0 -- offset voltage of output [Volts]
+ );
+ port (
+ terminal v_inp, v_inm, output : electrical);
+end entity VCOAnalog;
+
+-------------------------------------------------------------------------------
+-- VCO Equation:
+-- Fout = Fc + Kv*Vin
+-------------------------------------------------------------------------------
+architecture behavioral of VCOAnalog is
+ quantity vout across iout through output to electrical_ref;
+ quantity vctrl across v_inp to v_inm;
+ quantity phi : real;
+ quantity vtmp : real;
+ constant Kv_w : real := math_2_pi*Kv; -- convert to (Rad/s)/Volt
+ constant wc : real := math_2_pi*Fc; -- convert freq to Rad/s
+
+begin -- ARCHITECTURE behavioral
+
+ if vctrl > Vcmax use -- test control voltage for limits
+ vtmp == Vcmax;
+ elsif vctrl < Vcmin use
+ vtmp == Vcmin;
+ else
+ vtmp == vctrl;
+ end use;
+
+ if domain = quiescent_domain use
+ phi == 0.0;
+ else
+ -- use one of the following equations depending on preference
+ -- phi'dot == Fc + Kv*(vtmp-Vc); -- Calculate output Freq in Rad/s
+ phi'dot == wc + Kv_w*(vtmp-Vc); -- Calculate output Freq in Hz
+ end use;
+
+-- Use one of the following equations depending on phi'dot equation above
+--vout == Vout_offset + Vout_ampl*cos(math_2_pi*phi);
+vout == Vout_offset + Vout_ampl*cos(phi);
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : vLeadLag.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/11/09
+-- Last update: 2001/11/27
+-------------------------------------------------------------------------------
+-- Description: Lead-Lag filter with electrical connections
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/11/09 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vLeadLag is
+
+ generic (
+ K : real := 1.0; -- gain
+ Fp : real := 20.0e3; -- pole frequency
+ Fz : real := 1.0e6); -- zero frequency
+
+ port (
+ terminal input, output : electrical);
+
+end entity vLeadLag;
+
+-------------------------------------------------------------------------------
+-- Transfer Fucntion:
+--
+-- 1 + (s/wz)
+-- H(s) = K * ------------
+-- 1 + (s/wp)
+--
+-------------------------------------------------------------------------------
+
+architecture behavioral of vLeadLag is
+
+ quantity vin across input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ constant wp : real := math_2_pi*Fp; -- Pole freq (in radians)
+ constant wz : real := math_2_pi*Fz; -- Zero freq (in radians)
+ constant num : real_vector := (1.0, 1.0/wz);
+ constant den : real_vector := (1.0, 1.0/wp);
+
+begin
+
+ vout == K * vin'ltf(num, den); -- Laplace transform of input
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : vMult.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/11/09
+-- Last update: 2001/11/09
+-------------------------------------------------------------------------------
+-- Description: Two input Multiplier with electrical connections
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/11/09 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vMult is
+
+ generic (K : real := 1.0); -- Gain
+
+ port (
+ terminal in1, in2 : electrical;
+ terminal output : electrical);
+
+end entity vMult;
+
+architecture behavioral of vMult is
+
+ quantity vin1 across in1 to electrical_ref;
+ quantity vin2 across in2 to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+
+begin
+
+ vout == k * vin1 * vin2;
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity PLL is
+ port(
+ terminal lf_out : electrical;
+ terminal input : electrical;
+ terminal vco_out : electrical
+ );
+end PLL;
+
+architecture PLL of PLL is
+ -- Component declarations
+ -- Signal declarations
+ terminal pd_out : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ vco2 : entity work.VCOAnalog(behavioral)
+ generic map(
+ Fc => 455.0e3,
+ Vcmax => 5.0,
+ Vcmin => -5.0,
+ Vc => 0.0
+ )
+ port map(
+ v_inp => lf_out,
+ output => vco_out,
+ v_inm => ELECTRICAL_REF
+ );
+ vLeadLag1 : entity work.vLeadLag(behavioral)
+ generic map(
+ Fz => 500.0e3
+ )
+ port map(
+ input => pd_out,
+ output => lf_out
+ );
+ vmult1 : entity work.vMult(behavioral)
+ port map(
+ in1 => input,
+ in2 => vco_out,
+ output => pd_out
+ );
+end PLL;
+--
+
+-- Model of Binary Frequency Shift Keying (BFSK) modulator
+-- with digital input and analog output
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.MATH_REAL.all;
+
+entity bfsk is
+ generic (
+ fc : real := 455.0e3; -- Mean carrier frequency
+ delta_f : real := 5.0e3; -- Difference between low and high carrier frequency
+ amp : voltage := 1.0; -- Amplitude of modulated signal
+ offset : voltage := 0.0 -- output offset voltage
+ );
+
+ port (
+ d_in : in std_logic; -- digital input
+ terminal a_out : electrical -- output terminal
+ );
+end entity bfsk;
+
+architecture behavioral of bfsk is
+
+ quantity vout across iout through a_out; -- output branch
+ quantity phi : real; -- free quantity for angle in radians
+ constant wc : real := math_2_pi*fc; -- convert fc to rad/s
+ constant delta_w : real := math_2_pi*delta_f; -- convert delta_f to rad/s
+
+begin
+
+ if (d_in = '0') use
+ phi'dot == wc; -- set to carrier frequency
+ elsif (d_in = '1') use
+ phi'dot == wc + delta_w; -- set to carrier frequency + delta
+ else
+ phi'dot == 0.0;
+ end use;
+
+ vout == offset + amp*sin(phi); -- create sinusoidal output using phi
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : vLPF_2nd.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/11/27
+-- Last update: 2001/11/27
+-------------------------------------------------------------------------------
+-- Description: 2nd order Lowpass Filter with Electrical connections
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/11/27 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.MATH_REAL.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vLPF_2nd is
+ generic ( K : real := 1.0; -- Filter Gain
+ Fp : real; -- Double Pole Frequency [Hz]
+ Q : real := 0.707 -- Quality factor
+ );
+ port ( terminal input : electrical;
+ terminal output : electrical
+ );
+end entity vLPF_2nd;
+-------------------------------------------------------------------------------
+-- Transfer Function:
+--
+-- wp^2
+-- Vo(s) = K * --------------------- Vin(s)
+-- S^2 + (wp/Q)*s + wp^2
+-------------------------------------------------------------------------------
+architecture behavioral of vLPF_2nd is
+ quantity vin across input;
+ quantity vout across iout through output;
+
+ constant wp : real := math_2_pi*Fp; -- Frequency in Radians
+ constant num : real_vector := (wp*wp, 0.0, 0.0); -- Numerator array
+ constant den : real_vector := (wp*wp, wp/Q, 1.0); -- Denominator array
+
+begin
+
+ vout == K * vin'ltf(num, den); -- Laplace Transform of input
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+
+entity MeasFreq is
+ generic ( thres : real := 0.0 ); -- threshold crossing
+ port ( terminal input : electrical;
+ signal f_out : out real := 0.0);
+end entity MeasFreq;
+
+architecture ThresDetect of MeasFreq is
+ quantity vin across input;
+-- signal freq : real := 0.0;
+begin
+-- f_out <= freq;
+ detect : process (vin'above(thres)) is
+ variable t_old : real := real'low;
+ begin
+ if vin'above(thres) then
+ f_out <= 1.0 / (now - t_old);
+ t_old := now;
+ end if;
+ end process detect;
+end ThresDetect;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : a2d_bit.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Ideal one bit A/D converter
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+use IEEE.std_logic_1164.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity a2d_bit is
+
+ generic (
+ thres : real := 2.5); -- Threshold to determine logic output
+
+ port (
+ terminal a : electrical; -- analog input
+ signal d : out std_logic); -- digital (std_logic) output
+
+end entity a2d_bit;
+
+-------------------------------------------------------------------------------
+-- Ideal architecture
+-- Uses 'above operator to detect threshold crossing
+-------------------------------------------------------------------------------
+architecture ideal of a2d_bit is
+
+ quantity vin across a;
+
+begin
+
+ -- purpose: Detect threshold crossing and assign event on output (d)
+ -- type : combinational
+ -- inputs : vin'above(thres)
+ -- outputs: pulse_signal
+ process (vin'above(thres)) is
+ begin -- PROCESS
+ if vin'above(thres) then
+ d <= '1';
+ else
+ d <= '0';
+ end if;
+ end process;
+
+end ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity tb_CS4_CommSys_PLL is
+end tb_CS4_CommSys_PLL;
+
+architecture TB_CS4_CommSys_PLL of tb_CS4_CommSys_PLL is
+ -- Component declarations
+ -- Signal declarations
+ terminal a_out : electrical;
+ signal baseband : std_logic;
+ terminal fsk_out : electrical;
+ signal fsk_out_f : real;
+ terminal lpf_pll_out : electrical;
+ terminal vco_out : electrical;
+ signal bitstream : std_logic;
+ signal vco_out_f : real;
+begin
+ -- Signal assignments
+ -- Component instances
+ pll3 : entity work.PLL
+ port map(
+ vco_out => vco_out,
+ input => fsk_out,
+ lf_out => lpf_pll_out
+ );
+ BFSK4 : entity work.bfsk(behavioral)
+ port map(
+ d_in => bitstream,
+ a_out => fsk_out
+ );
+ vLPF1 : entity work.vLPF_2nd(behavioral)
+ generic map(
+ K => 200.0,
+ Fp => 50.0e3
+ )
+ port map(
+ input => lpf_pll_out,
+ output => a_out
+ );
+ MeasFreq8 : entity work.MeasFreq(ThresDetect)
+ port map(
+ input => fsk_out,
+ f_out => fsk_out_f
+ );
+ MeasFreq9 : entity work.MeasFreq(ThresDetect)
+ port map(
+ input => vco_out,
+ f_out => vco_out_f
+ );
+ a4 : entity work.a2d_bit(ideal)
+ port map(
+ D => baseband,
+ A => a_out
+ );
+ -- bitstream
+ P_bitstream :
+ process
+ begin
+ -- 0.000
+ wait for 0.000 ns; bitstream <= '0';
+ -- 50000.000
+ wait for 50000.000 ns; bitstream <= '1';
+ -- 100000.000
+ wait for 50000.000 ns; bitstream <= '0';
+ -- 150000.000
+ wait for 50000.000 ns; bitstream <= '1';
+ -- 200000.000
+ wait for 50000.000 ns; bitstream <= '0';
+ -- 300000.000
+ wait for 100000.000 ns; bitstream <= '1';
+ -- 501000.000
+ wait for 201000.000 ns; bitstream <= '0';
+ -- 550000.000
+ wait for 49000.000 ns; bitstream <= '1';
+ -- 600000.000
+ wait for 50000.000 ns; bitstream <= '0';
+ wait;
+ end process;
+
+end TB_CS4_CommSys_PLL;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_det.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_det.vhd
new file mode 100644
index 000000000..6e989b326
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_det.vhd
@@ -0,0 +1,830 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : capacitor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Electrical Capacitor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity capacitor is
+
+ generic (
+ cap : capacitance; -- Capacitance [F]
+ v_ic : real := real'low); -- Initial voltage (activated by
+ -- IF statement below)
+
+ port (
+ terminal p1, p2 : electrical);
+
+end entity capacitor;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture (I = C * dV/dt)
+-- Includes initial condition
+-------------------------------------------------------------------------------
+architecture ideal of capacitor is
+
+ quantity v across i through p1 to p2;
+
+begin
+
+ if domain = quiescent_domain and v_ic /= real'low use
+ v == v_ic;
+ else
+ i == cap * v'dot; -- characteristic equation
+ end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : resistor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Electrical Resistor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity resistor is
+
+ generic (
+ res : resistance); -- resistance (no initial value)
+
+ port (
+ terminal p1, p2 : electrical);
+
+end entity resistor;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture (V = I*R)
+-------------------------------------------------------------------------------
+architecture ideal of resistor is
+
+ quantity v across i through p1 to p2;
+
+begin
+
+-- Characteristic equation
+ v == i*res;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : diode.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/11/07
+-------------------------------------------------------------------------------
+-- Description: Diode model with ideal architecture
+-- Currently no Generics due to bug in DV
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-- 2001/11/07 1.1 Mentor Graphics Added limit_exp function
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
+use IEEE_proposed.energy_systems.all;
+
+entity diode is
+
+ port (
+ terminal p, n : electrical);
+
+end entity diode;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture: i = is*(exp(v/vt) - 1)
+-------------------------------------------------------------------------------
+architecture ideal of diode is
+
+-- Declare internal quanties and constants
+ quantity v across i through p to n;
+ constant isat : current := 1.0e-14; -- Saturation current [Amps]
+ constant TempC : real := 27.0; -- Ambient Temperature [Degrees]
+ constant TempK : real := 273.0 + TempC; -- Temperaure [Kelvin]
+ constant vt : real := K*TempK/Q; -- Thermal Voltage
+
+ -- This function is to limit the exponential function to avoid convergence
+ -- problems due to numerical overflow. At x=100, it becomes a straight line
+ -- with slope matching that at the intercept.
+ function limit_exp( x : real ) return real is
+ variable abs_x : real := abs(x);
+ variable result : real;
+ begin
+ if abs_x < 100.0 then
+ result := exp(abs_x);
+ else
+ result := exp(100.0) * (abs_x - 99.0);
+ end if;
+ -- If exponent is negative, set exp(-x) = 1/exp(x)
+ if x < 0.0 then
+ result := 1.0 / result;
+ end if;
+ return result;
+ end function limit_exp;
+begin -- ideal architecture
+
+-- Characteristic equation
+ i == isat*(limit_exp(v/vt) - 1.0);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity EnvDetect is
+ port(
+ terminal input : electrical;
+ terminal output : electrical
+ );
+end EnvDetect;
+
+architecture EnvDetect of EnvDetect is
+ -- Component declarations
+ -- Signal declarations
+ terminal XSIG010001 : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ C1 : entity work.capacitor(ideal)
+ generic map(
+ cap => 0.1e-6
+ )
+ port map(
+ p1 => XSIG010001,
+ p2 => ELECTRICAL_REF
+ );
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 1.0e3
+ )
+ port map(
+ p1 => XSIG010001,
+ p2 => ELECTRICAL_REF
+ );
+ D4 : entity work.diode(ideal)
+ port map(
+ p => input,
+ n => XSIG010001
+ );
+ C2 : entity work.capacitor(ideal)
+ generic map(
+ cap => 6.0e-6
+ )
+ port map(
+ p1 => XSIG010001,
+ p2 => output
+ );
+ R6 : entity work.resistor(ideal)
+ generic map(
+ res => 1.0e3
+ )
+ port map(
+ p1 => output,
+ p2 => ELECTRICAL_REF
+ );
+end EnvDetect;
+--
+
+-- Model of Binary Frequency Shift Keying (BFSK) modulator
+-- with digital input and analog output
+
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.MATH_REAL.all;
+
+entity bfsk is
+ generic (
+ fc : real := 455.0e3; -- Mean carrier frequency
+ delta_f : real := 5.0e3; -- Difference between low and high carrier frequency
+ amp : voltage := 1.0; -- Amplitude of modulated signal
+ offset : voltage := 0.0 -- output offset voltage
+ );
+
+ port (
+ d_in : in std_logic; -- digital input
+ terminal a_out : electrical -- output terminal
+ );
+end entity bfsk;
+
+architecture behavioral of bfsk is
+
+ quantity vout across iout through a_out; -- output branch
+ quantity phi : real; -- free quantity for angle in radians
+ constant wc : real := math_2_pi*fc; -- convert fc to rad/s
+ constant delta_w : real := math_2_pi*delta_f; -- convert delta_f to rad/s
+
+begin
+
+ if (d_in = '0') use
+ phi'dot == wc; -- set to carrier frequency
+ elsif (d_in = '1') use
+ phi'dot == wc + delta_w; -- set to carrier frequency + delta
+ else
+ phi'dot == 0.0;
+ end use;
+
+ vout == offset + amp*sin(phi); -- create sinusoidal output using phi
+
+end architecture behavioral;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : vSum.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/11/09
+-- Last update: 2001/11/09
+-------------------------------------------------------------------------------
+-- Description: Summing junction with electrical connections
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/11/09 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vSum is
+
+ generic (
+ K1 : real := 1.0;
+ K2 : real := -1.0);
+
+ port (
+ terminal in1, in2 : electrical;
+ terminal output : electrical);
+
+end entity vSum;
+
+architecture behavioral of vSum is
+
+ quantity vin1 across in1 to electrical_ref;
+ quantity vin2 across in2 to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+
+begin
+
+ vout == K1*vin1 + K2*vin2;
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : vLPF_2nd.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/11/27
+-- Last update: 2001/11/27
+-------------------------------------------------------------------------------
+-- Description: 2nd order Lowpass Filter with Electrical connections
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/11/27 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.MATH_REAL.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vLPF_2nd is
+ generic ( K : real := 1.0; -- Filter Gain
+ Fp : real; -- Double Pole Frequency [Hz]
+ Q : real := 0.707 -- Quality factor
+ );
+ port ( terminal input : electrical;
+ terminal output : electrical
+ );
+end entity vLPF_2nd;
+-------------------------------------------------------------------------------
+-- Transfer Function:
+--
+-- wp^2
+-- Vo(s) = K * --------------------- Vin(s)
+-- S^2 + (wp/Q)*s + wp^2
+-------------------------------------------------------------------------------
+architecture behavioral of vLPF_2nd is
+ quantity vin across input;
+ quantity vout across iout through output;
+
+ constant wp : real := math_2_pi*Fp; -- Frequency in Radians
+ constant num : real_vector := (wp*wp, 0.0, 0.0); -- Numerator array
+ constant den : real_vector := (wp*wp, wp/Q, 1.0); -- Denominator array
+
+begin
+
+ vout == K * vin'ltf(num, den); -- Laplace Transform of input
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : vBPF.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/11/27
+-- Last update: 2001/11/27
+-------------------------------------------------------------------------------
+-- Description: Bandpass Filter with Electrical connections
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/11/27 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vBPF is
+ generic ( K : real := 1.0; -- Filter Gain
+ Fc : real; -- Center Frequency [Hz]
+ Q : real := 0.707 -- Quality factor
+ );
+ port ( terminal input : electrical;
+ terminal output : electrical
+ );
+end entity vBPF;
+-------------------------------------------------------------------------------
+-- Transfer Function:
+--
+-- wc*s
+-- Vo(s) = K * --------------------- Vin(s)
+-- S^2 + (wc/Q)*s + wc^2
+-------------------------------------------------------------------------------
+architecture behavioral of vBPF is
+ quantity vin across input;
+ quantity vout across iout through output;
+
+ constant wc : real := math_2_pi*Fc; -- Frequency in Radians
+ constant num : real_vector := (0.0, wc); -- Numerator array
+ constant den : real_vector := (wc*wc, wc/Q, 1.0); -- Denominator array
+
+begin
+
+ vout == K * vin'ltf(num, den); -- Laplace Transform of output
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+
+entity MeasFreq is
+ generic ( thres : real := 0.0 ); -- threshold crossing
+ port ( terminal input : electrical;
+ signal f_out : out real := 0.0);
+end entity MeasFreq;
+
+architecture ThresDetect of MeasFreq is
+ quantity vin across input;
+-- signal freq : real := 0.0;
+begin
+-- f_out <= freq;
+ detect : process (vin'above(thres)) is
+ variable t_old : real := real'low;
+ begin
+ if vin'above(thres) then
+ f_out <= 1.0 / (now - t_old);
+ t_old := now;
+ end if;
+ end process detect;
+end ThresDetect;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : a2d_bit.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Ideal one bit A/D converter
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+use IEEE.std_logic_1164.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity a2d_bit is
+
+ generic (
+ thres : real := 2.5); -- Threshold to determine logic output
+
+ port (
+ terminal a : electrical; -- analog input
+ signal d : out std_logic); -- digital (std_logic) output
+
+end entity a2d_bit;
+
+-------------------------------------------------------------------------------
+-- Ideal architecture
+-- Uses 'above operator to detect threshold crossing
+-------------------------------------------------------------------------------
+architecture ideal of a2d_bit is
+
+ quantity vin across a;
+
+begin
+
+ -- purpose: Detect threshold crossing and assign event on output (d)
+ -- type : combinational
+ -- inputs : vin'above(thres)
+ -- outputs: pulse_signal
+ process (vin'above(thres)) is
+ begin -- PROCESS
+ if vin'above(thres) then
+ d <= '1';
+ else
+ d <= '0';
+ end if;
+ end process;
+
+end ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity tb_CS4_CommSys_det is
+end tb_CS4_CommSys_det;
+
+architecture TB_CS4_CommSys_det of tb_CS4_CommSys_det is
+ -- Component declarations
+ -- Signal declarations
+ signal baseband : std_logic;
+ signal bitstream : std_logic;
+ terminal bp1_out : electrical;
+ terminal bp2_out : electrical;
+ terminal ed1_out : electrical;
+ terminal ed2_out : electrical;
+ terminal fsk_out : electrical;
+ signal fsk_out_f : real;
+ terminal lna_in : electrical;
+ terminal lna_out : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ EnvDetect1 : entity work.EnvDetect
+ port map(
+ output => ed1_out,
+ input => bp1_out
+ );
+ EnvDetect2 : entity work.EnvDetect
+ port map(
+ output => ed2_out,
+ input => bp2_out
+ );
+ BFSK3 : entity work.bfsk(behavioral)
+ generic map(
+ amp => 5.0
+ )
+ port map(
+ d_in => bitstream,
+ a_out => fsk_out
+ );
+ vsum1 : entity work.vSum(behavioral)
+ port map(
+ in1 => ed1_out,
+ in2 => ed2_out,
+ output => lna_in
+ );
+ vLPF2 : entity work.vLPF_2nd(behavioral)
+ generic map(
+ Fp => 20.0e3,
+ K => 10000.0
+ )
+ port map(
+ input => lna_in,
+ output => lna_out
+ );
+ vBPF2 : entity work.vBPF(behavioral)
+ generic map(
+ Fc => 455.0e3
+ )
+ port map(
+ input => fsk_out,
+ output => bp2_out
+ );
+ vBPF3 : entity work.vBPF(behavioral)
+ generic map(
+ Fc => 460.0e3
+ )
+ port map(
+ input => fsk_out,
+ output => bp1_out
+ );
+ MeasFreq6 : entity work.MeasFreq(ThresDetect)
+ port map(
+ input => fsk_out,
+ f_out => fsk_out_f
+ );
+ a2 : entity work.a2d_bit(ideal)
+ generic map(
+ thres => 1.0
+ )
+ port map(
+ D => baseband,
+ A => lna_out
+ );
+ -- bitstream
+ P_bitstream :
+ process
+ begin
+ -- 0.000
+ wait for 0.000 ns; bitstream <= '0';
+ -- 50000.000
+ wait for 50000.000 ns; bitstream <= '1';
+ -- 100000.000
+ wait for 50000.000 ns; bitstream <= '0';
+ -- 150000.000
+ wait for 50000.000 ns; bitstream <= '1';
+ -- 200000.000
+ wait for 50000.000 ns; bitstream <= '0';
+ -- 300000.000
+ wait for 100000.000 ns; bitstream <= '1';
+ -- 501000.000
+ wait for 201000.000 ns; bitstream <= '0';
+ -- 550000.000
+ wait for 49000.000 ns; bitstream <= '1';
+ -- 600000.000
+ wait for 50000.000 ns; bitstream <= '0';
+ wait;
+ end process;
+
+-- KillerProc :
+-- process
+-- begin
+-- wait for 1 ns;
+-- lclclkinitwire <= '1';
+-- wait;
+-- end process;
+end TB_CS4_CommSys_det;
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_pll.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_pll.vhd
new file mode 100644
index 000000000..7b23d0587
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_pll.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+--
+-- File : C:\VHDL-AMS\CaseStudies\CS4_CommSystem\Default\genhdl\vhdl\tb_pll.vhd
+-- CDB : C:\VHDL-AMS\CaseStudies\CS4_CommSystem\default\default.cdb
+-- By : CDB2VHDL Netlister version 16.1.0.2
+-- Time : Fri Apr 05 12:08:46 2002
+
+-- Entity/architecture declarations
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity tb_pll is
+end tb_pll;
+
+architecture tb_pll of tb_pll is
+ -- Component declarations
+ -- Signal declarations
+ signal f_ref : real;
+ terminal lf_out : electrical;
+ terminal v_ref : electrical;
+ signal vco_f : real;
+ terminal vco_out : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ PLL6 : entity work.PLL(behavioral)
+ generic map(
+ Fp => 20.0e3,
+ Fz => 1.0e6,
+ Kv => 100.0e3,
+ Fc => 1.0e6
+ )
+ port map(
+ input => v_ref,
+ lf_out => lf_out,
+ vco_out => vco_out
+ );
+ v1 : entity work.v_SweptSine(bhv)
+ generic map(
+ StartFreq => 900.0e3,
+ SweepRate => 2000.0e6,
+ FinishFreq => 1.1e6,
+ InitDelay => 80.0e-6,
+ PeakAmp => 5.0
+ )
+ port map(
+ pos => v_ref,
+ neg => ELECTRICAL_REF
+ );
+ MeasFreq9 : entity work.MeasFreq(ThresDetect)
+ port map(
+ input => v_ref,
+ f_out => f_ref
+ );
+ MeasFreq10 : entity work.MeasFreq(ThresDetect)
+ port map(
+ input => vco_out,
+ f_out => vco_f
+ );
+end tb_pll;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_BPF.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_BPF.vhd
new file mode 100644
index 000000000..6558c1c85
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_BPF.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity v_BPF is
+
+ generic ( k : real := 1.0; -- filter gain
+ fo : real := 100.0e3; -- center frequency [Hz]
+ q : real := 0.707 ); -- quality factor
+
+ port ( terminal input : electrical;
+ terminal output : electrical );
+
+end entity v_BPF;
+
+----------------------------------------------------------------
+
+architecture behavioral of v_BPF is
+
+ quantity vin across input;
+ quantity vout across iout through output;
+ constant wo : real := math_2_pi * fo; -- frequency in radians
+ constant num : real_vector := (0.0, wo); -- numerator array
+ constant den : real_vector := (wo * wo, wo / q, 1.0); -- denominator array
+
+begin
+
+ vout == k * vin'ltf(num, den); -- Laplace transform of output
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_Sum.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_Sum.vhd
new file mode 100644
index 000000000..e3d4c1e2d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_Sum.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity v_Sum is
+ generic ( k1 : real := 1.0;
+ k2 : real := -1.0 );
+ port ( terminal in1, in2 : electrical;
+ terminal output : electrical );
+end entity v_Sum;
+
+----------------------------------------------------------------
+
+architecture behavioral of v_Sum is
+
+ quantity vin1 across in1 to electrical_ref;
+ quantity vin2 across in2 to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+
+begin
+
+ vout == k1 * vin1 + k2 * vin2;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/amp_lim.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/amp_lim.vhd
new file mode 100644
index 000000000..8c1059dce
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/amp_lim.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity amp_lim is
+ port ( terminal ps : electrical; -- positive supply terminal
+ terminal input, output : electrical );
+end entity amp_lim;
+
+----------------------------------------------------------------
+
+architecture simple of amp_lim is
+
+ quantity v_pwr across i_pwr through ps to electrical_ref;
+ quantity vin across iin through input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ quantity v_amplified : voltage ;
+ constant gain : real := 1.0;
+
+begin
+
+ v_amplified == gain * vin;
+
+ if v_amplified'above(v_pwr) use
+ vout == v_pwr;
+ else
+ vout == v_amplified;
+ end use;
+
+ break on v_amplified'above(v_pwr);
+
+ -- ignore loading effects
+ i_pwr == 0.0;
+ iin == 0.0;
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/index-ams.txt
new file mode 100644
index 000000000..13d7da7e0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/index-ams.txt
@@ -0,0 +1,200 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 26 - Case Study 5: RC Airplane System
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+amp_lim.vhd entity amp_lim simple Figure 26-10
+pwl_functions.vhd package pwl_functions body Figure 26-20
+prop_pwl.vhd entity prop_pwl ideal Figure 26-20
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_CS5_Amp_Lim.vhd entity sum2_e simple
+-- entity gain_e simple
+-- entity limiter_2_e simple
+-- entity lead_lag_e simple
+-- entity rudder_servo rudder_servo
+-- entity gear_rv_r ideal
+-- entity rot2v bhv
+-- entity horn_r2t bhv
+-- entity horn_t2r bhv
+-- entity DC_Motor basic
+-- entity stop_r ideal
+-- entity tran_linkage a1
+-- entity rudder bhv
+-- entity resistor ideal
+-- entity amp_lim simple
+-- entity v_pulse ideal
+-- entity v_pwl_full ideal
+-- entity tb_CS5_Amp_Lim TB_CS5_Amp_Lim
+tb_CS5_Prop.vhd entity DC_Motor basic
+-- entity v_constant ideal
+-- entity switch_dig_log linear
+-- entity switch_dig_log log
+-- entity opamp basic
+-- entity resistor ideal
+-- entity comparator_d behavioral
+-- entity v_pulse ideal
+-- entity pwm_mac pwm_mac
+-- entity prop_pwl ideal
+-- entity diode_pwl simple
+-- entity v_sine ideal
+-- entity tb_CS5_Prop TB_CS5_Prop
+tb_CS5_CC_Rudder.vhd entity sum2_e simple
+-- entity gain_e simple
+-- entity limiter_2_e simple
+-- entity lead_lag_e simple
+-- entity rudder_servo rudder_servo
+-- entity gear_rv_r ideal
+-- entity rot2v bhv
+-- entity horn_r2t bhv
+-- entity horn_t2r bhv
+-- entity tran_linkage a1
+-- entity rudder bhv
+-- entity v_constant ideal
+-- entity stick ideal
+-- entity RF_xmtr_rcvr behavioral
+-- entity switch_dig_2in ideal
+-- entity clock ideal
+-- entity clock_duty ideal
+-- entity rc_clk rc_clk
+-- entity bit_cnt behavioral
+-- entity state_mach1 state_diagram
+-- entity sm_cnt sm_cnt
+-- entity a2d_nbit sar
+-- entity shift_reg behavioral
+-- entity frame_gen simple
+-- entity xor2 ideal
+-- entity level_set_tri ideal
+-- entity buffer_tri ideal
+-- entity d2a_bit ideal
+-- entity parity_gen parity_gen
+-- entity tdm_encoder tdm_encoder
+-- entity menc_rsc bhv
+-- entity Digitize_Encode_Man Digitize_Encode_Man
+-- entity lpf_2_e simple
+-- entity and2 ideal
+-- entity d_latch_n_edge_rst behav
+-- entity counter_12 counter_12
+-- entity a2d_bit ideal
+-- entity clock_en ideal
+-- entity inverter ideal
+-- entity or2 ideal
+-- entity d2a_nbit behavioral
+-- entity pw2ana pw2ana
+-- entity DC_Motor basic
+-- entity stop_r ideal
+-- entity dig_cmp simple
+-- entity resistor ideal
+-- entity sr_ff simple
+-- entity state_mach_rcvr state_diagram
+-- entity sm_cnt_rcvr sm_cnt_rcvr
+-- entity level_set ideal
+-- entity ser2par a1
+-- entity frame_det simple
+-- entity parity_det parity_det
+-- entity TDM_Demux_dbg TDM_Demux_dbg
+-- entity mdec_rsc bhv
+-- entity mdec_rsc bhv_8
+-- entity Decode_PW_Man Decode_PW_Man
+-- entity tb_CS5_CC_Rudder TB_CS5_CC_Rudder
+tb_CS5_Rudder_Power.vhd entity sum2_e simple
+-- entity gain_e simple
+-- entity limiter_2_e simple
+-- entity lead_lag_e simple
+-- entity rudder_servo rudder_servo
+-- entity gear_rv_r ideal
+-- entity rot2v bhv
+-- entity horn_r2t bhv
+-- entity horn_t2r bhv
+-- entity DC_Motor basic
+-- entity stop_r ideal
+-- entity tran_linkage a1
+-- entity rudder bhv
+-- entity switch_dig_log linear
+-- entity switch_dig_log log
+-- entity buff ideal
+-- entity inverter ideal
+-- entity opamp basic
+-- entity resistor ideal
+-- entity v_constant ideal
+-- entity comparator_d behavioral
+-- entity v_pulse ideal
+-- entity pwm_mac pwm_mac
+-- entity diode_pwl simple
+-- entity pwm_H_bridge pwm_H_bridge
+-- entity stick ideal
+-- entity inductor ideal
+-- entity capacitor ideal
+-- entity capacitor ESR
+-- entity buck_sw average
+-- entity sw_LoopCtrl ideal
+-- entity comp_2p2z ltf
+-- entity ex_buck ex_buck
+-- entity tb_CS5_Rudder_Power TB_CS5_Rudder_Power
+tb_CS5_HCL.vhd entity sum2_e simple
+-- entity gain_e simple
+-- entity limiter_2_e simple
+-- entity lead_lag_e simple
+-- entity rudder_servo rudder_servo
+-- entity gear_rv_r ideal
+-- entity rot2v bhv
+-- entity horn_r2t bhv
+-- entity horn_t2r bhv
+-- entity DC_Motor basic
+-- entity stop_r ideal
+-- entity tran_linkage a1
+-- entity rudder bhv
+-- entity v_constant ideal
+-- entity stick ideal
+-- entity RF_xmtr_rcvr behavioral
+-- entity switch_dig_2in ideal
+-- entity clock ideal
+-- entity clock_duty ideal
+-- entity rc_clk rc_clk
+-- entity bit_cnt behavioral
+-- entity state_mach1 state_diagram
+-- entity sm_cnt sm_cnt
+-- entity a2d_nbit sar
+-- entity shift_reg behavioral
+-- entity frame_gen simple
+-- entity xor2 ideal
+-- entity level_set_tri ideal
+-- entity buffer_tri ideal
+-- entity d2a_bit ideal
+-- entity parity_gen parity_gen
+-- entity tdm_encoder tdm_encoder
+-- entity menc_rsc bhv
+-- entity Digitize_Encode_Man Digitize_Encode_Man
+-- entity and2 ideal
+-- entity d_latch_n_edge_rst behav
+-- entity counter_12 counter_12
+-- entity dig_cmp simple
+-- entity resistor ideal
+-- entity clock_en ideal
+-- entity sr_ff simple
+-- entity inverter ideal
+-- entity state_mach_rcvr state_diagram
+-- entity sm_cnt_rcvr sm_cnt_rcvr
+-- entity level_set ideal
+-- entity ser2par a1
+-- entity frame_det simple
+-- entity parity_det parity_det
+-- entity d2a_nbit behavioral
+-- entity TDM_Demux_dbg TDM_Demux_dbg
+-- entity mdec_rsc bhv
+-- entity mdec_rsc bhv_8
+-- entity Decode_PW_Man Decode_PW_Man
+-- entity lpf_2_e simple
+-- entity a2d_bit ideal
+-- entity or2 ideal
+-- entity pw2ana pw2ana
+-- entity v_pulse ideal
+-- entity v_pwl ideal
+-- entity plane_pos_src plane_pos_src
+-- entity integ_1_e simple
+-- entity lpf_1_e simple
+-- entity hcl hcl
+-- entity tb_CS5_HCL TB_CS5_HCL
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/prop_pwl.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/prop_pwl.vhd
new file mode 100644
index 000000000..739a9c40c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/prop_pwl.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.mechanical_systems.all;
+
+entity prop_pwl is
+ generic ( ydata : real_vector; -- torque data points
+ xdata : real_vector ); -- velocity data points
+ port ( terminal shaft1 : rotational_v );
+end entity prop_pwl;
+
+----------------------------------------------------------------
+
+architecture ideal of prop_pwl is
+
+ use work.pwl_functions.all;
+
+ quantity w across torq through shaft1 to rotational_v_ref;
+
+begin
+
+ torq == pwl_dim1_extrap(w, xdata, ydata);
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd
new file mode 100644
index 000000000..f45a8158b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+
+package pwl_functions is
+
+ function pwl_dim1_extrap ( x : in real; xdata, ydata : in real_vector )
+ return real;
+
+ function interpolate (x,y2,y1,x2,x1 : in real)
+ return real;
+
+ function extrapolate (x,y2,y1,x2,x1 : in real)
+ return real;
+
+end package pwl_functions;
+
+
+package body pwl_functions is
+
+ -- code from book
+
+ function pwl_dim1_extrap ( x : in real; xdata, ydata : in real_vector )
+ return real is
+
+ variable xvalue, yvalue, m : real;
+ variable start, fin, mid: integer;
+
+ begin
+ if x <= xdata(0) then
+ yvalue := extrapolate ( x, ydata(1), ydata(0), xdata(1), xdata(0) );
+ return yvalue;
+ end if;
+
+ if x >= xdata(xdata'right) then
+ yvalue := extrapolate( x, ydata(ydata'right), ydata(ydata'right - 1),
+ xdata(xdata'right), xdata(xdata'right - 1) );
+ return yvalue;
+ end if;
+
+ start := 0;
+ fin := xdata'right;
+ while start <= fin loop
+ mid := (start + fin) / 2;
+ if xdata(mid) < x then
+ start := mid + 1;
+ else
+ fin := mid - 1;
+ end if;
+ end loop;
+ if xdata(mid) > x then
+ mid := mid - 1;
+ end if;
+ yvalue := interpolate( x, ydata(mid + 1), ydata(mid),
+ xdata(mid + 1), xdata(mid) );
+ return yvalue;
+ end function pwl_dim1_extrap;
+
+ -- end code from book
+
+ function interpolate (x,y2,y1,x2,x1 : in real)
+ return real is
+ variable m, yvalue : real;
+ begin
+ assert (x1 /= x2)
+ report "interpolate: x1 cannot be equal to x2"
+ severity error;
+ assert (x >= x1) and (x <= x2)
+ report "interpolate: x must be between x1 and x2, inclusively "
+ severity error;
+ m := (y2 - y1)/(x2 - x1);
+ yvalue := y1 + m*(x - x1);
+ return yvalue;
+ end function interpolate;
+
+ function extrapolate (x,y2,y1,x2,x1 : in real)
+ return real is
+ variable m, yvalue : real;
+ begin
+ assert (x1 /= x2)
+ report "extrapolate: x1 cannot be equal to x2"
+ severity error;
+ assert (x <= x1) or (x >= x2)
+ report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
+ severity warning;
+ m := (y2 - y1)/(x2 - x1);
+ yvalue := y1 + m*(x - x1);
+ return yvalue;
+ end function extrapolate;
+
+end package body pwl_functions;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
new file mode 100644
index 000000000..41fedb4a0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
@@ -0,0 +1,1095 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+ generic (k1, k2: real := 1.0); -- Gain multipliers
+ port ( terminal in1, in2: electrical;
+ terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+ QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+ QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+ generic (
+ k: REAL := 1.0); -- Gain multiplier
+ port ( terminal input : electrical;
+ terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+ generic (
+ limit_high : real := 4.8; -- upper limit
+ limit_low : real := -4.8); -- lower limit
+ port (
+ terminal input: electrical;
+ terminal output: electrical);
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+ constant slope : real := 1.0e-4;
+begin
+ if vin > limit_high use -- Upper limit exceeded, so limit input signal
+ vout == limit_high + slope*(vin - limit_high);
+ elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
+ vout == limit_low + slope*(vin - limit_low);
+ else -- No limit exceeded, so pass input signal as is
+ vout == vin;
+ end use;
+ break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+-- Transfer Function:
+--
+-- (s + w1)
+-- H(s) = k * ----------
+-- (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lead_lag_e is
+ generic (
+ k: real := 1.0; -- Gain multiplier
+ f1: real := 10.0; -- First break frequency (zero)
+ f2: real := 100.0); -- Second break frequency (pole)
+ port ( terminal input: electrical;
+ terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ quantity vin_temp : real;
+ constant w1 : real := f1*math_2_pi;
+ constant w2 : real := f2*math_2_pi;
+ constant num : real_vector := (w1, 1.0);
+ constant den : real_vector := (w2, 1.0);
+begin
+ vin_temp == vin;
+ vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo is
+ port(
+ terminal servo_in : electrical;
+ terminal pos_fb : electrical;
+ terminal servo_out : electrical
+ );
+end rudder_servo;
+
+architecture rudder_servo of rudder_servo is
+ -- Component declarations
+ -- Signal declarations
+ terminal error : electrical;
+ terminal ll_in : electrical;
+ terminal ll_out : electrical;
+ terminal summer_fb : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ summer : entity work.sum2_e(simple)
+ port map(
+ in1 => servo_in,
+ in2 => summer_fb,
+ output => error
+ );
+ forward_gain : entity work.gain_e(simple)
+ generic map(
+ k => 100.0
+ )
+ port map(
+ input => error,
+ output => ll_in
+ );
+ fb_gain : entity work.gain_e(simple)
+ generic map(
+ k => -4.57
+ )
+ port map(
+ input => pos_fb,
+ output => summer_fb
+ );
+ XCMP21 : entity work.limiter_2_e(simple)
+ generic map(
+ limit_high => 4.8,
+ limit_low => -4.8
+ )
+ port map(
+ input => ll_out,
+ output => servo_out
+ );
+ XCMP22 : entity work.lead_lag_e(simple)
+ generic map(
+ f2 => 2000.0,
+ f1 => 5.0,
+ k => 400.0
+ )
+ port map(
+ input => ll_in,
+ output => ll_out
+ );
+end rudder_servo;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : gear_rv_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/10/10 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+ generic(
+ ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+ -- Note: can be negative, if shaft polarity changes
+
+ port ( terminal rotv1 : rotational_v;
+ terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+ quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
+ quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+-- w2 == w1*ratio;
+ theta == ratio*w1'integ;
+ torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+
+ generic (
+ k : real := 1.0); -- optional gain
+
+ port (
+ terminal input : rotational; -- input terminal
+ terminal output : electrical); -- output terminal
+
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref; -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+ begin -- bhv
+ v_out == k*rot_in;
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- tran = R*sin(rot)
+--
+-- Where pos = output translational position,
+-- R = horn radius,
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+
+ generic (
+ R : real := 1.0); -- horn radius
+
+ port (
+ terminal theta : ROTATIONAL; -- input angular position port
+ terminal pos : TRANSLATIONAL); -- output translational position port
+
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+ begin -- bhv
+ tran == R*sin(rot); -- Convert angle in to translational out
+ tran_frc == -rot_tq/R; -- Convert torque in to force out
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- theta = arcsin(pos/R)
+--
+-- Where pos = input translational position,
+-- R = horn radius,
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+
+ generic (
+ R : real := 1.0); -- Rudder horn radius
+
+ port (
+ terminal pos : translational; -- input translational position port
+ terminal theta : rotational); -- output angular position port
+
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+ begin -- bhv
+ rot == arcsin(tran/R); -- Convert translational to angle
+ rot_tq == -tran_frc*R; -- Convert force to torque
+
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : DC_Motor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+ generic (
+ r_wind : resistance; -- Motor winding resistance [Ohm]
+ kt : real; -- Torque coefficient [N*m/Amp]
+ l : inductance; -- Winding inductance [Henrys]
+ d : real; -- Damping coefficient [N*m/(rad/sec)]
+ j : mmoment_i); -- Moment of inertia [kg*meter**2]
+
+ port (terminal p1, p2 : electrical;
+ terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
+-- T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+ quantity v across i through p1 to p2;
+ quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+ torq == -1.0*kt*i + d*w + j*w'dot;
+ v == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : stop_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+ generic (
+ k_stop : real;
+-- ang_max : angle;
+-- ang_min : angle := 0.0;
+ ang_max : real;
+ ang_min : real := 0.0;
+ damp_stop : real := 0.000000001
+ );
+
+ port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+ quantity velocity : velocity;
+ quantity ang across trq through ang1 to ang2;
+
+begin
+
+ velocity == ang'dot;
+
+ if ang'above(ang_max) use
+ trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+ elsif ang'above(ang_min) use
+ trq == 0.0;
+ else
+ trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
+ end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+ terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+ QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+ QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+ pos_2 == pos_1; -- Pass position
+ frc_2 == -frc_1; -- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+-- Transfer Function:
+--
+-- torq = -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+
+ generic (
+ k : real := 1.0; -- Spring constant
+ theta_0 : real := 0.0);
+
+ port (
+ terminal rot : rotational); -- input rotational angle
+
+end entity rudder;
+
+architecture bhv of rudder is
+
+ QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+ begin -- bhv
+
+ torq == k*(theta - theta_0); -- Convert force to torque
+
+end bhv;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical Resistor Model
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY resistor IS
+
+-- Initialize parameters
+ GENERIC (
+ res : RESISTANCE); -- resistance (no initial value)
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL p1, p2 : ELECTRICAL);
+
+END ENTITY resistor;
+
+-- Ideal Architecture (V = I*R)
+ARCHITECTURE ideal OF resistor IS
+
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH p1 TO p2;
+
+BEGIN
+
+-- Characteristic equations
+ v == i*res;
+
+END ARCHITECTURE ideal;
+
+--
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+
+entity amp_lim is
+ port (terminal ps : electrical; -- positive supply terminal
+ terminal input, output : electrical);
+end entity amp_lim;
+
+
+architecture simple of amp_lim is
+ quantity v_pwr across i_pwr through ps to electrical_ref;
+ quantity vin across iin through input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ quantity v_amplified : voltage ;
+ constant gain : real := 1.0;
+begin
+ v_amplified == gain*vin;
+
+ if v_amplified > v_pwr use
+ vout == v_pwr;
+ else
+ vout == v_amplified;
+ end use;
+
+ -- ignore loading effects
+ i_pwr == 0.0;
+ iin == 0.0;
+
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : v_pulse.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/07/09
+-------------------------------------------------------------------------------
+-- Description: Voltage Pulse Source
+-- Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
+-- time. Uses time2real function.
+-- Pulsewidth no longer includes
+-- rise and fall times.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_pulse is
+
+ generic (
+ initial : voltage := 0.0; -- initial value [Volts]
+ pulse : voltage; -- pulsed value [Volts]
+ ti2p : time := 1ns; -- initial to pulse [Sec]
+ tp2i : time := 1ns; -- pulse to initial [Sec]
+ delay : time := 0ms; -- delay time [Sec]
+ width : time; -- duration of pulse [Sec]
+ period : time; -- period [Sec]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port (
+ terminal pos, neg : electrical);
+
+end entity v_pulse;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_pulse is
+
+-- Declare Through and Across Branch Quantities
+ quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+-- Signal used in CreateEvent process below
+ signal pulse_signal : voltage := initial;
+
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+-- Note: these lines gave an error during simulation. Had to use a
+-- function call instead.
+-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
+-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
+
+-- Function to convert numbers of type TIME to type REAL
+ function time2real(tt : time) return real is
+ begin
+ return time'pos(tt) * 1.0e-15;
+ end time2real;
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+ constant ri2p : real := time2real(ti2p);
+ constant rp2i : real := time2real(tp2i);
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+ v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
+ else
+ v == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+-- purpose: Create events to define pulse shape
+-- type : combinational
+-- inputs :
+-- outputs: pulse_signal
+CreateEvent : process
+begin
+ wait for delay;
+ loop
+ pulse_signal <= pulse;
+ wait for (width + ti2p);
+ pulse_signal <= initial;
+ wait for (period - width - ti2p);
+ end loop;
+end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.math_real.all;
+package pwl_full_functions is
+
+ function next_increment(x : in real; xdata : in real_vector )
+ return real;
+ function interpolate (x,y2,y1,x2,x1 : in real)
+ return real;
+ function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector )
+ return real;
+
+end package pwl_full_functions;
+
+package body pwl_full_functions is
+
+ function next_increment(x : in real; xdata : in real_vector)
+ return real is
+ variable i : integer;
+ begin
+ i := 0;
+ while i <= xdata'right loop
+ if x >= xdata(i) - 6.0e-15 then -- The value 6.0e-15 envelopes round-off error
+ -- of real-to-time conversion in calling model
+ i := i + 1;
+ else
+ return xdata(i) - xdata(i - 1);
+ end if;
+ end loop;
+ return 1.0; -- Returns a "large number" relative to expected High-Speed time scale
+ end function next_increment;
+
+ function interpolate (x,y2,y1,x2,x1 : in real)
+ return real is
+ variable m, yvalue : real;
+ begin
+ assert (x1 /= x2)
+ report "interpolate: x1 cannot be equal to x2"
+ severity error;
+ assert (x >= x1) and (x <= x2)
+ report "interpolate: x must be between x1 and x2, inclusively "
+ severity error;
+
+ m := (y2 - y1)/(x2 - x1);
+ yvalue := y1 + m*(x - x1);
+ return yvalue;
+ end function interpolate;
+
+ -- Created a new pwl_dim1_flat function that returns a constant
+ -- value of ydata(0) if x < xdata(0), or ydata(ydata'right) if x > xdata(xdata'right)
+
+ function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector )
+ return real is
+ variable xvalue, yvalue, m : real;
+ variable start, fin, mid: integer;
+ begin
+ if x >= xdata(xdata'right) then
+ yvalue := ydata(ydata'right);
+ return yvalue;
+ end if;
+ if x <= xdata(0) then
+ yvalue := ydata(0);
+ return yvalue;
+ end if;
+ start:=0;
+ fin:=xdata'right;
+-- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive.
+-- so fin==n-1 in C terms (where n is the size of the array).
+ while start <=fin loop
+ mid:=(start+fin)/2;
+ if xdata(mid) < x
+ then start:=mid+1;
+ else fin:=mid-1;
+ end if;
+ end loop;
+
+ if xdata(mid) > x
+ then mid:=mid-1;
+ end if;
+ yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));
+
+ return yvalue;
+ end function pwl_dim1_flat;
+
+end package body pwl_full_functions;
+
+-- Not sure the sync_tdata process is necessary. Requires the tdata set contain
+-- a larger value than the actual simulation time.
+-- Piece-wise linear voltage source model
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+Library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use work.pwl_full_functions.all;
+
+entity v_pwl_full is
+generic (
+ vdata : real_vector; -- v-pulse data
+ tdata : real_vector -- time-data for v-pulse
+ );
+
+port (
+ terminal pos, neg : electrical
+ );
+end entity v_pwl_full;
+
+
+architecture ideal of v_pwl_full is
+
+QUANTITY v across i through pos TO neg;
+signal tick : std_logic := '0'; -- Sync signal for tdata "tracking"
+
+begin
+
+sync_tdata: process is
+variable next_tick_delay : real := 0.0; -- Time increment to the next time-point in tdata
+begin
+ wait until domain = time_domain;
+ loop
+ next_tick_delay := next_increment(NOW,tdata);
+ tick <= (not tick) after (integer(next_tick_delay * 1.0e15) * 1 fs);
+ wait on tick;
+ end loop;
+end process sync_tdata;
+
+break on tick; -- Forces analog solution point at all tdata time-points
+
+v == pwl_dim1_flat(NOW, tdata, vdata);
+
+end architecture ideal;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity tb_CS5_Amp_Lim is
+end tb_CS5_Amp_Lim;
+
+architecture TB_CS5_Amp_Lim of tb_CS5_Amp_Lim is
+ -- Component declarations
+ -- Signal declarations
+ terminal amp_in : electrical;
+ terminal gear_out : rotational;
+ terminal link_in : translational;
+ terminal link_out : translational;
+ terminal mot_in : electrical;
+ terminal mot_out : rotational_v;
+ terminal pos_fb_v : electrical;
+ terminal power : electrical;
+ terminal rudder_in : rotational;
+ terminal src_in : electrical;
+ terminal XSIG010068 : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ rudder_servo1 : entity work.rudder_servo
+ port map(
+ servo_out => amp_in,
+ servo_in => src_in,
+ pos_fb => pos_fb_v
+ );
+ gear3 : entity work.gear_rv_r(ideal)
+ generic map(
+ ratio => 0.01
+ )
+ port map(
+ rotv1 => mot_out,
+ rot2 => gear_out
+ );
+ r2v : entity work.rot2v(bhv)
+ generic map(
+ k => 1.0
+ )
+ port map(
+ output => pos_fb_v,
+ input => gear_out
+ );
+ r2t : entity work.horn_r2t(bhv)
+ port map(
+ theta => gear_out,
+ pos => link_in
+ );
+ t2r : entity work.horn_t2r(bhv)
+ port map(
+ theta => rudder_in,
+ pos => link_out
+ );
+ motor1 : entity work.DC_Motor(basic)
+ generic map(
+ j => 168.0e-9,
+ d => 5.63e-6,
+ l => 2.03e-3,
+ kt => 3.43e-3,
+ r_wind => 2.2
+ )
+ port map(
+ p1 => mot_in,
+ p2 => ELECTRICAL_REF,
+ shaft_rotv => mot_out
+ );
+ stop1 : entity work.stop_r(ideal)
+ generic map(
+ ang_min => -1.05,
+ ang_max => 1.05,
+ k_stop => 1.0e6,
+ damp_stop => 1.0e2
+ )
+ port map(
+ ang1 => gear_out,
+ ang2 => ROTATIONAL_REF
+ );
+ XCMP35 : entity work.tran_linkage(a1)
+ port map(
+ p2 => link_out,
+ p1 => link_in
+ );
+ XCMP36 : entity work.rudder(bhv)
+ generic map(
+ k => 0.2
+ )
+ port map(
+ rot => rudder_in
+ );
+ R2w : entity work.resistor(ideal)
+ generic map(
+ res => 1000.0
+ )
+ port map(
+ p1 => XSIG010068,
+ p2 => ELECTRICAL_REF
+ );
+ XCMP55 : entity work.amp_lim(simple)
+ port map(
+ input => amp_in,
+ output => mot_in,
+ ps => power
+ );
+ v9 : entity work.v_pulse(ideal)
+ generic map(
+ initial => 0.0,
+ pulse => 4.8,
+ ti2p => 300ms,
+ tp2i => 300ms,
+ delay => 100ms,
+ width => 5ms,
+ period => 605ms
+ )
+ port map(
+ pos => src_in,
+ neg => ELECTRICAL_REF
+ );
+ XCMP57 : entity work.v_pwl_full(ideal)
+ generic map(
+ tdata => (0.0,100.0e-3,400.0e-3,900.0e-3,1300.0e-3,1800.0e-3,2300.0e-3,2600.0e-3, 2900.0e-3),
+ vdata => (0.0,0.0,2.4,2.4,4.7,4.7,1.0,1.0,0.0)
+ )
+ port map(
+ pos => XSIG010068,
+ neg => ELECTRICAL_REF
+ );
+ XCMP60 : entity work.v_pwl_full(ideal)
+ generic map(
+ vdata => (4.8,4.8,4.4,4.4,4.0,4.0,3.6,3.6,3.2,3.2),
+ tdata => (0.0,705.0e-3,706.0e-3,1310.0e-3,1320.0e-3,1915.0e-3,1925.0e-3,2520.0e-3,2530.0e-3,3125.0e-3)
+ )
+ port map(
+ pos => power,
+ neg => ELECTRICAL_REF
+ );
+end TB_CS5_Amp_Lim;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
new file mode 100644
index 000000000..60fdc24be
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
@@ -0,0 +1,3668 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+ generic (k1, k2: real := 1.0); -- Gain multipliers
+ port ( terminal in1, in2: electrical;
+ terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+ QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+ QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+ generic (
+ k: REAL := 1.0); -- Gain multiplier
+ port ( terminal input : electrical;
+ terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+ generic (
+ limit_high : real := 4.8; -- upper limit
+ limit_low : real := -4.8); -- lower limit
+ port (
+ terminal input: electrical;
+ terminal output: electrical);
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+ constant slope : real := 1.0e-4;
+begin
+ if vin > limit_high use -- Upper limit exceeded, so limit input signal
+ vout == limit_high + slope*(vin - limit_high);
+ elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
+ vout == limit_low + slope*(vin - limit_low);
+ else -- No limit exceeded, so pass input signal as is
+ vout == vin;
+ end use;
+ break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+-- Transfer Function:
+--
+-- (s + w1)
+-- H(s) = k * ----------
+-- (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lead_lag_e is
+ generic (
+ k: real := 1.0; -- Gain multiplier
+ f1: real := 10.0; -- First break frequency (zero)
+ f2: real := 100.0); -- Second break frequency (pole)
+ port ( terminal input: electrical;
+ terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ quantity vin_temp : real;
+ constant w1 : real := f1*math_2_pi;
+ constant w2 : real := f2*math_2_pi;
+ constant num : real_vector := (w1, 1.0);
+ constant den : real_vector := (w2, 1.0);
+begin
+ vin_temp == vin;
+ vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo is
+ port(
+ terminal servo_in : electrical;
+ terminal pos_fb : electrical;
+ terminal servo_out : electrical
+ );
+end rudder_servo;
+
+architecture rudder_servo of rudder_servo is
+ -- Component declarations
+ -- Signal declarations
+ terminal error : electrical;
+ terminal ll_in : electrical;
+ terminal ll_out : electrical;
+ terminal summer_fb : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ summer : entity work.sum2_e(simple)
+ port map(
+ in1 => servo_in,
+ in2 => summer_fb,
+ output => error
+ );
+ forward_gain : entity work.gain_e(simple)
+ generic map(
+ k => 100.0
+ )
+ port map(
+ input => error,
+ output => ll_in
+ );
+ fb_gain : entity work.gain_e(simple)
+ generic map(
+ k => -4.57
+ )
+ port map(
+ input => pos_fb,
+ output => summer_fb
+ );
+ servo_limiter : entity work.limiter_2_e(simple)
+ generic map(
+ limit_high => 4.8,
+ limit_low => -4.8
+ )
+ port map(
+ input => ll_out,
+ output => servo_out
+ );
+ lead_lag : entity work.lead_lag_e(simple)
+ generic map(
+ k => 400.0,
+ f1 => 5.0,
+ f2 => 2000.0
+ )
+ port map(
+ input => ll_in,
+ output => ll_out
+ );
+end rudder_servo;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : gear_rv_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/10/10 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+ generic(
+ ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+ -- Note: can be negative, if shaft polarity changes
+
+ port ( terminal rotv1 : rotational_v;
+ terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+ quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
+ quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+-- w2 == w1*ratio;
+ theta == ratio*w1'integ;
+ torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+
+ generic (
+ k : real := 1.0); -- optional gain
+
+ port (
+ terminal input : rotational; -- input terminal
+ terminal output : electrical); -- output terminal
+
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref; -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+ begin -- bhv
+ v_out == k*rot_in;
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- tran = R*sin(rot)
+--
+-- Where pos = output translational position,
+-- R = horn radius,
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+
+ generic (
+ R : real := 1.0); -- horn radius
+
+ port (
+ terminal theta : ROTATIONAL; -- input angular position port
+ terminal pos : TRANSLATIONAL); -- output translational position port
+
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+ begin -- bhv
+ tran == R*sin(rot); -- Convert angle in to translational out
+ tran_frc == -rot_tq/R; -- Convert torque in to force out
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- theta = arcsin(pos/R)
+--
+-- Where pos = input translational position,
+-- R = horn radius,
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+
+ generic (
+ R : real := 1.0); -- Rudder horn radius
+
+ port (
+ terminal pos : translational; -- input translational position port
+ terminal theta : rotational); -- output angular position port
+
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+ begin -- bhv
+ rot == arcsin(tran/R); -- Convert translational to angle
+ rot_tq == -tran_frc*R; -- Convert force to torque
+
+end bhv;
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+ terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+ QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+ QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+ pos_2 == pos_1; -- Pass position
+ frc_2 == -frc_1; -- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+-- Transfer Function:
+--
+-- torq = -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+
+ generic (
+ k : real := 1.0; -- Spring constant
+ theta_0 : real := 0.0);
+
+ port (
+ terminal rot : rotational); -- input rotational angle
+
+end entity rudder;
+
+architecture bhv of rudder is
+
+ QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+ begin -- bhv
+
+ torq == k*(theta - theta_0); -- Convert force to torque
+
+end bhv;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Constant Voltage Source (Includes Frequency Domain settings)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY v_constant IS
+
+-- Initialize parameters
+ GENERIC (
+ level : VOLTAGE; -- Constant voltage value (V)
+ ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
+ ac_phase : real := 0.0); -- AC phase (degrees)
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL pos, neg : ELECTRICAL);
+
+END ENTITY v_constant;
+
+-- Ideal Architecture (I = constant)
+ARCHITECTURE ideal OF v_constant IS
+
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH pos TO neg;
+-- Declare quantity in frequency domain for AC analysis
+ QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+
+ IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
+ v == level;
+ ELSE
+ v == ac_spec; -- used for Frequency (AC) analysis
+ END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical sinusoidal voltage source (stick.vhd)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+
+ENTITY stick IS
+
+-- Initialize parameters
+ GENERIC (
+ freq : real; -- frequency, [Hertz]
+ amplitude : real; -- amplitude, [Volt]
+ phase : real := 0.0; -- initial phase, [Degree]
+ offset : real := 0.0; -- DC value, [Volt]
+ df : real := 0.0; -- damping factor, [1/second]
+ ac_mag : real := 1.0; -- AC magnitude, [Volt]
+ ac_phase : real := 0.0); -- AC phase, [Degree]
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL v_out : ELECTRICAL);
+
+END ENTITY stick;
+
+-- Ideal Architecture
+ARCHITECTURE ideal OF stick IS
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
+-- Declare Quantity for Phase in radians (calculated below)
+ QUANTITY phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+ QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+-- Convert phase to radians
+ phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+ IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
+ v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+ ELSE
+ v == ac_spec; -- used for Frequency (AC) analysis
+ END USE;
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity RF_xmtr_rcvr is
+generic (td : time := 0ns);
+port
+(
+ tdm_in : in std_logic ;
+ tdm_out : out std_logic
+);
+
+end RF_xmtr_rcvr;
+
+architecture behavioral of RF_xmtr_rcvr is
+begin
+
+tdm_out <= tdm_in after td;
+
+end;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Simple Digital-Controlled Two-position Switch Model
+-- Switch position 1 ('0') or switch position 2 ('1')
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY switch_dig_2in is
+ GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
+ r_closed : RESISTANCE := 0.001; -- Closed switch resistance
+ trans_time : real := 0.00001); -- Transition time to each position
+
+ PORT (sw_state : in std_logic; -- Digital control input
+ TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
+
+END ENTITY switch_dig_2in;
+
+
+ARCHITECTURE ideal OF switch_dig_2in IS
+
+-- CONSTANT log_r_open : real := log10(r_open);
+-- CONSTANT log_r_closed : real := log10(r_closed);
+-- SIGNAL r_sig1 : RESISTANCE := log_r_closed; -- Variable to accept switch resistance
+-- SIGNAL r_sig2 : RESISTANCE := log_r_open; -- Variable to accept switch resistance
+ SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
+ SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
+ QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
+ QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
+ QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
+ QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
+
+BEGIN
+
+ PROCESS (sw_state) -- Sensitivity to digital control input
+ BEGIN
+ IF (sw_state'event AND sw_state = '0') THEN -- Close sig1, open sig2
+ r_sig1 <= r_closed;
+ r_sig2 <= r_open;
+ ELSIF (sw_state'event AND sw_state = '1') THEN -- Open sig1, close sig2
+ r_sig1 <= r_open;
+ r_sig2 <= r_closed;
+ END IF;
+ END PROCESS;
+
+ r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
+ r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
+ v1 == r1*i1; -- Apply Ohm's law to in1
+ v2 == r2*i2; -- Apply Ohm's law to in2
+
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Digital clock with 50% duty cycle
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock IS
+ GENERIC (
+ period : time); -- Clock period
+
+ PORT (
+ clk_out : OUT std_logic);
+
+END ENTITY clock;
+
+ARCHITECTURE ideal OF clock IS
+
+BEGIN
+
+-- clock process
+ process
+ begin
+ clk_out <= '0';
+ wait for period/2;
+ clk_out <= '1';
+ wait for period/2;
+ end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- This digital clock allows user to specify the duty cycle using
+-- the parameters "on_time" and "off_time"
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY clock_duty IS
+
+ GENERIC (
+ on_time : time := 20 us;
+ off_time : time := 19.98 ms
+ );
+
+ PORT (
+ clock_out : OUT std_logic := '0');
+
+END ENTITY clock_duty;
+
+ARCHITECTURE ideal OF clock_duty IS
+
+BEGIN
+
+-- clock process
+ process
+ begin
+ clock_out <= '1';
+ wait for on_time;
+ clock_out <= '0';
+ wait for off_time;
+ end process;
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rc_clk is
+ port(
+ clk_100k : out std_logic;
+ clk_6K : out std_logic;
+ clk_50 : out std_logic
+ );
+end rc_clk;
+
+architecture rc_clk of rc_clk is
+ -- Component declarations
+ -- Signal declarations
+begin
+ -- Signal assignments
+ -- Component instances
+ XCMP1 : entity work.clock(ideal)
+ generic map(
+ period => 10us
+ )
+ port map(
+ CLK_OUT => clk_100k
+ );
+ XCMP2 : entity work.clock(ideal)
+ generic map(
+ period => 150us
+ )
+ port map(
+ CLK_OUT => clk_6K
+ );
+ clk_50Hz : entity work.clock_duty(ideal)
+ generic map(
+ on_time => 20 us,
+ off_time => 19.98 ms
+ )
+ port map(
+ CLOCK_OUT => clk_50
+ );
+end rc_clk;
+--
+
+-- This model counts the number of input clock transitions and outputs
+-- a '1' when this number equals the value of the user-defined constant 'count'
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity bit_cnt is
+ generic (
+ count : integer -- User-defined value to count up to
+ );
+port
+(
+ bit_in : in std_logic ;
+ clk : in std_logic ;
+ dly_out : out std_logic
+);
+end bit_cnt;
+
+architecture behavioral of bit_cnt is
+begin
+ serial_clock : process is
+ begin
+ wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
+ FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
+ wait until clk'event AND (clk = '1' OR clk = 'H');
+ END LOOP ;
+ dly_out <= '1'; -- After count is reached, set output high
+ wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
+ dly_out <= '0'; -- Reset output to '0' on next clock input
+ end process serial_clock;
+end;
+--
+
+--//////////////////////////////////////////////////////////////////
+-- NOTE: This is an intermediate file for HDL inspection only.
+-- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach1.sdg.
+-- Generated by sde2hdl version 16.1.0.2
+--//////////////////////////////////////////////////////////////////
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+
+ENTITY state_mach1 IS
+ PORT (
+ a2d_eoc : IN std_logic;
+ clk_50 : IN std_logic;
+ clk_100k : IN std_logic;
+ clk_6k : IN std_logic;
+ ser_done : IN std_logic;
+ ch_sel : OUT std_logic;
+ frm_gen : OUT std_logic;
+ a2d_oe : OUT std_logic;
+ a2d_start : OUT std_logic;
+ p2s_oe : OUT std_logic;
+ p2s_load : OUT std_logic;
+ parity_oe : OUT std_logic;
+ ser_cnt : OUT std_logic;
+ p2s_clr : OUT std_logic);
+
+END state_mach1;
+
+ARCHITECTURE state_diagram OF state_mach1 IS
+
+ ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+ TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
+ , load, ad_ch2, delay);
+ SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
+
+ SIGNAL FB_frm_gen : std_logic;
+ SIGNAL FB_p2s_load : std_logic;
+ SIGNAL FB_ch_sel : std_logic;
+
+BEGIN
+ frm_gen <= FB_frm_gen ;
+ p2s_load <= FB_p2s_load ;
+ ch_sel <= FB_ch_sel ;
+
+sm1:
+ PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel)
+ BEGIN
+
+ CASE CS_state_mach1_sm1 IS
+ WHEN V_begin =>
+ FB_frm_gen <= ('1');
+ a2d_start <= ('0');
+ a2d_oe <= ('0');
+ FB_p2s_load <= ('0');
+ p2s_clr <= ('0');
+ p2s_oe <= ('0');
+ FB_ch_sel <= ('0');
+ parity_oe <= ('0');
+ ser_cnt <= ('0');
+
+ IF ((FB_frm_gen = '1')) THEN
+ NS_state_mach1_sm1 <= frm_rd;
+ ELSE
+ NS_state_mach1_sm1 <= V_begin;
+ END IF;
+
+ WHEN frm_rd =>
+ FB_p2s_load <= ('1');
+
+ IF ((FB_p2s_load = '1')) THEN
+ NS_state_mach1_sm1 <= ser_oe;
+ ELSE
+ NS_state_mach1_sm1 <= frm_rd;
+ END IF;
+
+ WHEN ser_oe =>
+ p2s_oe <= ('1');
+ FB_frm_gen <= ('0');
+ FB_p2s_load <= ('0');
+ ser_cnt <= ('1');
+
+ IF ((ser_done = '1')) THEN
+ NS_state_mach1_sm1 <= ch1;
+ ELSE
+ NS_state_mach1_sm1 <= ser_oe;
+ END IF;
+
+ WHEN ch1 =>
+ p2s_oe <= ('0');
+ FB_ch_sel <= ('0');
+ a2d_start <= ('1');
+ ser_cnt <= ('0');
+
+ IF ((a2d_eoc = '1')) THEN
+ NS_state_mach1_sm1 <= data_en;
+ ELSE
+ NS_state_mach1_sm1 <= ch1;
+ END IF;
+
+ WHEN data_en =>
+ a2d_start <= ('0');
+ a2d_oe <= ('1');
+ parity_oe <= ('1');
+ NS_state_mach1_sm1 <= load;
+
+ WHEN tdm_oe =>
+ a2d_oe <= ('0');
+ parity_oe <= ('0');
+ p2s_oe <= ('1');
+ FB_p2s_load <= ('0');
+ ser_cnt <= ('1');
+
+ IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
+ NS_state_mach1_sm1 <= ch2;
+ ELSE
+ NS_state_mach1_sm1 <= tdm_oe;
+ END IF;
+
+ WHEN ch2 =>
+ p2s_oe <= ('0');
+ ser_cnt <= ('0');
+ FB_ch_sel <= ('1');
+ NS_state_mach1_sm1 <= delay;
+
+ WHEN load =>
+ FB_p2s_load <= ('1');
+ NS_state_mach1_sm1 <= tdm_oe;
+
+ WHEN ad_ch2 =>
+ a2d_start <= ('1');
+
+ IF ((a2d_eoc = '1')) THEN
+ NS_state_mach1_sm1 <= data_en;
+ ELSE
+ NS_state_mach1_sm1 <= ad_ch2;
+ END IF;
+
+ WHEN delay =>
+ NS_state_mach1_sm1 <= ad_ch2;
+
+ END CASE;
+
+ END PROCESS;
+
+sm1_CTL:
+ PROCESS (clk_100k, clk_50)
+ BEGIN
+
+ IF (clk_100k'event AND clk_100k='1') THEN
+ IF (clk_50= '1' ) THEN
+ CS_state_mach1_sm1 <= V_begin;
+ ELSE
+ CS_state_mach1_sm1 <= NS_state_mach1_sm1;
+ END IF;
+ END IF;
+
+ END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt is
+ port(
+ a2d_eoc : in std_logic;
+ clk_50 : in std_logic;
+ clk_100k : in std_logic;
+ clk_6k : in std_logic;
+ p2s_load : out std_logic;
+ p2s_oe : out std_logic;
+ parity_oe : out std_logic;
+ a2d_start : out std_logic;
+ a2d_oe : out std_logic;
+ frm_gen : out std_logic;
+ ch_sel : out std_logic;
+ p2s_clr : out std_logic
+ );
+end sm_cnt;
+
+architecture sm_cnt of sm_cnt is
+ -- Component declarations
+ -- Signal declarations
+ signal ser_done : std_logic;
+ signal serial_cnt : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ bit_cnt1 : entity work.bit_cnt(behavioral)
+ generic map(
+ count => 15
+ )
+ port map(
+ bit_in => serial_cnt,
+ clk => clk_6k,
+ dly_out => ser_done
+ );
+ state_mach16 : entity work.state_mach1
+ port map(
+ ser_cnt => serial_cnt,
+ ch_sel => ch_sel,
+ frm_gen => frm_gen,
+ a2d_oe => a2d_oe,
+ a2d_start => a2d_start,
+ parity_oe => parity_oe,
+ p2s_oe => p2s_oe,
+ p2s_load => p2s_load,
+ p2s_clr => p2s_clr,
+ clk_6k => clk_6k,
+ clk_100k => clk_100k,
+ clk_50 => clk_50,
+ a2d_eoc => a2d_eoc,
+ ser_done => ser_done
+ );
+end sm_cnt;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+-- Analog to Digital Converter (Successive Aproximation Register) model with sar architecture (a2d_nbit.vhd)
+--DESCRIPTION:
+--
+--This is a VHDL-AMS model of a simple analog to digital converter. The model
+--describes the general behavior of A/D converters for system level design and
+--verification.
+--The format of the digital output is binary coding.
+--
+--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
+--
+
+-- Use IEEE natures and packages
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity a2d_nbit is
+ generic (
+ Vmax: REAL := 5.0 ; -- ADC's maximum range
+ Nbits: INTEGER := 10 ; -- number bits in ADC's output
+ delay: TIME := 10 us -- ADC's conversion time
+ );
+
+port (
+ signal start: in std_logic ; -- Start signal
+ signal clk: in std_logic ; -- Strobe clock
+ signal oe: in std_logic ; -- Output enable
+ terminal ain: ELECTRICAL ; -- ADC's analog input terminal
+ signal eoc: out std_logic := '0' ; -- End Of Conversion pin
+ signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
+end entity a2d_nbit;
+
+architecture sar of a2d_nbit is
+
+ type states is (input, convert, output) ; -- Three states of A2D Conversion
+ constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
+ quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
+
+begin
+
+ sa_adc: process
+
+ variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
+ variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
+ variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
+ variable status: states := input ; -- Begin with "input" CASE
+ variable bit_cnt: integer := Nbits -1 ;
+
+ begin
+ CASE status is
+ when input => -- Read input voltages when start goes high
+ wait on start until start = '1' or start = 'H' ;
+ thresh := Vmax ;
+ Vtmp := Vin ;
+ eoc <= '0' ;
+ status := convert ; -- Go to convert state
+ when convert => -- Begin successive approximation conversion
+ thresh := thresh / 2.0 ; -- Get value of MSB
+ wait on clk until clk = '1' OR clk = 'H';
+ if Vtmp > thresh then
+ dtmp(bit_cnt) := '1' ;
+ Vtmp := Vtmp - thresh ;
+ else
+ dtmp(bit_cnt) := '0' ;
+ end if ;
+ bit_cnt := bit_cnt - 1 ;
+ if (bit_cnt + 1) < 1 then
+ status := output ; -- Go to output state
+ end if;
+ when output => -- Wait for output enable, then put data on output pins
+ eoc <= '1' after delay ;
+ wait on oe until oe = '1' OR oe = 'H' ;
+ FOR i in bit_range DOWNTO 0 LOOP
+ dout(i) <= dtmp(i) ;
+ END LOOP ;
+ wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
+ FOR i in bit_range DOWNTO 0 LOOP
+ dout <= "ZZZZZZZZZZ" ;
+ END LOOP ;
+ bit_cnt := bit_range ;
+ status := input ; -- Set up for next conversion
+ END CASE ;
+ end process sa_adc ;
+
+ Iin == 0.0 ; -- Ideal input draws no current
+
+end architecture sar ;
+--
+
+-- Parallel input/serial output shift register
+-- With 4 trailing zeros
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity shift_reg is
+generic ( td : time := 0 ns);
+
+port
+(
+ bus_in : in std_logic_vector ; -- Input bus
+ clk : in std_logic ; -- Shift clock
+ oe : in std_logic ; -- Output enable
+ ser_out : out std_logic := '0'; -- Output port
+ load : in std_logic ; -- Parallel input load
+ clr : in std_logic -- Clear register
+);
+
+end entity shift_reg;
+
+architecture behavioral of shift_reg is
+begin
+
+control_proc : process
+ VARIABLE bit_val : std_logic_vector(11 downto 0); -- Default 12-bit input
+ begin
+
+ IF (clr = '1' OR clr = 'H') then
+ bit_val := "000000000000"; -- Set all input bits to zero
+ ELSE
+ wait until load'event AND (load = '1' OR load = 'H');
+ FOR i IN bus_in'high DOWNTO bus_in'low LOOP
+ bit_val(i) := bus_in(i) ; -- Transfer input data to variable
+ END LOOP ;
+ END IF;
+
+ wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
+ FOR i IN bit_val'high DOWNTO bit_val'low LOOP
+ wait until clk'event AND (clk = '1' OR clk = 'H');
+ ser_out <= bit_val(i) ;
+ END LOOP ;
+
+ FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros
+ wait until clk'event AND (clk = '1' OR clk = 'H');
+ ser_out <= '0';
+ END LOOP;
+
+END process;
+
+end architecture behavioral;
+--
+
+-- This model generates a 12-bit data frame synchronization code
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_gen is
+port
+(
+ oe : in std_logic := '0';
+ sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
+
+end entity frame_gen;
+
+architecture simple of frame_gen is
+begin
+ enbl: PROCESS
+ BEGIN
+ WAIT ON OE;
+ IF OE = '1' THEN
+ sync_out <= "010101010101"; -- Sync code
+ ELSE
+ sync_out <= "ZZZZZZZZZZZZ";
+ END IF;
+ END PROCESS;
+end architecture simple;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input XOR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY xor2 IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ in1, in2 : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY xor2;
+
+ARCHITECTURE ideal OF xor2 IS
+BEGIN
+ output <= in1 XOR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- level_set_tri.vhd
+-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
+-- If OE = '0' set output to high impedance
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set_tri IS
+
+ GENERIC (
+ logic_val : std_logic := 'Z');
+
+ PORT (
+ OE : IN std_logic;
+ level : OUT std_logic := 'Z');
+
+END ENTITY level_set_tri;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set_tri IS
+BEGIN
+ oe_ctl: PROCESS
+ BEGIN
+ WAIT ON OE;
+ IF OE = '1' THEN
+ level <= logic_val;
+ ELSE
+ level <= 'Z';
+ END IF;
+ END PROCESS;
+
+END ARCHITECTURE ideal;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Simple Tri-state Buffer with delay time
+-- If OE = 1, output = input after delay
+-- If OE /= 1, output = Z after delay
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY buffer_tri IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ input : IN std_logic;
+ OE : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY buffer_tri;
+
+ARCHITECTURE ideal OF buffer_tri IS
+BEGIN
+ oe_ctl: PROCESS
+ BEGIN
+ WAIT ON OE, input;
+ IF OE = '1' THEN
+ output <= input AFTER delay;
+ ELSE
+ output <= 'Z' AFTER delay;
+ END IF;
+ END PROCESS;
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- ideal one bit D/A converter
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY d2a_bit IS
+ GENERIC (vlow : real :=0.0; -- output high voltage
+ vhigh : real :=5.0); -- output low voltage
+ PORT (D : IN std_logic; -- digital (std_logic) intout
+ TERMINAL A : electrical); -- analog (electrical) output
+END ENTITY d2a_bit;
+
+ARCHITECTURE ideal OF d2a_bit IS
+ QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
+ SIGNAL vin : real := 0.0;
+
+ BEGIN
+ vin <= vhigh WHEN D = '1' ELSE vlow;
+ -- Use 'RAMP for discontinuous signal
+ vout == vin'RAMP(1.0e-9);
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_gen is
+ port(
+ parity : in std_logic_vector(1 to 10);
+ oe : in std_logic;
+ parity_out : out std_logic_vector(0 to 11)
+ );
+end parity_gen;
+
+architecture parity_gen of parity_gen is
+ -- Component declarations
+ -- Signal declarations
+ terminal par_bit_gen_a : electrical;
+ signal XSIG010002 : std_logic;
+ signal XSIG010003 : std_logic;
+ signal XSIG010004 : std_logic;
+ signal XSIG010005 : std_logic;
+ signal XSIG010006 : std_logic;
+ signal XSIG010007 : std_logic;
+ signal XSIG010008 : std_logic;
+ signal XSIG010009 : std_logic;
+ signal XSIG010098 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ XCMP1 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(1),
+ in2 => parity(2),
+ output => XSIG010002
+ );
+ XCMP2 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(3),
+ in2 => parity(4),
+ output => XSIG010003
+ );
+ XCMP3 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(5),
+ in2 => parity(6),
+ output => XSIG010004
+ );
+ XCMP4 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(7),
+ in2 => parity(8),
+ output => XSIG010005
+ );
+ XCMP5 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(9),
+ in2 => parity(10),
+ output => XSIG010008
+ );
+ XCMP6 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010002,
+ in2 => XSIG010003,
+ output => XSIG010006
+ );
+ XCMP7 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010004,
+ in2 => XSIG010005,
+ output => XSIG010007
+ );
+ XCMP8 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010006,
+ in2 => XSIG010007,
+ output => XSIG010009
+ );
+ XCMP9 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010009,
+ in2 => XSIG010008,
+ output => XSIG010098
+ );
+ XCMP18 : entity work.level_set_tri(ideal)
+ generic map(
+ logic_val => '1'
+ )
+ port map(
+ level => parity_out(11),
+ oe => oe
+ );
+ XCMP19 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(1),
+ output => parity_out(1),
+ oe => oe
+ );
+ XCMP20 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(2),
+ output => parity_out(2),
+ oe => oe
+ );
+ XCMP21 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(3),
+ output => parity_out(3),
+ oe => oe
+ );
+ XCMP22 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(4),
+ output => parity_out(4),
+ oe => oe
+ );
+ XCMP23 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(5),
+ output => parity_out(5),
+ oe => oe
+ );
+ XCMP24 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(6),
+ output => parity_out(6),
+ oe => oe
+ );
+ XCMP25 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(7),
+ output => parity_out(7),
+ oe => oe
+ );
+ XCMP26 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(8),
+ output => parity_out(8),
+ oe => oe
+ );
+ XCMP27 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(9),
+ output => parity_out(9),
+ oe => oe
+ );
+ XCMP28 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(10),
+ output => parity_out(10),
+ oe => oe
+ );
+ XCMP29 : entity work.buffer_tri(ideal)
+ port map(
+ input => XSIG010098,
+ output => parity_out(0),
+ oe => oe
+ );
+ XCMP30 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010098,
+ A => par_bit_gen_a
+ );
+end parity_gen;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tdm_encoder is
+ port(
+ clk : in std_logic;
+ p2s_oe : in std_logic;
+ p2s_load : in std_logic;
+ frm_gen : in std_logic;
+ parity_oe : in std_logic;
+ tdm_out : out std_logic;
+ p2s_clr : in std_logic;
+ a2d_data : in std_logic_vector(1 to 10)
+ );
+end tdm_encoder;
+
+architecture tdm_encoder of tdm_encoder is
+ -- Component declarations
+ -- Signal declarations
+ signal sync_par : std_logic_vector(0 to 11);
+begin
+ -- Signal assignments
+ -- Component instances
+ p2s1 : entity work.shift_reg(behavioral)
+ port map(
+ bus_in => sync_par,
+ clk => clk,
+ oe => p2s_oe,
+ ser_out => tdm_out,
+ load => p2s_load,
+ clr => p2s_clr
+ );
+ sync_gen1 : entity work.frame_gen(simple)
+ port map(
+ oe => frm_gen,
+ sync_out => sync_par
+ );
+ par_gen1 : entity work.parity_gen
+ port map(
+ parity => a2d_data,
+ parity_out => sync_par,
+ oe => parity_oe
+ );
+end tdm_encoder;
+--
+
+-- Manchester Encoder
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY menc_rsc IS
+
+ port ( dig_in : in STD_LOGIC; -- digital input
+ clk : in STD_LOGIC; -- TX internal clock
+ reset: in STD_LOGIC; -- not reset
+-- bit_out : inout real); -- real output
+ bit_out : out std_logic); -- real output
+
+END ENTITY menc_rsc;
+
+ARCHITECTURE bhv OF menc_rsc IS
+
+-- signal bhigh:real:= 1.0; -- bit encoding
+-- signal blow:real:= -1.0; -- bit encoding
+-- signal bnormal:real:=0.0; -- bit encoding
+ signal bit1:STD_LOGIC;
+ signal bhigh:std_logic:= '1'; -- bit encoding
+ signal blow:std_logic:= '0'; -- bit encoding
+
+begin
+
+-- proc1: process (dig_in, clk, bit1,bhigh,blow,bnormal)
+ proc1: process (dig_in, clk, bit1,bhigh,blow)
+ begin
+
+ if (reset = '1') then
+ bit1 <= '0';
+ else
+ bit1 <= dig_in XOR clk; -- manchester encoding
+ end if;
+
+ if (bit1 = '1') then
+ bit_out <= bhigh;
+ else
+ bit_out <= blow;
+-- elsif bit1 = '0' then
+-- bit_out <= blow;
+-- else
+-- bit_out <= bnormal;
+ end if;
+
+ end process;
+
+end architecture bhv;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Digitize_Encode_Man is
+ port(
+ tdm_out : out std_logic;
+ terminal ch1_in : electrical;
+ terminal ch2_in : electrical
+ );
+end Digitize_Encode_Man;
+
+architecture Digitize_Encode_Man of Digitize_Encode_Man is
+ -- Component declarations
+ -- Signal declarations
+ terminal a2d_ana_in : electrical;
+ signal ch_bus : std_logic_vector(1 to 10);
+ signal clk_6K : std_logic;
+ signal dig_in : std_logic;
+ signal frm_gen_ctl : std_logic;
+ signal p2s_clr : std_logic;
+ signal p2s_load : std_logic;
+ signal p2s_oe : std_logic;
+ signal par_oe : std_logic;
+ signal reset : std_logic;
+ signal reset_m : std_logic;
+ signal start_a2d1 : std_logic;
+ signal sw_ctl : std_logic;
+ signal XSIG010091 : std_logic;
+ signal XSIG010190 : std_logic;
+ signal XSIG010196 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ A_SWITCH1 : entity work.switch_dig_2in(ideal)
+ port map(
+ p_in1 => ch1_in,
+ p_out => a2d_ana_in,
+ sw_state => sw_ctl,
+ p_in2 => ch2_in
+ );
+ rc_clk2 : entity work.rc_clk
+ port map(
+ clk_50 => reset,
+ clk_6K => clk_6K,
+ clk_100k => XSIG010190
+ );
+ sm_xmtr1 : entity work.sm_cnt
+ port map(
+ clk_100k => XSIG010190,
+ a2d_start => start_a2d1,
+ a2d_eoc => XSIG010091,
+ p2s_oe => p2s_oe,
+ p2s_load => p2s_load,
+ ch_sel => sw_ctl,
+ frm_gen => frm_gen_ctl,
+ parity_oe => par_oe,
+ a2d_oe => XSIG010196,
+ clk_50 => reset,
+ clk_6k => clk_6K,
+ p2s_clr => p2s_clr
+ );
+ a2d1 : entity work.a2d_nbit(sar)
+ generic map(
+ Vmax => 4.8
+ )
+ port map(
+ dout => ch_bus,
+ ain => a2d_ana_in,
+ clk => XSIG010190,
+ start => start_a2d1,
+ eoc => XSIG010091,
+ oe => XSIG010196
+ );
+ tdm_enc1 : entity work.tdm_encoder
+ port map(
+ clk => clk_6K,
+ p2s_oe => p2s_oe,
+ tdm_out => dig_in,
+ p2s_load => p2s_load,
+ a2d_data => ch_bus,
+ frm_gen => frm_gen_ctl,
+ parity_oe => par_oe,
+ p2s_clr => p2s_clr
+ );
+ menc_rsc3 : entity work.menc_rsc(bhv)
+ port map(
+ dig_in => dig_in,
+ clk => clk_6K,
+ reset => reset_m,
+ bit_out => tdm_out
+ );
+ XCMP90 : entity work.clock_duty(ideal)
+ generic map(
+ off_time => 19.98 sec
+ )
+ port map(
+ CLOCK_OUT => reset_m
+ );
+end Digitize_Encode_Man;
+--
+
+-------------------------------------------------------------------------------
+-- Second Order Lowpass filter
+--
+-- Transfer Function:
+--
+-- w1*w2
+-- H(s) = k * ----------------
+-- (s + w1)(s + w2)
+--
+-- DC Gain = k
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lpf_2_e is
+ generic (
+ k: real := 1.0; -- Gain multiplier
+ f1: real := 10.0; -- First break frequency (pole)
+ f2: real := 100.0); -- Second break frequency (pole)
+ port ( terminal input: electrical;
+ terminal output: electrical);
+end entity lpf_2_e;
+
+architecture simple of lpf_2_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ quantity vin_temp : real;
+ constant w1 : real := f1*math_2_pi;
+ constant w2 : real := f2*math_2_pi;
+-- constant num : real := k;
+ constant num : real_vector := (0 => w1*w2*k); -- 0=> is needed to give
+ -- index when only a single
+ -- element is used.
+ constant den : real_vector := (w1*w2, w1+w2, 1.0);
+begin
+ vin_temp == vin; -- intermediate variable (vin) req'd for now
+ vout == vin_temp'ltf(num, den);
+end architecture simple;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input AND gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY and2 IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ in1, in2 : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY and2;
+
+ARCHITECTURE ideal OF and2 IS
+BEGIN
+ output <= in1 AND in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- D Flip Flop with reset (negative edge triggered)
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY d_latch_n_edge_rst IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ data, clk : IN std_logic;
+ q : OUT std_logic := '0';
+ qn : OUT std_logic := '1';
+ rst : IN std_logic := '0'); -- reset
+
+END ENTITY d_latch_n_edge_rst ;
+
+ARCHITECTURE behav OF d_latch_n_edge_rst IS
+BEGIN
+
+ data_in : PROCESS(clk, rst) IS
+
+ BEGIN
+ IF clk = '0' AND clk'event AND rst /= '1' THEN
+ q <= data AFTER delay;
+ qn <= NOT data AFTER delay;
+ ELSIF rst = '1' THEN
+ q <= '0';
+ qn <= '1';
+ END IF;
+
+ END PROCESS data_in; -- End of process data_in
+
+END ARCHITECTURE behav;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity counter_12 is
+ port(
+ cnt : out std_logic_vector(0 to 11);
+ reset : in std_logic;
+ enable : in std_logic;
+ clk : in std_logic
+ );
+end counter_12;
+
+architecture counter_12 of counter_12 is
+ -- Component declarations
+ -- Signal declarations
+ signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
+ signal XSIG010078 : std_logic;
+ signal XSIG010081 : std_logic;
+ signal XSIG010083 : std_logic;
+ signal XSIG010085 : std_logic;
+ signal XSIG010087 : std_logic;
+ signal XSIG010101 : std_logic;
+ signal XSIG010102 : std_logic;
+ signal XSIG010103 : std_logic;
+ signal XSIG010104 : std_logic;
+ signal XSIG010115 : std_logic;
+ signal XSIG010116 : std_logic;
+ signal XSIG010117 : std_logic;
+ signal XSIG010132 : std_logic;
+begin
+ -- Signal assignments
+ cnt(0) <= cdb2vhdl_tmp_1(0);
+ cnt(1) <= cdb2vhdl_tmp_1(1);
+ cnt(2) <= cdb2vhdl_tmp_1(2);
+ cnt(3) <= cdb2vhdl_tmp_1(3);
+ cnt(4) <= cdb2vhdl_tmp_1(4);
+ cnt(5) <= cdb2vhdl_tmp_1(5);
+ cnt(6) <= cdb2vhdl_tmp_1(6);
+ cnt(7) <= cdb2vhdl_tmp_1(7);
+ cnt(8) <= cdb2vhdl_tmp_1(8);
+ cnt(9) <= cdb2vhdl_tmp_1(9);
+ cnt(10) <= cdb2vhdl_tmp_1(10);
+ cnt(11) <= cdb2vhdl_tmp_1(11);
+ -- Component instances
+ XCMP92 : entity work.and2(ideal)
+ port map(
+ in1 => clk,
+ in2 => enable,
+ output => XSIG010132
+ );
+ XCMP93 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => XSIG010132,
+ DATA => XSIG010078,
+ QN => XSIG010078,
+ Q => cdb2vhdl_tmp_1(0),
+ RST => reset
+ );
+ XCMP94 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(0),
+ DATA => XSIG010081,
+ QN => XSIG010081,
+ Q => cdb2vhdl_tmp_1(1),
+ RST => reset
+ );
+ XCMP95 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(1),
+ DATA => XSIG010083,
+ QN => XSIG010083,
+ Q => cdb2vhdl_tmp_1(2),
+ RST => reset
+ );
+ XCMP96 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(2),
+ DATA => XSIG010085,
+ QN => XSIG010085,
+ Q => cdb2vhdl_tmp_1(3),
+ RST => reset
+ );
+ XCMP97 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(3),
+ DATA => XSIG010087,
+ QN => XSIG010087,
+ Q => cdb2vhdl_tmp_1(4),
+ RST => reset
+ );
+ XCMP98 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(4),
+ DATA => XSIG010101,
+ QN => XSIG010101,
+ Q => cdb2vhdl_tmp_1(5),
+ RST => reset
+ );
+ XCMP99 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(5),
+ DATA => XSIG010102,
+ QN => XSIG010102,
+ Q => cdb2vhdl_tmp_1(6),
+ RST => reset
+ );
+ XCMP100 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(6),
+ DATA => XSIG010103,
+ QN => XSIG010103,
+ Q => cdb2vhdl_tmp_1(7),
+ RST => reset
+ );
+ XCMP101 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(7),
+ DATA => XSIG010104,
+ QN => XSIG010104,
+ Q => cdb2vhdl_tmp_1(8),
+ RST => reset
+ );
+ XCMP102 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(8),
+ DATA => XSIG010115,
+ QN => XSIG010115,
+ Q => cdb2vhdl_tmp_1(9),
+ RST => reset
+ );
+ XCMP103 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(9),
+ DATA => XSIG010116,
+ QN => XSIG010116,
+ Q => cdb2vhdl_tmp_1(10),
+ RST => reset
+ );
+ XCMP104 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(10),
+ DATA => XSIG010117,
+ QN => XSIG010117,
+ Q => cdb2vhdl_tmp_1(11),
+ RST => reset
+ );
+end counter_12;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- ideal one bit A/D converter
+
+LIBRARY IEEE;
+USE IEEE.math_real.ALL;
+USE IEEE.std_logic_1164.ALL;
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY a2d_bit IS
+
+ GENERIC (
+ thres : real := 2.5); -- Threshold to determine logic output
+
+ PORT (
+ TERMINAL a : electrical; -- analog input
+ SIGNAL d : OUT std_logic); -- digital (std_logic) output
+
+END ENTITY a2d_bit;
+
+
+ARCHITECTURE ideal OF a2d_bit IS
+
+ QUANTITY vin ACROSS a;
+
+ BEGIN -- threshold
+-- Process needed to detect threshold crossing and assign output (d)
+ PROCESS (vin'ABOVE(thres)) IS
+ BEGIN -- PROCESS
+ IF vin'ABOVE(thres) THEN
+ d <= '1';
+ ELSE
+ d <= '0';
+ END IF;
+ END PROCESS;
+
+END ideal;
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Digital clock with 50% duty cycle and enable pin
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock_en IS
+ GENERIC (
+ pw : time); -- Clock pulse width
+
+ PORT (
+ enable : IN std_logic ;
+ clock_out : INOUT std_logic := '0');
+
+END ENTITY clock_en;
+
+ARCHITECTURE ideal OF clock_en IS
+
+BEGIN
+
+-- clock process
+ process (clock_out, enable) is
+ begin
+ if clock_out = '0' AND enable = '1' THEN
+ clock_out <= '1' after pw, '0' after 2*pw;
+ end if;
+ end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Inverter
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY inverter IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ input : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY inverter;
+
+ARCHITECTURE ideal OF inverter IS
+BEGIN
+ output <= NOT input AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input OR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY or2 IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ in1, in2 : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY or2;
+
+ARCHITECTURE ideal OF or2 IS
+BEGIN
+ output <= in1 OR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY d2a_nbit IS
+
+ GENERIC (
+ vmax : real := 5.0; -- High output
+ vmin : real := 0.0; -- Low output
+ high_bit : integer := 9; -- High end of bit range for D/A
+ low_bit : integer := 0); -- Low end of bit range for D/A
+
+ PORT (
+ SIGNAL bus_in : IN STD_LOGIC_VECTOR; -- variable width vector input
+ SIGNAL latch : IN STD_LOGIC;
+ TERMINAL ana_out : electrical); -- analog output
+
+END ENTITY d2a_nbit ;
+
+ARCHITECTURE behavioral OF d2a_nbit IS
+
+ SIGNAL sout : real := 0.0;
+ QUANTITY vout across iout through ana_out TO electrical_ref;
+
+BEGIN -- ARCHITECTURE behavioral
+
+ proc : PROCESS
+
+ VARIABLE v_sum : real; -- Sum of voltage contribution from each bit
+ VARIABLE delt_v : real; -- Represents the voltage value of each bit
+
+ BEGIN
+ WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
+ v_sum := vmin;
+ delt_v := vmax - vmin;
+
+ FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
+ delt_v := delt_v / 2.0;
+ IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
+ v_sum := v_sum + delt_v;
+ END IF;
+ END LOOP;
+
+ sout <= v_sum;
+ END PROCESS;
+
+ vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
+
+END ARCHITECTURE behavioral;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pw2ana is
+ port(
+ terminal ana_out : electrical;
+ terminal pw_in : electrical
+ );
+end pw2ana;
+
+architecture pw2ana of pw2ana is
+ -- Component declarations
+ -- Signal declarations
+ signal bus_servo : std_logic_vector(0 to 11);
+ signal XSIG010008 : std_logic;
+ signal XSIG010013 : std_logic;
+ signal XSIG010019 : std_logic;
+ signal XSIG010020 : std_logic;
+ signal XSIG010021 : std_logic;
+ signal XSIG010022 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ counter_rudder : entity work.counter_12
+ port map(
+ enable => XSIG010022,
+ cnt => bus_servo,
+ reset => XSIG010021,
+ clk => XSIG010008
+ );
+ XCMP3 : entity work.a2d_bit(ideal)
+ port map(
+ D => XSIG010022,
+ A => pw_in
+ );
+ clk_en_rudder : entity work.clock_en(ideal)
+ generic map(
+ pw => 500ns
+ )
+ port map(
+ CLOCK_OUT => XSIG010008,
+ enable => XSIG010022
+ );
+ XCMP5 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => XSIG010022,
+ output => XSIG010013
+ );
+ XCMP8 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => XSIG010020,
+ output => XSIG010021
+ );
+ XCMP9 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => XSIG010022,
+ output => XSIG010019
+ );
+ or_rudder : entity work.or2(ideal)
+ port map(
+ in1 => XSIG010022,
+ in2 => XSIG010019,
+ output => XSIG010020
+ );
+ XCMP11 : entity work.d2a_nbit(behavioral)
+ generic map(
+ vmax => 4.8,
+ high_bit => 9,
+ low_bit => 0
+ )
+ port map(
+ bus_in => bus_servo,
+ ana_out => ana_out,
+ latch => XSIG010013
+ );
+end pw2ana;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : DC_Motor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+ generic (
+ r_wind : resistance; -- Motor winding resistance [Ohm]
+ kt : real; -- Torque coefficient [N*m/Amp]
+ l : inductance; -- Winding inductance [Henrys]
+ d : real; -- Damping coefficient [N*m/(rad/sec)]
+ j : mmoment_i); -- Moment of inertia [kg*meter**2]
+
+ port (terminal p1, p2 : electrical;
+ terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
+-- T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+ quantity v across i through p1 to p2;
+ quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+ torq == -1.0*kt*i + d*w + j*w'dot;
+ v == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : stop_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+ generic (
+ k_stop : real;
+-- ang_max : angle;
+-- ang_min : angle := 0.0;
+ ang_max : real;
+ ang_min : real := 0.0;
+ damp_stop : real := 0.000000001
+ );
+
+ port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+ quantity velocity : velocity;
+ quantity ang across trq through ang1 to ang2;
+
+begin
+
+ velocity == ang'dot;
+
+ if ang'above(ang_max) use
+ trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+ elsif ang'above(ang_min) use
+ trq == 0.0;
+ else
+ trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
+ end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-- 12-bit digital comparator model
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity dig_cmp is
+port
+(
+ eq : out std_logic := '0';
+ in1 : in std_logic_vector (0 to 11);
+ in2 : in std_logic_vector (0 to 11);
+ latch_in1 : in std_logic := '0'; -- Currently unused
+ latch_in2 : in std_logic := '0';
+ cmp : in std_logic := '0';
+ clk : in std_logic
+ );
+
+end entity dig_cmp ;
+
+architecture simple of dig_cmp is
+
+begin
+
+ compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
+ variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
+ BEGIN
+ if latch_in2 = '1' then -- in2 data is latched and stored
+ in2_hold := in2;
+ end if;
+ if cmp = '1' then
+ if in1 = in2_hold then -- latched in2 checked against current in1
+ eq <= '0';
+ else eq <= '1';
+ end if;
+ end if;
+ END PROCESS;
+end architecture simple;
+
+--
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical Resistor Model
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY resistor IS
+
+-- Initialize parameters
+ GENERIC (
+ res : RESISTANCE); -- resistance (no initial value)
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL p1, p2 : ELECTRICAL);
+
+END ENTITY resistor;
+
+-- Ideal Architecture (V = I*R)
+ARCHITECTURE ideal OF resistor IS
+
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH p1 TO p2;
+
+BEGIN
+
+-- Characteristic equations
+ v == i*res;
+
+END ARCHITECTURE ideal;
+
+--
+-- Set/reset flip flop
+-- When S goes high, Q is set high until reset
+-- When R goes high, Q is set low until set
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sr_ff is
+port
+(
+ S : in std_logic ;
+ R : in std_logic ;
+ Q : out std_logic
+);
+
+end sr_ff ;
+
+architecture simple of sr_ff is
+begin
+
+ set_reset: PROCESS(S, R) IS
+
+ BEGIN
+-- assert S='1' nand R='1' -- Warning if both inputs are high
+-- report "S and R are both active. Use with caution"
+-- severity warning;
+ if S'event AND S = '1' then
+ Q <= '1';
+ end if;
+ if R'event AND R = '1' then
+ Q <= '0';
+ end if;
+ END PROCESS set_reset;
+
+end;
+--
+
+--//////////////////////////////////////////////////////////////////
+-- NOTE: This is an intermediate file for HDL inspection only.
+-- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach_rcvr.sdg.
+-- Generated by sde2hdl version 16.1.0.2
+--//////////////////////////////////////////////////////////////////
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+USE IEEE_proposed.fluidic_systems.all;
+USE IEEE_proposed.thermal_systems.all;
+USE IEEE_proposed.radiant_systems.all;
+ENTITY state_mach_rcvr IS
+ PORT (
+ clk_50 : IN std_logic;
+ clk_100k : IN std_logic;
+ ser_done : IN std_logic;
+ par_det : IN std_logic;
+ frm_det : IN std_logic;
+ clk_6k : IN std_logic;
+ start_pulse : IN std_logic;
+ dly_done : IN std_logic;
+ s2p_rst : OUT std_logic;
+ s2p_en : OUT std_logic;
+ cnt1_en : OUT std_logic;
+ cnt1_rst : OUT std_logic;
+ cmp1_ltch1 : OUT std_logic;
+ cmp1_ltch2 : OUT std_logic;
+ cnt2_en : OUT std_logic;
+ cnt2_rst : OUT std_logic;
+ cmp2_ltch1 : OUT std_logic;
+ cmp2_ltch2 : OUT std_logic;
+ da_latch : OUT std_logic;
+ ser_cnt : OUT std_logic;
+ dly_cnt : OUT std_logic;
+ par_oe : OUT std_logic);
+
+END state_mach_rcvr;
+
+ARCHITECTURE state_diagram OF state_mach_rcvr IS
+
+ ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+ TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
+ , s_bit, par1, par2);
+ SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
+
+
+BEGIN
+
+sm1:
+ PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det)
+ BEGIN
+
+ CASE CS_state_mach_rcvr_sm1 IS
+ WHEN V_begin =>
+ cnt1_en <= ('0');
+ cnt1_rst <= ('1');
+ cmp1_ltch1 <= ('0');
+ cmp1_ltch2 <= ('0');
+ cnt2_en <= ('0');
+ cnt2_rst <= ('1');
+ cmp2_ltch1 <= ('0');
+ cmp2_ltch2 <= ('0');
+ s2p_en <= ('1');
+ s2p_rst <= ('0');
+ da_latch <= ('0');
+ ser_cnt <= ('0');
+ dly_cnt <= ('0');
+ par_oe <= ('0');
+
+ IF ((frm_det = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= s_bit;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= V_begin;
+ END IF;
+
+ WHEN cnt =>
+ ser_cnt <= ('1');
+ cnt1_rst <= ('0');
+ cnt2_rst <= ('0');
+
+ IF ((ser_done = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= par1;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= cnt;
+ END IF;
+
+ WHEN ch1 =>
+ cmp1_ltch2 <= ('1');
+ ser_cnt <= ('0');
+ dly_cnt <= ('1');
+
+ IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
+ NS_state_mach_rcvr_sm1 <= rst1;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= ch1;
+ END IF;
+
+ WHEN rst1 =>
+ cmp1_ltch2 <= ('0');
+ ser_cnt <= ('1');
+ dly_cnt <= ('0');
+ par_oe <= ('0');
+
+ IF ((ser_done = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= par2;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= rst1;
+ END IF;
+
+ WHEN ch2 =>
+ cmp2_ltch2 <= ('1');
+ ser_cnt <= ('0');
+ da_latch <= ('1');
+ NS_state_mach_rcvr_sm1 <= rst2;
+
+ WHEN rst2 =>
+ cmp2_ltch2 <= ('0');
+ s2p_en <= ('0');
+ par_oe <= ('0');
+ da_latch <= ('0');
+ NS_state_mach_rcvr_sm1 <= cnt_cmp;
+
+ WHEN cnt_cmp =>
+ cnt1_en <= ('1');
+ cmp1_ltch1 <= ('1');
+ cnt2_en <= ('1');
+ cmp2_ltch1 <= ('1');
+ NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+ WHEN rst_cnt =>
+ cnt1_en <= ('0');
+ cmp1_ltch1 <= ('0');
+ cnt2_en <= ('0');
+ cmp2_ltch1 <= ('0');
+ NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+ WHEN s_bit =>
+
+ IF ((start_pulse = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= cnt;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= s_bit;
+ END IF;
+
+ WHEN par1 =>
+ par_oe <= ('1');
+
+ IF ((par_det = '0')) THEN
+ NS_state_mach_rcvr_sm1 <= ch1;
+ ELSIF ((par_det = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= rst1;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= par1;
+ END IF;
+
+ WHEN par2 =>
+ par_oe <= ('1');
+
+ IF ((par_det = '0')) THEN
+ NS_state_mach_rcvr_sm1 <= ch2;
+ ELSIF ((par_det = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= rst2;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= par2;
+ END IF;
+
+ END CASE;
+
+ END PROCESS;
+
+sm1_CTL:
+ PROCESS (clk_100k, clk_50)
+ BEGIN
+
+ IF (clk_100k'event AND clk_100k='1') THEN
+ IF (clk_50= '1' ) THEN
+ CS_state_mach_rcvr_sm1 <= V_begin;
+ ELSE
+ CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
+ END IF;
+ END IF;
+
+ END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt_rcvr is
+ port(
+ cmp1_ltch1 : out std_logic;
+ cmp2_ltch1 : out std_logic;
+ s2p_en : out std_logic;
+ s2p_rst : out std_logic;
+ frm_det : in std_logic;
+ par_det : in std_logic;
+ clk_100k : in std_logic;
+ clk_6k : in std_logic;
+ clk_50 : in std_logic;
+ start_pulse : in std_logic;
+ cnt1_en : out std_logic;
+ cnt1_rst : out std_logic;
+ cmp1_ltch2 : out std_logic;
+ cnt2_en : out std_logic;
+ cnt2_rst : out std_logic;
+ cmp2_ltch2 : out std_logic;
+ da_latch : out std_logic;
+ par_oe : out std_logic
+ );
+end sm_cnt_rcvr;
+
+architecture sm_cnt_rcvr of sm_cnt_rcvr is
+ -- Component declarations
+ -- Signal declarations
+ terminal dly_cnt_a : electrical;
+ terminal dly_done_a : electrical;
+ terminal ser_cnt_a : electrical;
+ terminal ser_done_a : electrical;
+ signal XSIG010001 : std_logic;
+ signal XSIG010002 : std_logic;
+ signal XSIG010145 : std_logic;
+ signal XSIG010146 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ XCMP1 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010001,
+ A => ser_cnt_a
+ );
+ XCMP2 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010002,
+ A => ser_done_a
+ );
+ bit_cnt3 : entity work.bit_cnt(behavioral)
+ generic map(
+ count => 2
+ )
+ port map(
+ bit_in => XSIG010145,
+ clk => clk_6k,
+ dly_out => XSIG010146
+ );
+ bit_cnt4 : entity work.bit_cnt(behavioral)
+ generic map(
+ count => 10
+ )
+ port map(
+ bit_in => XSIG010001,
+ clk => clk_6k,
+ dly_out => XSIG010002
+ );
+ XCMP8 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010145,
+ A => dly_cnt_a
+ );
+ XCMP9 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010146,
+ A => dly_done_a
+ );
+ state_mach_rcvr8 : entity work.state_mach_rcvr
+ port map(
+ clk_100k => clk_100k,
+ clk_50 => clk_50,
+ s2p_rst => s2p_rst,
+ s2p_en => s2p_en,
+ cnt1_en => cnt1_en,
+ cnt1_rst => cnt1_rst,
+ cmp1_ltch1 => cmp1_ltch1,
+ cmp1_ltch2 => cmp1_ltch2,
+ cnt2_en => cnt2_en,
+ cnt2_rst => cnt2_rst,
+ cmp2_ltch1 => cmp2_ltch1,
+ cmp2_ltch2 => cmp2_ltch2,
+ da_latch => da_latch,
+ ser_cnt => XSIG010001,
+ ser_done => XSIG010002,
+ par_det => par_det,
+ frm_det => frm_det,
+ clk_6k => clk_6k,
+ start_pulse => start_pulse,
+ dly_done => XSIG010146,
+ dly_cnt => XSIG010145,
+ par_oe => par_oe
+ );
+end sm_cnt_rcvr;
+--
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- level_set.vhd
+-- Set digital output "level" with parameter "logic_val" (default is '1')
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set IS
+
+ GENERIC (
+ logic_val : std_logic := '1');
+
+ PORT (
+ level : OUT std_logic);
+
+END ENTITY level_set;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set IS
+
+BEGIN
+
+ level <= logic_val;
+
+END ARCHITECTURE ideal;
+
+--
+
+-- Serial to parallel data converter
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity ser2par is
+port
+(
+ par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
+ clk : in std_logic ;
+ load_en : in std_logic ;
+ ser_in : in std_logic ;
+ reset : in std_logic
+);
+
+begin
+
+end ser2par;
+
+architecture a1 of ser2par is
+BEGIN
+ sr_sm: PROCESS (load_en, clk, reset, ser_in)
+ BEGIN
+ if (reset = '1' and load_en = '1') then
+ par_out <= "000000000000"; -- Reset the parallel data out
+
+ elsif (clk'event and clk = '1') then
+ if (load_en ='1') then
+
+ -- The register will shift when load is enabled
+ -- and will shift at rising edge of clock
+
+ par_out(0) <= ser_in; -- Input data shifts into bit 0
+ par_out(1) <= par_out(0);
+ par_out(2) <= par_out(1);
+ par_out(3) <= par_out(2);
+ par_out(4) <= par_out(3);
+ par_out(5) <= par_out(4);
+ par_out(6) <= par_out(5);
+ par_out(7) <= par_out(6);
+ par_out(8) <= par_out(7);
+ par_out(9) <= par_out(8);
+ par_out(10) <= par_out(9);
+ par_out(11) <= par_out(10);
+
+ else
+ -- The otput data will not change
+ -- if load_en is not enabled
+ par_out <= "ZZZZZZZZZZZZ";
+ end if;
+ end if;
+ END PROCESS;
+end;
+--
+
+-- This model ouputs a '1' when a specific bit pattern is encountered
+-- Otherwise, it outputs a zero
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_det is
+port
+(
+ bus_in : in std_logic_vector (0 to 11);
+ clk : in std_logic;
+ frm_bit : out std_logic := '0' -- Initialize output to zero
+ );
+
+end entity frame_det;
+
+architecture simple of frame_det is
+begin
+ enbl: PROCESS (bus_in, clk) -- Sensitivity list
+ BEGIN
+ if bus_in = "010101010101" then -- This is the pre-defined bit pattern
+ if clk'event AND clk = '0' then -- Output updated synchronously
+ frm_bit <= '1';
+ end if;
+ else frm_bit <= '0';
+ end if;
+ END PROCESS;
+end architecture simple;
+
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_det is
+ port(
+ bus_in : in std_logic_vector(0 to 11);
+ par_bit : out std_logic;
+ oe : in std_logic
+ );
+end parity_det;
+
+architecture parity_det of parity_det is
+ -- Component declarations
+ -- Signal declarations
+ signal cdb2vhdl_tmp_1 : std_logic;
+ terminal par_bit_a : electrical;
+ signal XSIG010010 : std_logic;
+ signal XSIG010011 : std_logic;
+ signal XSIG010012 : std_logic;
+ signal XSIG010013 : std_logic;
+ signal XSIG010014 : std_logic;
+ signal XSIG010015 : std_logic;
+ signal XSIG010016 : std_logic;
+ signal XSIG010017 : std_logic;
+ signal XSIG010019 : std_logic;
+ signal XSIG010057 : std_logic;
+begin
+ -- Signal assignments
+ par_bit <= cdb2vhdl_tmp_1;
+ -- Component instances
+ XCMP1 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(1),
+ in2 => bus_in(2),
+ output => XSIG010010
+ );
+ XCMP2 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(3),
+ in2 => bus_in(4),
+ output => XSIG010011
+ );
+ XCMP3 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(5),
+ in2 => bus_in(6),
+ output => XSIG010012
+ );
+ XCMP4 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(7),
+ in2 => bus_in(8),
+ output => XSIG010013
+ );
+ XCMP5 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(9),
+ in2 => bus_in(10),
+ output => XSIG010016
+ );
+ XCMP6 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010010,
+ in2 => XSIG010011,
+ output => XSIG010014
+ );
+ XCMP7 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010012,
+ in2 => XSIG010013,
+ output => XSIG010015
+ );
+ XCMP8 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010014,
+ in2 => XSIG010015,
+ output => XSIG010017
+ );
+ XCMP9 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010017,
+ in2 => XSIG010016,
+ output => XSIG010019
+ );
+ XCMP10 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010019,
+ in2 => bus_in(0),
+ output => XSIG010057
+ );
+ XCMP11 : entity work.d2a_bit(ideal)
+ port map(
+ D => cdb2vhdl_tmp_1,
+ A => par_bit_a
+ );
+ XCMP12 : entity work.and2(ideal)
+ port map(
+ in1 => oe,
+ in2 => XSIG010057,
+ output => cdb2vhdl_tmp_1
+ );
+end parity_det;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TDM_Demux_dbg is
+ port(
+ s2p_en : in std_logic;
+ tdm_in : in std_logic;
+ clk_6k : in std_logic;
+ s2p_rst : in std_logic;
+ par_det : out std_logic;
+ frm_det : out std_logic;
+ da_latch : in std_logic;
+ par_oe : in std_logic;
+ data_bus : out std_logic_vector(1 to 10);
+ start_bit : out std_logic
+ );
+end TDM_Demux_dbg;
+
+architecture TDM_Demux_dbg of TDM_Demux_dbg is
+ -- Component declarations
+ -- Signal declarations
+ terminal d2a_out : electrical;
+ signal rcvr_bus : std_logic_vector(0 to 11);
+begin
+ -- Signal assignments
+ data_bus(1) <= rcvr_bus(1);
+ data_bus(2) <= rcvr_bus(2);
+ data_bus(3) <= rcvr_bus(3);
+ data_bus(4) <= rcvr_bus(4);
+ data_bus(5) <= rcvr_bus(5);
+ data_bus(6) <= rcvr_bus(6);
+ data_bus(7) <= rcvr_bus(7);
+ data_bus(8) <= rcvr_bus(8);
+ data_bus(9) <= rcvr_bus(9);
+ data_bus(10) <= rcvr_bus(10);
+ start_bit <= rcvr_bus(0);
+ -- Component instances
+ s2p1 : entity work.ser2par(a1)
+ port map(
+ par_out => rcvr_bus,
+ clk => clk_6k,
+ load_en => s2p_en,
+ ser_in => tdm_in,
+ reset => s2p_rst
+ );
+ frm_det1 : entity work.frame_det(simple)
+ port map(
+ bus_in => rcvr_bus,
+ frm_bit => frm_det,
+ clk => clk_6k
+ );
+ par_det1 : entity work.parity_det
+ port map(
+ bus_in => rcvr_bus,
+ par_bit => par_det,
+ oe => par_oe
+ );
+ XCMP113 : entity work.d2a_nbit(behavioral)
+ generic map(
+ low_bit => 1,
+ high_bit => 10,
+ vmax => 4.8
+ )
+ port map(
+ bus_in => rcvr_bus(1 to 10),
+ ana_out => d2a_out,
+ latch => da_latch
+ );
+end TDM_Demux_dbg;
+--
+
+-- Manchester Decoder with clock recovery using 8x referenced clock
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity mdec_rsc is
+-- port ( din: in real; -- real input
+ port ( din: in std_logic; -- real input
+ clk16x: in std_logic; -- 16x referenced clock
+ reset: in std_logic; -- not reset
+ bout: out std_logic := '0'; -- digital output
+ clk_out: inout std_logic := '0'); -- recovered clock
+end entity mdec_rsc;
+
+architecture bhv of mdec_rsc is
+-- signal bhigh:real:= 1.0; -- bit decoding
+-- signal blow:real:= -1.0; -- bit decoding
+-- signal bnormal:real:=0.0; -- bit decoding
+ signal bhigh:std_logic:= '1'; -- bit decoding
+ signal blow:std_logic:= '0'; -- bit decoding
+ signal bout1:std_logic;
+ signal clk_div:std_logic_vector(3 downto 0):="0000"; -- clock counter
+ signal trans:std_logic; -- transisition trigger
+begin
+ -- bit decoding
+ proc1: process (reset,din,clk16x)
+ begin
+ if (reset = '1') then
+ bout1 <= 'X';
+ elsif (clk16x'event and clk16x = '1') then
+ if (din = bhigh) then
+ bout1 <= '1';
+ elsif (din = blow) then
+ bout1 <= '0';
+ else
+ bout1 <= 'X';
+ end if;
+ end if;
+ end process;
+
+ -- clock counter
+ proc2: process (reset, clk16x, clk_div)
+ begin
+
+ if (reset = '1') then
+ clk_div <= "0000";
+ elsif (clk16x'event and clk16x = '1') then
+ clk_div <= clk_div + "0001";
+ end if;
+ end process;
+
+ -- recovered clock
+ -- clk_out <= not clk_div(3);
+ clk_out <= clk_div(3);
+
+ -- transition trigger
+trans <= ((not clk_div(3)) and (not clk_div(2)) and clk_div(1) and clk_div(0)) or
+ (clk_div(3) and clk_div(2) and (not clk_div(1)) and (not clk_div(0)));
+
+ -- Manchester decoder
+ proc3: process (reset, trans, bout1, clk_out, clk16x)
+ begin
+ if (reset = '1') then
+ bout <= '0';
+ elsif (clk16x'event and clk16x = '1') then
+ if (trans = '1') then
+ bout <= bout1 XOR clk_out;
+ end if;
+ end if;
+ end process;
+
+end architecture bhv;
+
+architecture bhv_8 of mdec_rsc is
+-- signal bhigh:real:= 1.0; -- bit decoding
+-- signal blow:real:= -1.0; -- bit decoding
+-- signal bnormal:real:=0.0; -- bit decoding
+ signal bhigh:std_logic:= '1'; -- bit decoding
+ signal blow:std_logic:= '0'; -- bit decoding
+ signal bout1:std_logic;
+ signal clk_div:std_logic_vector(2 downto 0):="000"; -- clock counter
+ signal trans:std_logic; -- transisition trigger
+begin
+ -- bit decoding
+ proc1: process (reset,din,clk16x)
+ begin
+ if (reset = '1') then
+ bout1 <= 'X';
+ elsif (clk16x'event and clk16x = '1') then
+ if (din = bhigh) then
+ bout1 <= '1';
+ elsif (din = blow) then
+ bout1 <= '0';
+ else
+ bout1 <= 'X';
+ end if;
+ end if;
+ end process;
+
+ -- clock counter
+ proc2: process (reset, clk16x, clk_div)
+ begin
+
+ if (reset = '1') then
+ clk_div <= "000";
+ elsif (clk16x'event and clk16x = '1') then
+ clk_div <= clk_div + "001";
+ end if;
+ end process;
+
+ -- recovered clock
+ clk_out <= not clk_div(2);
+
+ -- transition trigger
+ trans <= ((not clk_div(1)) and clk_div(0)) or (clk_div(1) and (not clk_div(0)));
+
+ -- Manchester decoder
+ proc3: process (reset, trans, bout1, clk_out, clk16x)
+ begin
+ if (reset = '1') then
+ bout <= '0';
+ elsif (clk16x'event and clk16x = '1') then
+ if (trans = '1') then
+ bout <= bout1 XOR clk_out;
+ end if;
+ end if;
+ end process;
+
+end architecture bhv_8;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Decode_PW_Man is
+ port(
+ terminal power : electrical;
+ terminal ch1_pw : electrical;
+ terminal ch2_pw : electrical;
+ bit_stream_in : in std_logic
+ );
+end Decode_PW_Man;
+
+architecture Decode_PW_Man of Decode_PW_Man is
+ -- Component declarations
+ -- Signal declarations
+ signal bit_stream_in_mdec : std_logic;
+ signal clk16x : std_logic;
+ signal clk6k : std_logic;
+ signal clk_100k : std_logic;
+ signal cmp_bus : std_logic_vector(0 to 11);
+ signal cnt1 : std_logic_vector(0 to 11);
+ signal cnt2 : std_logic_vector(0 to 11);
+ signal mdec_clk : std_logic;
+ signal mdec_out : std_logic;
+ signal reset : std_logic;
+ signal reset_m : std_logic;
+ signal XSIG010228 : std_logic;
+ signal XSIG010229 : std_logic;
+ signal XSIG010256 : std_logic;
+ signal XSIG010263 : std_logic;
+ signal XSIG010264 : std_logic;
+ signal XSIG010266 : std_logic;
+ signal XSIG010267 : std_logic;
+ signal XSIG010268 : std_logic;
+ signal XSIG010320 : std_logic;
+ signal XSIG010330 : std_logic;
+ signal XSIG010334 : std_logic;
+ signal XSIG010339 : std_logic;
+ signal XSIG010349 : std_logic;
+ signal XSIG010357 : std_logic;
+ signal XSIG010371 : std_logic;
+ signal XSIG010372 : std_logic;
+ signal XSIG010373 : std_logic;
+ signal XSIG010383 : std_logic;
+ signal XSIG010384 : std_logic;
+ signal XSIG010385 : std_logic;
+ signal XSIG010386 : std_logic;
+ signal XSIG010390 : std_logic;
+ signal XSIG010433 : std_logic;
+begin
+ -- Signal assignments
+ bit_stream_in_mdec <= bit_stream_in;
+ -- Component instances
+ cntr1 : entity work.counter_12
+ port map(
+ enable => XSIG010384,
+ cnt => cnt1,
+ reset => XSIG010357,
+ clk => XSIG010433
+ );
+ cntr2 : entity work.counter_12
+ port map(
+ enable => XSIG010349,
+ cnt => cnt2,
+ reset => XSIG010385,
+ clk => XSIG010320
+ );
+ cmp1 : entity work.dig_cmp(simple)
+ port map(
+ in1 => cnt1,
+ eq => XSIG010371,
+ clk => XSIG010433,
+ in2 => cmp_bus,
+ cmp => XSIG010384,
+ latch_in1 => XSIG010256,
+ latch_in2 => XSIG010383
+ );
+ cmp2 : entity work.dig_cmp(simple)
+ port map(
+ in1 => cnt2,
+ eq => XSIG010372,
+ clk => XSIG010320,
+ in2 => cmp_bus,
+ cmp => XSIG010349,
+ latch_in1 => XSIG010263,
+ latch_in2 => XSIG010264
+ );
+ XCMP109 : entity work.resistor(ideal)
+ generic map(
+ res => 1000000.0
+ )
+ port map(
+ p1 => power,
+ p2 => ELECTRICAL_REF
+ );
+ clk_1M2 : entity work.clock_en(ideal)
+ generic map(
+ pw => 500 ns
+ )
+ port map(
+ CLOCK_OUT => XSIG010320,
+ enable => XSIG010349
+ );
+ clk_1M1 : entity work.clock_en(ideal)
+ generic map(
+ pw => 500 ns
+ )
+ port map(
+ CLOCK_OUT => XSIG010433,
+ enable => XSIG010384
+ );
+ XCMP134 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010371,
+ A => ch1_pw
+ );
+ XCMP135 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010372,
+ A => ch2_pw
+ );
+ XCMP137 : entity work.SR_FF(simple)
+ port map(
+ S => XSIG010330,
+ R => XSIG010334,
+ Q => XSIG010349
+ );
+ XCMP138 : entity work.inverter(ideal)
+ port map(
+ input => XSIG010372,
+ output => XSIG010334
+ );
+ XCMP139 : entity work.SR_FF(simple)
+ port map(
+ S => XSIG010373,
+ R => XSIG010339,
+ Q => XSIG010384
+ );
+ XCMP140 : entity work.inverter(ideal)
+ port map(
+ input => XSIG010371,
+ output => XSIG010339
+ );
+ rc_clk2 : entity work.rc_clk
+ port map(
+ clk_50 => reset,
+ clk_6K => clk6k,
+ clk_100k => clk_100k
+ );
+ sm_rcvr1 : entity work.sm_cnt_rcvr
+ port map(
+ cnt1_en => XSIG010373,
+ cmp1_ltch1 => XSIG010256,
+ cnt2_rst => XSIG010385,
+ clk_100k => clk_100k,
+ cnt1_rst => XSIG010357,
+ cnt2_en => XSIG010330,
+ cmp2_ltch1 => XSIG010263,
+ frm_det => XSIG010229,
+ par_det => XSIG010228,
+ s2p_en => XSIG010266,
+ s2p_rst => XSIG010267,
+ clk_6k => mdec_clk,
+ clk_50 => reset,
+ da_latch => XSIG010268,
+ cmp1_ltch2 => XSIG010383,
+ cmp2_ltch2 => XSIG010264,
+ start_pulse => XSIG010390,
+ par_oe => XSIG010386
+ );
+ XCMP155 : entity work.level_set(ideal)
+ generic map(
+ logic_val => '0'
+ )
+ port map(
+ level => cmp_bus(11)
+ );
+ XCMP157 : entity work.TDM_Demux_dbg
+ port map(
+ data_bus => cmp_bus(0 to 9),
+ tdm_in => mdec_out,
+ clk_6k => mdec_clk,
+ s2p_en => XSIG010266,
+ s2p_rst => XSIG010267,
+ da_latch => XSIG010268,
+ frm_det => XSIG010229,
+ par_det => XSIG010228,
+ par_oe => XSIG010386,
+ start_bit => XSIG010390
+ );
+ XCMP172 : entity work.level_set(ideal)
+ generic map(
+ logic_val => '1'
+ )
+ port map(
+ level => cmp_bus(10)
+ );
+ clock1 : entity work.clock(ideal)
+ generic map(
+ period => 9.375us
+ )
+ port map(
+ CLK_OUT => clk16x
+ );
+ mdec_rsc7 : entity work.mdec_rsc(bhv)
+ port map(
+ din => bit_stream_in_mdec,
+ clk16x => clk16x,
+ reset => reset_m,
+ bout => mdec_out,
+ clk_out => mdec_clk
+ );
+ XCMP181 : entity work.clock_duty(ideal)
+ generic map(
+ off_time => 19.98 sec
+ )
+ port map(
+ CLOCK_OUT => reset_m
+ );
+end Decode_PW_Man;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CS5_CC_Rudder is
+end tb_CS5_CC_Rudder;
+
+architecture TB_CS5_CC_Rudder of tb_CS5_CC_Rudder is
+ -- Component declarations
+ -- Signal declarations
+ terminal gear_out : rotational;
+ terminal link_in : translational;
+ terminal link_out : translational;
+ terminal pot_fb : electrical;
+ signal rf_in : std_logic;
+ signal rf_out : std_logic;
+ terminal rudder : rotational;
+ terminal rudder_ana : electrical;
+ terminal rudder_cmd : electrical;
+ terminal rudder_mtr_in : electrical;
+ terminal rudder_mtr_out : rotational_v;
+ terminal rudder_pw : electrical;
+ terminal rudder_servo_in : electrical;
+ terminal throttle_ana : electrical;
+ terminal throttle_cmd : electrical;
+ terminal throttle_pw : electrical;
+ terminal XSIG010013 : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ rudder_servo1 : entity work.rudder_servo
+ port map(
+ servo_out => rudder_mtr_in,
+ servo_in => rudder_servo_in,
+ pos_fb => pot_fb
+ );
+ gear1 : entity work.gear_rv_r(ideal)
+ generic map(
+ ratio => 0.01
+ )
+ port map(
+ rotv1 => rudder_mtr_out,
+ rot2 => gear_out
+ );
+ potentiometer : entity work.rot2v(bhv)
+ generic map(
+ k => 1.0
+ )
+ port map(
+ output => pot_fb,
+ input => gear_out
+ );
+ g_horn : entity work.horn_r2t(bhv)
+ port map(
+ theta => gear_out,
+ pos => link_in
+ );
+ r_horn : entity work.horn_t2r(bhv)
+ port map(
+ theta => rudder,
+ pos => link_out
+ );
+ \linkage\ : entity work.tran_linkage(a1)
+ port map(
+ p2 => link_out,
+ p1 => link_in
+ );
+ rudder_1 : entity work.rudder(bhv)
+ generic map(
+ k => 0.2
+ )
+ port map(
+ rot => rudder
+ );
+ XCMP6 : entity work.v_constant(ideal)
+ generic map(
+ level => 5.0
+ )
+ port map(
+ pos => XSIG010013,
+ neg => ELECTRICAL_REF
+ );
+ t_stick : entity work.stick(ideal)
+ generic map(
+ offset => 2.397,
+ phase => 0.0,
+ amplitude => 2.397,
+ freq => 1.0
+ )
+ port map(
+ v_out => throttle_cmd
+ );
+ r_stick : entity work.stick(ideal)
+ generic map(
+ freq => 1.0,
+ amplitude => 2.397,
+ phase => 270.0,
+ offset => 2.397
+ )
+ port map(
+ v_out => rudder_cmd
+ );
+ RF : entity work.rf_xmtr_rcvr(behavioral)
+ port map(
+ tdm_in => rf_in,
+ tdm_out => rf_out
+ );
+ Digitize_Encode1 : entity work.Digitize_Encode_Man
+ port map(
+ ch2_in => rudder_cmd,
+ ch1_in => throttle_cmd,
+ tdm_out => rf_in
+ );
+ filter : entity work.lpf_2_e(simple)
+ generic map(
+ f2 => 10.0,
+ f1 => 10.0
+ )
+ port map(
+ input => rudder_ana,
+ output => rudder_servo_in
+ );
+ t_pw2ana : entity work.pw2ana
+ port map(
+ ana_out => throttle_ana,
+ pw_in => throttle_pw
+ );
+ r_pw2ana : entity work.pw2ana
+ port map(
+ ana_out => rudder_ana,
+ pw_in => rudder_pw
+ );
+ motor2 : entity work.DC_Motor(basic)
+ generic map(
+ r_wind => 2.2,
+ kt => 3.43e-3,
+ l => 2.03e-3,
+ d => 5.63e-6,
+ j => 168.0e-9
+ )
+ port map(
+ p1 => rudder_mtr_in,
+ p2 => ELECTRICAL_REF,
+ shaft_rotv => rudder_mtr_out
+ );
+ stop3 : entity work.stop_r(ideal)
+ generic map(
+ k_stop => 1.0e6,
+ ang_max => 1.05,
+ ang_min => -1.05,
+ damp_stop => 1.0e2
+ )
+ port map(
+ ang1 => gear_out,
+ ang2 => ROTATIONAL_REF
+ );
+ Decode_PW_Man2 : entity work.Decode_PW_Man
+ port map(
+ bit_stream_in => rf_out,
+ ch2_pw => rudder_pw,
+ ch1_pw => throttle_pw,
+ power => XSIG010013
+ );
+end TB_CS5_CC_Rudder;
+--
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd
new file mode 100644
index 000000000..d4d70577c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd
@@ -0,0 +1,4192 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+ generic (k1, k2: real := 1.0); -- Gain multipliers
+ port ( terminal in1, in2: electrical;
+ terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+ QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+ QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+ generic (
+ k: REAL := 1.0); -- Gain multiplier
+ port ( terminal input : electrical;
+ terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+ generic (
+ limit_high : real := 4.8; -- upper limit
+ limit_low : real := -4.8); -- lower limit
+ port (
+ terminal input: electrical;
+ terminal output: electrical);
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+ constant slope : real := 1.0e-4;
+begin
+ if vin > limit_high use -- Upper limit exceeded, so limit input signal
+ vout == limit_high + slope*(vin - limit_high);
+ elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
+ vout == limit_low + slope*(vin - limit_low);
+ else -- No limit exceeded, so pass input signal as is
+ vout == vin;
+ end use;
+ break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+-- Transfer Function:
+--
+-- (s + w1)
+-- H(s) = k * ----------
+-- (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lead_lag_e is
+ generic (
+ k: real := 1.0; -- Gain multiplier
+ f1: real := 10.0; -- First break frequency (zero)
+ f2: real := 100.0); -- Second break frequency (pole)
+ port ( terminal input: electrical;
+ terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ quantity vin_temp : real;
+ constant w1 : real := f1*math_2_pi;
+ constant w2 : real := f2*math_2_pi;
+ constant num : real_vector := (w1, 1.0);
+ constant den : real_vector := (w2, 1.0);
+begin
+ vin_temp == vin;
+ vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo is
+ port(
+ terminal servo_in : electrical;
+ terminal pos_fb : electrical;
+ terminal servo_out : electrical
+ );
+end rudder_servo;
+
+architecture rudder_servo of rudder_servo is
+ -- Component declarations
+ -- Signal declarations
+ terminal error : electrical;
+ terminal ll_in : electrical;
+ terminal ll_out : electrical;
+ terminal summer_fb : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ summer : entity work.sum2_e(simple)
+ port map(
+ in1 => servo_in,
+ in2 => summer_fb,
+ output => error
+ );
+ forward_gain : entity work.gain_e(simple)
+ generic map(
+ k => 100.0
+ )
+ port map(
+ input => error,
+ output => ll_in
+ );
+ fb_gain : entity work.gain_e(simple)
+ generic map(
+ k => -4.57
+ )
+ port map(
+ input => pos_fb,
+ output => summer_fb
+ );
+ servo_limiter : entity work.limiter_2_e(simple)
+ generic map(
+ limit_high => 4.8,
+ limit_low => -4.8
+ )
+ port map(
+ input => ll_out,
+ output => servo_out
+ );
+ lead_lag : entity work.lead_lag_e(simple)
+ generic map(
+ k => 400.0,
+ f1 => 5.0,
+ f2 => 2000.0
+ )
+ port map(
+ input => ll_in,
+ output => ll_out
+ );
+end rudder_servo;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : gear_rv_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/10/10 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+ generic(
+ ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+ -- Note: can be negative, if shaft polarity changes
+
+ port ( terminal rotv1 : rotational_v;
+ terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+ quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
+ quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+-- w2 == w1*ratio;
+ theta == ratio*w1'integ;
+ torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+
+ generic (
+ k : real := 1.0); -- optional gain
+
+ port (
+ terminal input : rotational; -- input terminal
+ terminal output : electrical); -- output terminal
+
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref; -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+ begin -- bhv
+ v_out == k*rot_in;
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- tran = R*sin(rot)
+--
+-- Where pos = output translational position,
+-- R = horn radius,
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+
+ generic (
+ R : real := 1.0); -- horn radius
+
+ port (
+ terminal theta : ROTATIONAL; -- input angular position port
+ terminal pos : TRANSLATIONAL); -- output translational position port
+
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+ begin -- bhv
+ tran == R*sin(rot); -- Convert angle in to translational out
+ tran_frc == -rot_tq/R; -- Convert torque in to force out
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- theta = arcsin(pos/R)
+--
+-- Where pos = input translational position,
+-- R = horn radius,
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+
+ generic (
+ R : real := 1.0); -- Rudder horn radius
+
+ port (
+ terminal pos : translational; -- input translational position port
+ terminal theta : rotational); -- output angular position port
+
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+ begin -- bhv
+ rot == arcsin(tran/R); -- Convert translational to angle
+ rot_tq == -tran_frc*R; -- Convert force to torque
+
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : DC_Motor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+ generic (
+ r_wind : resistance; -- Motor winding resistance [Ohm]
+ kt : real; -- Torque coefficient [N*m/Amp]
+ l : inductance; -- Winding inductance [Henrys]
+ d : real; -- Damping coefficient [N*m/(rad/sec)]
+ j : mmoment_i); -- Moment of inertia [kg*meter**2]
+
+ port (terminal p1, p2 : electrical;
+ terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
+-- T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+ quantity v across i through p1 to p2;
+ quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+ torq == -1.0*kt*i + d*w + j*w'dot;
+ v == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : stop_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+ generic (
+ k_stop : real;
+-- ang_max : angle;
+-- ang_min : angle := 0.0;
+ ang_max : real;
+ ang_min : real := 0.0;
+ damp_stop : real := 0.000000001
+ );
+
+ port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+ quantity velocity : velocity;
+ quantity ang across trq through ang1 to ang2;
+
+begin
+
+ velocity == ang'dot;
+
+ if ang'above(ang_max) use
+ trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+ elsif ang'above(ang_min) use
+ trq == 0.0;
+ else
+ trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
+ end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+ terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+ QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+ QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+ pos_2 == pos_1; -- Pass position
+ frc_2 == -frc_1; -- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+-- Transfer Function:
+--
+-- torq = -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+
+ generic (
+ k : real := 1.0; -- Spring constant
+ theta_0 : real := 0.0);
+
+ port (
+ terminal rot : rotational); -- input rotational angle
+
+end entity rudder;
+
+architecture bhv of rudder is
+
+ QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+ begin -- bhv
+
+ torq == k*(theta - theta_0); -- Convert force to torque
+
+end bhv;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Constant Voltage Source (Includes Frequency Domain settings)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY v_constant IS
+
+-- Initialize parameters
+ GENERIC (
+ level : VOLTAGE; -- Constant voltage value (V)
+ ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
+ ac_phase : real := 0.0); -- AC phase (degrees)
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL pos, neg : ELECTRICAL);
+
+END ENTITY v_constant;
+
+-- Ideal Architecture (I = constant)
+ARCHITECTURE ideal OF v_constant IS
+
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH pos TO neg;
+-- Declare quantity in frequency domain for AC analysis
+ QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+
+ IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
+ v == level;
+ ELSE
+ v == ac_spec; -- used for Frequency (AC) analysis
+ END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical sinusoidal voltage source (stick.vhd)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+
+ENTITY stick IS
+
+-- Initialize parameters
+ GENERIC (
+ freq : real; -- frequency, [Hertz]
+ amplitude : real; -- amplitude, [Volt]
+ phase : real := 0.0; -- initial phase, [Degree]
+ offset : real := 0.0; -- DC value, [Volt]
+ df : real := 0.0; -- damping factor, [1/second]
+ ac_mag : real := 1.0; -- AC magnitude, [Volt]
+ ac_phase : real := 0.0); -- AC phase, [Degree]
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL v_out : ELECTRICAL);
+
+END ENTITY stick;
+
+-- Ideal Architecture
+ARCHITECTURE ideal OF stick IS
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
+-- Declare Quantity for Phase in radians (calculated below)
+ QUANTITY phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+ QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+-- Convert phase to radians
+ phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+ IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
+ v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+ ELSE
+ v == ac_spec; -- used for Frequency (AC) analysis
+ END USE;
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity RF_xmtr_rcvr is
+generic (td : time := 0ns);
+port
+(
+ tdm_in : in std_logic ;
+ tdm_out : out std_logic
+);
+
+end RF_xmtr_rcvr;
+
+architecture behavioral of RF_xmtr_rcvr is
+begin
+
+tdm_out <= tdm_in after td;
+
+end;
+--
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Simple Digital-Controlled Two-position Switch Model
+-- Switch position 1 ('0') or switch position 2 ('1')
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY switch_dig_2in is
+ GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
+ r_closed : RESISTANCE := 0.001; -- Closed switch resistance
+ trans_time : real := 0.00001); -- Transition time to each position
+
+ PORT (sw_state : in std_logic; -- Digital control input
+ TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
+
+END ENTITY switch_dig_2in;
+
+
+ARCHITECTURE ideal OF switch_dig_2in IS
+
+-- CONSTANT log_r_open : real := log10(r_open);
+-- CONSTANT log_r_closed : real := log10(r_closed);
+-- SIGNAL r_sig1 : RESISTANCE := log_r_closed; -- Variable to accept switch resistance
+-- SIGNAL r_sig2 : RESISTANCE := log_r_open; -- Variable to accept switch resistance
+ SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
+ SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
+ QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
+ QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
+ QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
+ QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
+
+BEGIN
+
+ PROCESS (sw_state) -- Sensitivity to digital control input
+ BEGIN
+ IF (sw_state'event AND sw_state = '0') THEN -- Close sig1, open sig2
+ r_sig1 <= r_closed;
+ r_sig2 <= r_open;
+ ELSIF (sw_state'event AND sw_state = '1') THEN -- Open sig1, close sig2
+ r_sig1 <= r_open;
+ r_sig2 <= r_closed;
+ END IF;
+ END PROCESS;
+
+ r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
+ r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
+ v1 == r1*i1; -- Apply Ohm's law to in1
+ v2 == r2*i2; -- Apply Ohm's law to in2
+
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Digital clock with 50% duty cycle
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock IS
+ GENERIC (
+ period : time); -- Clock period
+
+ PORT (
+ clk_out : OUT std_logic);
+
+END ENTITY clock;
+
+ARCHITECTURE ideal OF clock IS
+
+BEGIN
+
+-- clock process
+ process
+ begin
+ clk_out <= '0';
+ wait for period/2;
+ clk_out <= '1';
+ wait for period/2;
+ end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- This digital clock allows user to specify the duty cycle using
+-- the parameters "on_time" and "off_time"
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY clock_duty IS
+
+ GENERIC (
+ on_time : time := 20 us;
+ off_time : time := 19.98 ms
+ );
+
+ PORT (
+ clock_out : OUT std_logic := '0');
+
+END ENTITY clock_duty;
+
+ARCHITECTURE ideal OF clock_duty IS
+
+BEGIN
+
+-- clock process
+ process
+ begin
+ clock_out <= '1';
+ wait for on_time;
+ clock_out <= '0';
+ wait for off_time;
+ end process;
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rc_clk is
+ port(
+ clk_100k : out std_logic;
+ clk_6K : out std_logic;
+ clk_50 : out std_logic
+ );
+end rc_clk;
+
+architecture rc_clk of rc_clk is
+ -- Component declarations
+ -- Signal declarations
+begin
+ -- Signal assignments
+ -- Component instances
+ XCMP1 : entity work.clock(ideal)
+ generic map(
+ period => 10us
+ )
+ port map(
+ CLK_OUT => clk_100k
+ );
+ XCMP2 : entity work.clock(ideal)
+ generic map(
+ period => 150us
+ )
+ port map(
+ CLK_OUT => clk_6K
+ );
+ clk_50Hz : entity work.clock_duty(ideal)
+ generic map(
+ on_time => 20 us,
+ off_time => 19.98 ms
+ )
+ port map(
+ CLOCK_OUT => clk_50
+ );
+end rc_clk;
+--
+
+-- This model counts the number of input clock transitions and outputs
+-- a '1' when this number equals the value of the user-defined constant 'count'
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity bit_cnt is
+ generic (
+ count : integer -- User-defined value to count up to
+ );
+port
+(
+ bit_in : in std_logic ;
+ clk : in std_logic ;
+ dly_out : out std_logic
+);
+end bit_cnt;
+
+architecture behavioral of bit_cnt is
+begin
+ serial_clock : process is
+ begin
+ wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
+ FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
+ wait until clk'event AND (clk = '1' OR clk = 'H');
+ END LOOP ;
+ dly_out <= '1'; -- After count is reached, set output high
+ wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
+ dly_out <= '0'; -- Reset output to '0' on next clock input
+ end process serial_clock;
+end;
+--
+
+--//////////////////////////////////////////////////////////////////
+-- NOTE: This is an intermediate file for HDL inspection only.
+-- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach1.sdg.
+-- Generated by sde2hdl version 16.1.0.2
+--//////////////////////////////////////////////////////////////////
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+
+ENTITY state_mach1 IS
+ PORT (
+ a2d_eoc : IN std_logic;
+ clk_50 : IN std_logic;
+ clk_100k : IN std_logic;
+ clk_6k : IN std_logic;
+ ser_done : IN std_logic;
+ ch_sel : OUT std_logic;
+ frm_gen : OUT std_logic;
+ a2d_oe : OUT std_logic;
+ a2d_start : OUT std_logic;
+ p2s_oe : OUT std_logic;
+ p2s_load : OUT std_logic;
+ parity_oe : OUT std_logic;
+ ser_cnt : OUT std_logic;
+ p2s_clr : OUT std_logic);
+
+END state_mach1;
+
+ARCHITECTURE state_diagram OF state_mach1 IS
+
+ ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+ TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
+ , load, ad_ch2, delay);
+ SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
+
+ SIGNAL FB_frm_gen : std_logic;
+ SIGNAL FB_p2s_load : std_logic;
+ SIGNAL FB_ch_sel : std_logic;
+
+BEGIN
+ frm_gen <= FB_frm_gen ;
+ p2s_load <= FB_p2s_load ;
+ ch_sel <= FB_ch_sel ;
+
+sm1:
+ PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel)
+ BEGIN
+
+ CASE CS_state_mach1_sm1 IS
+ WHEN V_begin =>
+ FB_frm_gen <= ('1');
+ a2d_start <= ('0');
+ a2d_oe <= ('0');
+ FB_p2s_load <= ('0');
+ p2s_clr <= ('0');
+ p2s_oe <= ('0');
+ FB_ch_sel <= ('0');
+ parity_oe <= ('0');
+ ser_cnt <= ('0');
+
+ IF ((FB_frm_gen = '1')) THEN
+ NS_state_mach1_sm1 <= frm_rd;
+ ELSE
+ NS_state_mach1_sm1 <= V_begin;
+ END IF;
+
+ WHEN frm_rd =>
+ FB_p2s_load <= ('1');
+
+ IF ((FB_p2s_load = '1')) THEN
+ NS_state_mach1_sm1 <= ser_oe;
+ ELSE
+ NS_state_mach1_sm1 <= frm_rd;
+ END IF;
+
+ WHEN ser_oe =>
+ p2s_oe <= ('1');
+ FB_frm_gen <= ('0');
+ FB_p2s_load <= ('0');
+ ser_cnt <= ('1');
+
+ IF ((ser_done = '1')) THEN
+ NS_state_mach1_sm1 <= ch1;
+ ELSE
+ NS_state_mach1_sm1 <= ser_oe;
+ END IF;
+
+ WHEN ch1 =>
+ p2s_oe <= ('0');
+ FB_ch_sel <= ('0');
+ a2d_start <= ('1');
+ ser_cnt <= ('0');
+
+ IF ((a2d_eoc = '1')) THEN
+ NS_state_mach1_sm1 <= data_en;
+ ELSE
+ NS_state_mach1_sm1 <= ch1;
+ END IF;
+
+ WHEN data_en =>
+ a2d_start <= ('0');
+ a2d_oe <= ('1');
+ parity_oe <= ('1');
+ NS_state_mach1_sm1 <= load;
+
+ WHEN tdm_oe =>
+ a2d_oe <= ('0');
+ parity_oe <= ('0');
+ p2s_oe <= ('1');
+ FB_p2s_load <= ('0');
+ ser_cnt <= ('1');
+
+ IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
+ NS_state_mach1_sm1 <= ch2;
+ ELSE
+ NS_state_mach1_sm1 <= tdm_oe;
+ END IF;
+
+ WHEN ch2 =>
+ p2s_oe <= ('0');
+ ser_cnt <= ('0');
+ FB_ch_sel <= ('1');
+ NS_state_mach1_sm1 <= delay;
+
+ WHEN load =>
+ FB_p2s_load <= ('1');
+ NS_state_mach1_sm1 <= tdm_oe;
+
+ WHEN ad_ch2 =>
+ a2d_start <= ('1');
+
+ IF ((a2d_eoc = '1')) THEN
+ NS_state_mach1_sm1 <= data_en;
+ ELSE
+ NS_state_mach1_sm1 <= ad_ch2;
+ END IF;
+
+ WHEN delay =>
+ NS_state_mach1_sm1 <= ad_ch2;
+
+ END CASE;
+
+ END PROCESS;
+
+sm1_CTL:
+ PROCESS (clk_100k, clk_50)
+ BEGIN
+
+ IF (clk_100k'event AND clk_100k='1') THEN
+ IF (clk_50= '1' ) THEN
+ CS_state_mach1_sm1 <= V_begin;
+ ELSE
+ CS_state_mach1_sm1 <= NS_state_mach1_sm1;
+ END IF;
+ END IF;
+
+ END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt is
+ port(
+ a2d_eoc : in std_logic;
+ clk_50 : in std_logic;
+ clk_100k : in std_logic;
+ clk_6k : in std_logic;
+ p2s_load : out std_logic;
+ p2s_oe : out std_logic;
+ parity_oe : out std_logic;
+ a2d_start : out std_logic;
+ a2d_oe : out std_logic;
+ frm_gen : out std_logic;
+ ch_sel : out std_logic;
+ p2s_clr : out std_logic
+ );
+end sm_cnt;
+
+architecture sm_cnt of sm_cnt is
+ -- Component declarations
+ -- Signal declarations
+ signal ser_done : std_logic;
+ signal serial_cnt : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ bit_cnt1 : entity work.bit_cnt(behavioral)
+ generic map(
+ count => 15
+ )
+ port map(
+ bit_in => serial_cnt,
+ clk => clk_6k,
+ dly_out => ser_done
+ );
+ state_mach16 : entity work.state_mach1
+ port map(
+ ser_cnt => serial_cnt,
+ ch_sel => ch_sel,
+ frm_gen => frm_gen,
+ a2d_oe => a2d_oe,
+ a2d_start => a2d_start,
+ parity_oe => parity_oe,
+ p2s_oe => p2s_oe,
+ p2s_load => p2s_load,
+ p2s_clr => p2s_clr,
+ clk_6k => clk_6k,
+ clk_100k => clk_100k,
+ clk_50 => clk_50,
+ a2d_eoc => a2d_eoc,
+ ser_done => ser_done
+ );
+end sm_cnt;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+-- Analog to Digital Converter (Successive Aproximation Register) model with sar architecture (a2d_nbit.vhd)
+--DESCRIPTION:
+--
+--This is a VHDL-AMS model of a simple analog to digital converter. The model
+--describes the general behavior of A/D converters for system level design and
+--verification.
+--The format of the digital output is binary coding.
+--
+--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
+--
+
+-- Use IEEE natures and packages
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity a2d_nbit is
+ generic (
+ Vmax: REAL := 5.0 ; -- ADC's maximum range
+ Nbits: INTEGER := 10 ; -- number bits in ADC's output
+ delay: TIME := 10 us -- ADC's conversion time
+ );
+
+port (
+ signal start: in std_logic ; -- Start signal
+ signal clk: in std_logic ; -- Strobe clock
+ signal oe: in std_logic ; -- Output enable
+ terminal ain: ELECTRICAL ; -- ADC's analog input terminal
+ signal eoc: out std_logic := '0' ; -- End Of Conversion pin
+ signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
+end entity a2d_nbit;
+
+architecture sar of a2d_nbit is
+
+ type states is (input, convert, output) ; -- Three states of A2D Conversion
+ constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
+ quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
+
+begin
+
+ sa_adc: process
+
+ variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
+ variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
+ variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
+ variable status: states := input ; -- Begin with "input" CASE
+ variable bit_cnt: integer := Nbits -1 ;
+
+ begin
+ CASE status is
+ when input => -- Read input voltages when start goes high
+ wait on start until start = '1' or start = 'H' ;
+ thresh := Vmax ;
+ Vtmp := Vin ;
+ eoc <= '0' ;
+ status := convert ; -- Go to convert state
+ when convert => -- Begin successive approximation conversion
+ thresh := thresh / 2.0 ; -- Get value of MSB
+ wait on clk until clk = '1' OR clk = 'H';
+ if Vtmp > thresh then
+ dtmp(bit_cnt) := '1' ;
+ Vtmp := Vtmp - thresh ;
+ else
+ dtmp(bit_cnt) := '0' ;
+ end if ;
+ bit_cnt := bit_cnt - 1 ;
+ if (bit_cnt + 1) < 1 then
+ status := output ; -- Go to output state
+ end if;
+ when output => -- Wait for output enable, then put data on output pins
+ eoc <= '1' after delay ;
+ wait on oe until oe = '1' OR oe = 'H' ;
+ FOR i in bit_range DOWNTO 0 LOOP
+ dout(i) <= dtmp(i) ;
+ END LOOP ;
+ wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
+ FOR i in bit_range DOWNTO 0 LOOP
+ dout <= "ZZZZZZZZZZ" ;
+ END LOOP ;
+ bit_cnt := bit_range ;
+ status := input ; -- Set up for next conversion
+ END CASE ;
+ end process sa_adc ;
+
+ Iin == 0.0 ; -- Ideal input draws no current
+
+end architecture sar ;
+--
+
+-- Parallel input/serial output shift register
+-- With 4 trailing zeros
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity shift_reg is
+generic ( td : time := 0 ns);
+
+port
+(
+ bus_in : in std_logic_vector ; -- Input bus
+ clk : in std_logic ; -- Shift clock
+ oe : in std_logic ; -- Output enable
+ ser_out : out std_logic := '0'; -- Output port
+ load : in std_logic ; -- Parallel input load
+ clr : in std_logic -- Clear register
+);
+
+end entity shift_reg;
+
+architecture behavioral of shift_reg is
+begin
+
+control_proc : process
+ VARIABLE bit_val : std_logic_vector(11 downto 0); -- Default 12-bit input
+ begin
+
+ IF (clr = '1' OR clr = 'H') then
+ bit_val := "000000000000"; -- Set all input bits to zero
+ ELSE
+ wait until load'event AND (load = '1' OR load = 'H');
+ FOR i IN bus_in'high DOWNTO bus_in'low LOOP
+ bit_val(i) := bus_in(i) ; -- Transfer input data to variable
+ END LOOP ;
+ END IF;
+
+ wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
+ FOR i IN bit_val'high DOWNTO bit_val'low LOOP
+ wait until clk'event AND (clk = '1' OR clk = 'H');
+ ser_out <= bit_val(i) ;
+ END LOOP ;
+
+ FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros
+ wait until clk'event AND (clk = '1' OR clk = 'H');
+ ser_out <= '0';
+ END LOOP;
+
+END process;
+
+end architecture behavioral;
+--
+
+-- This model generates a 12-bit data frame synchronization code
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_gen is
+port
+(
+ oe : in std_logic := '0';
+ sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
+
+end entity frame_gen;
+
+architecture simple of frame_gen is
+begin
+ enbl: PROCESS
+ BEGIN
+ WAIT ON OE;
+ IF OE = '1' THEN
+ sync_out <= "010101010101"; -- Sync code
+ ELSE
+ sync_out <= "ZZZZZZZZZZZZ";
+ END IF;
+ END PROCESS;
+end architecture simple;
+--
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input XOR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY xor2 IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ in1, in2 : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY xor2;
+
+ARCHITECTURE ideal OF xor2 IS
+BEGIN
+ output <= in1 XOR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- level_set_tri.vhd
+-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
+-- If OE = '0' set output to high impedance
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set_tri IS
+
+ GENERIC (
+ logic_val : std_logic := 'Z');
+
+ PORT (
+ OE : IN std_logic;
+ level : OUT std_logic := 'Z');
+
+END ENTITY level_set_tri;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set_tri IS
+BEGIN
+ oe_ctl: PROCESS
+ BEGIN
+ WAIT ON OE;
+ IF OE = '1' THEN
+ level <= logic_val;
+ ELSE
+ level <= 'Z';
+ END IF;
+ END PROCESS;
+
+END ARCHITECTURE ideal;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Simple Tri-state Buffer with delay time
+-- If OE = 1, output = input after delay
+-- If OE /= 1, output = Z after delay
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY buffer_tri IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ input : IN std_logic;
+ OE : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY buffer_tri;
+
+ARCHITECTURE ideal OF buffer_tri IS
+BEGIN
+ oe_ctl: PROCESS
+ BEGIN
+ WAIT ON OE, input;
+ IF OE = '1' THEN
+ output <= input AFTER delay;
+ ELSE
+ output <= 'Z' AFTER delay;
+ END IF;
+ END PROCESS;
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- ideal one bit D/A converter
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY d2a_bit IS
+ GENERIC (vlow : real :=0.0; -- output high voltage
+ vhigh : real :=5.0); -- output low voltage
+ PORT (D : IN std_logic; -- digital (std_logic) intout
+ TERMINAL A : electrical); -- analog (electrical) output
+END ENTITY d2a_bit;
+
+ARCHITECTURE ideal OF d2a_bit IS
+ QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
+ SIGNAL vin : real := 0.0;
+
+ BEGIN
+ vin <= vhigh WHEN D = '1' ELSE vlow;
+ -- Use 'RAMP for discontinuous signal
+ vout == vin'RAMP(1.0e-9);
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_gen is
+ port(
+ parity : in std_logic_vector(1 to 10);
+ oe : in std_logic;
+ parity_out : out std_logic_vector(0 to 11)
+ );
+end parity_gen;
+
+architecture parity_gen of parity_gen is
+ -- Component declarations
+ -- Signal declarations
+ terminal par_bit_gen_a : electrical;
+ signal XSIG010002 : std_logic;
+ signal XSIG010003 : std_logic;
+ signal XSIG010004 : std_logic;
+ signal XSIG010005 : std_logic;
+ signal XSIG010006 : std_logic;
+ signal XSIG010007 : std_logic;
+ signal XSIG010008 : std_logic;
+ signal XSIG010009 : std_logic;
+ signal XSIG010098 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ XCMP1 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(1),
+ in2 => parity(2),
+ output => XSIG010002
+ );
+ XCMP2 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(3),
+ in2 => parity(4),
+ output => XSIG010003
+ );
+ XCMP3 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(5),
+ in2 => parity(6),
+ output => XSIG010004
+ );
+ XCMP4 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(7),
+ in2 => parity(8),
+ output => XSIG010005
+ );
+ XCMP5 : entity work.xor2(ideal)
+ port map(
+ in1 => parity(9),
+ in2 => parity(10),
+ output => XSIG010008
+ );
+ XCMP6 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010002,
+ in2 => XSIG010003,
+ output => XSIG010006
+ );
+ XCMP7 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010004,
+ in2 => XSIG010005,
+ output => XSIG010007
+ );
+ XCMP8 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010006,
+ in2 => XSIG010007,
+ output => XSIG010009
+ );
+ XCMP9 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010009,
+ in2 => XSIG010008,
+ output => XSIG010098
+ );
+ XCMP18 : entity work.level_set_tri(ideal)
+ generic map(
+ logic_val => '1'
+ )
+ port map(
+ level => parity_out(11),
+ oe => oe
+ );
+ XCMP19 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(1),
+ output => parity_out(1),
+ oe => oe
+ );
+ XCMP20 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(2),
+ output => parity_out(2),
+ oe => oe
+ );
+ XCMP21 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(3),
+ output => parity_out(3),
+ oe => oe
+ );
+ XCMP22 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(4),
+ output => parity_out(4),
+ oe => oe
+ );
+ XCMP23 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(5),
+ output => parity_out(5),
+ oe => oe
+ );
+ XCMP24 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(6),
+ output => parity_out(6),
+ oe => oe
+ );
+ XCMP25 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(7),
+ output => parity_out(7),
+ oe => oe
+ );
+ XCMP26 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(8),
+ output => parity_out(8),
+ oe => oe
+ );
+ XCMP27 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(9),
+ output => parity_out(9),
+ oe => oe
+ );
+ XCMP28 : entity work.buffer_tri(ideal)
+ port map(
+ input => parity(10),
+ output => parity_out(10),
+ oe => oe
+ );
+ XCMP29 : entity work.buffer_tri(ideal)
+ port map(
+ input => XSIG010098,
+ output => parity_out(0),
+ oe => oe
+ );
+ XCMP30 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010098,
+ A => par_bit_gen_a
+ );
+end parity_gen;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tdm_encoder is
+ port(
+ clk : in std_logic;
+ p2s_oe : in std_logic;
+ p2s_load : in std_logic;
+ frm_gen : in std_logic;
+ parity_oe : in std_logic;
+ tdm_out : out std_logic;
+ p2s_clr : in std_logic;
+ a2d_data : in std_logic_vector(1 to 10)
+ );
+end tdm_encoder;
+
+architecture tdm_encoder of tdm_encoder is
+ -- Component declarations
+ -- Signal declarations
+ signal sync_par : std_logic_vector(0 to 11);
+begin
+ -- Signal assignments
+ -- Component instances
+ p2s1 : entity work.shift_reg(behavioral)
+ port map(
+ bus_in => sync_par,
+ clk => clk,
+ oe => p2s_oe,
+ ser_out => tdm_out,
+ load => p2s_load,
+ clr => p2s_clr
+ );
+ sync_gen1 : entity work.frame_gen(simple)
+ port map(
+ oe => frm_gen,
+ sync_out => sync_par
+ );
+ par_gen1 : entity work.parity_gen
+ port map(
+ parity => a2d_data,
+ parity_out => sync_par,
+ oe => parity_oe
+ );
+end tdm_encoder;
+--
+
+-- Manchester Encoder
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY menc_rsc IS
+
+ port ( dig_in : in STD_LOGIC; -- digital input
+ clk : in STD_LOGIC; -- TX internal clock
+ reset: in STD_LOGIC; -- not reset
+-- bit_out : inout real); -- real output
+ bit_out : out std_logic); -- real output
+
+END ENTITY menc_rsc;
+
+ARCHITECTURE bhv OF menc_rsc IS
+
+-- signal bhigh:real:= 1.0; -- bit encoding
+-- signal blow:real:= -1.0; -- bit encoding
+-- signal bnormal:real:=0.0; -- bit encoding
+ signal bit1:STD_LOGIC;
+ signal bhigh:std_logic:= '1'; -- bit encoding
+ signal blow:std_logic:= '0'; -- bit encoding
+
+begin
+
+-- proc1: process (dig_in, clk, bit1,bhigh,blow,bnormal)
+ proc1: process (dig_in, clk, bit1,bhigh,blow)
+ begin
+
+ if (reset = '1') then
+ bit1 <= '0';
+ else
+ bit1 <= dig_in XOR clk; -- manchester encoding
+ end if;
+
+ if (bit1 = '1') then
+ bit_out <= bhigh;
+ else
+ bit_out <= blow;
+-- elsif bit1 = '0' then
+-- bit_out <= blow;
+-- else
+-- bit_out <= bnormal;
+ end if;
+
+ end process;
+
+end architecture bhv;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Digitize_Encode_Man is
+ port(
+ tdm_out : out std_logic;
+ terminal ch1_in : electrical;
+ terminal ch2_in : electrical
+ );
+end Digitize_Encode_Man;
+
+architecture Digitize_Encode_Man of Digitize_Encode_Man is
+ -- Component declarations
+ -- Signal declarations
+ terminal a2d_ana_in : electrical;
+ signal ch_bus : std_logic_vector(1 to 10);
+ signal clk_6K : std_logic;
+ signal dig_in : std_logic;
+ signal frm_gen_ctl : std_logic;
+ signal p2s_clr : std_logic;
+ signal p2s_load : std_logic;
+ signal p2s_oe : std_logic;
+ signal par_oe : std_logic;
+ signal reset : std_logic;
+ signal reset_m : std_logic;
+ signal start_a2d1 : std_logic;
+ signal sw_ctl : std_logic;
+ signal XSIG010091 : std_logic;
+ signal XSIG010190 : std_logic;
+ signal XSIG010196 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ A_SWITCH1 : entity work.switch_dig_2in(ideal)
+ port map(
+ p_in1 => ch1_in,
+ p_out => a2d_ana_in,
+ sw_state => sw_ctl,
+ p_in2 => ch2_in
+ );
+ rc_clk2 : entity work.rc_clk
+ port map(
+ clk_50 => reset,
+ clk_6K => clk_6K,
+ clk_100k => XSIG010190
+ );
+ sm_xmtr1 : entity work.sm_cnt
+ port map(
+ clk_100k => XSIG010190,
+ a2d_start => start_a2d1,
+ a2d_eoc => XSIG010091,
+ p2s_oe => p2s_oe,
+ p2s_load => p2s_load,
+ ch_sel => sw_ctl,
+ frm_gen => frm_gen_ctl,
+ parity_oe => par_oe,
+ a2d_oe => XSIG010196,
+ clk_50 => reset,
+ clk_6k => clk_6K,
+ p2s_clr => p2s_clr
+ );
+ a2d1 : entity work.a2d_nbit(sar)
+ generic map(
+ Vmax => 4.8
+ )
+ port map(
+ dout => ch_bus,
+ ain => a2d_ana_in,
+ clk => XSIG010190,
+ start => start_a2d1,
+ eoc => XSIG010091,
+ oe => XSIG010196
+ );
+ tdm_enc1 : entity work.tdm_encoder
+ port map(
+ clk => clk_6K,
+ p2s_oe => p2s_oe,
+ tdm_out => dig_in,
+ p2s_load => p2s_load,
+ a2d_data => ch_bus,
+ frm_gen => frm_gen_ctl,
+ parity_oe => par_oe,
+ p2s_clr => p2s_clr
+ );
+ menc_rsc3 : entity work.menc_rsc(bhv)
+ port map(
+ dig_in => dig_in,
+ clk => clk_6K,
+ reset => reset_m,
+ bit_out => tdm_out
+ );
+ XCMP90 : entity work.clock_duty(ideal)
+ generic map(
+ off_time => 19.98 sec
+ )
+ port map(
+ CLOCK_OUT => reset_m
+ );
+end Digitize_Encode_Man;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input AND gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY and2 IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ in1, in2 : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY and2;
+
+ARCHITECTURE ideal OF and2 IS
+BEGIN
+ output <= in1 AND in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- D Flip Flop with reset (negative edge triggered)
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY d_latch_n_edge_rst IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ data, clk : IN std_logic;
+ q : OUT std_logic := '0';
+ qn : OUT std_logic := '1';
+ rst : IN std_logic := '0'); -- reset
+
+END ENTITY d_latch_n_edge_rst ;
+
+ARCHITECTURE behav OF d_latch_n_edge_rst IS
+BEGIN
+
+ data_in : PROCESS(clk, rst) IS
+
+ BEGIN
+ IF clk = '0' AND clk'event AND rst /= '1' THEN
+ q <= data AFTER delay;
+ qn <= NOT data AFTER delay;
+ ELSIF rst = '1' THEN
+ q <= '0';
+ qn <= '1';
+ END IF;
+
+ END PROCESS data_in; -- End of process data_in
+
+END ARCHITECTURE behav;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity counter_12 is
+ port(
+ cnt : out std_logic_vector(0 to 11);
+ reset : in std_logic;
+ enable : in std_logic;
+ clk : in std_logic
+ );
+end counter_12;
+
+architecture counter_12 of counter_12 is
+ -- Component declarations
+ -- Signal declarations
+ signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
+ signal XSIG010078 : std_logic;
+ signal XSIG010081 : std_logic;
+ signal XSIG010083 : std_logic;
+ signal XSIG010085 : std_logic;
+ signal XSIG010087 : std_logic;
+ signal XSIG010101 : std_logic;
+ signal XSIG010102 : std_logic;
+ signal XSIG010103 : std_logic;
+ signal XSIG010104 : std_logic;
+ signal XSIG010115 : std_logic;
+ signal XSIG010116 : std_logic;
+ signal XSIG010117 : std_logic;
+ signal XSIG010132 : std_logic;
+begin
+ -- Signal assignments
+ cnt(0) <= cdb2vhdl_tmp_1(0);
+ cnt(1) <= cdb2vhdl_tmp_1(1);
+ cnt(2) <= cdb2vhdl_tmp_1(2);
+ cnt(3) <= cdb2vhdl_tmp_1(3);
+ cnt(4) <= cdb2vhdl_tmp_1(4);
+ cnt(5) <= cdb2vhdl_tmp_1(5);
+ cnt(6) <= cdb2vhdl_tmp_1(6);
+ cnt(7) <= cdb2vhdl_tmp_1(7);
+ cnt(8) <= cdb2vhdl_tmp_1(8);
+ cnt(9) <= cdb2vhdl_tmp_1(9);
+ cnt(10) <= cdb2vhdl_tmp_1(10);
+ cnt(11) <= cdb2vhdl_tmp_1(11);
+ -- Component instances
+ XCMP92 : entity work.and2(ideal)
+ port map(
+ in1 => clk,
+ in2 => enable,
+ output => XSIG010132
+ );
+ XCMP93 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => XSIG010132,
+ DATA => XSIG010078,
+ QN => XSIG010078,
+ Q => cdb2vhdl_tmp_1(0),
+ RST => reset
+ );
+ XCMP94 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(0),
+ DATA => XSIG010081,
+ QN => XSIG010081,
+ Q => cdb2vhdl_tmp_1(1),
+ RST => reset
+ );
+ XCMP95 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(1),
+ DATA => XSIG010083,
+ QN => XSIG010083,
+ Q => cdb2vhdl_tmp_1(2),
+ RST => reset
+ );
+ XCMP96 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(2),
+ DATA => XSIG010085,
+ QN => XSIG010085,
+ Q => cdb2vhdl_tmp_1(3),
+ RST => reset
+ );
+ XCMP97 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(3),
+ DATA => XSIG010087,
+ QN => XSIG010087,
+ Q => cdb2vhdl_tmp_1(4),
+ RST => reset
+
+ );
+ XCMP98 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(4),
+ DATA => XSIG010101,
+ QN => XSIG010101,
+ Q => cdb2vhdl_tmp_1(5),
+ RST => reset
+ );
+ XCMP99 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(5),
+ DATA => XSIG010102,
+ QN => XSIG010102,
+ Q => cdb2vhdl_tmp_1(6),
+ RST => reset
+ );
+ XCMP100 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(6),
+ DATA => XSIG010103,
+ QN => XSIG010103,
+ Q => cdb2vhdl_tmp_1(7),
+ RST => reset
+ );
+ XCMP101 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(7),
+ DATA => XSIG010104,
+ QN => XSIG010104,
+ Q => cdb2vhdl_tmp_1(8),
+ RST => reset
+ );
+ XCMP102 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(8),
+ DATA => XSIG010115,
+ QN => XSIG010115,
+ Q => cdb2vhdl_tmp_1(9),
+ RST => reset
+ );
+ XCMP103 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(9),
+ DATA => XSIG010116,
+ QN => XSIG010116,
+ Q => cdb2vhdl_tmp_1(10),
+ RST => reset
+ );
+ XCMP104 : entity work.d_latch_n_edge_rst(behav)
+ port map(
+ CLK => cdb2vhdl_tmp_1(10),
+ DATA => XSIG010117,
+ QN => XSIG010117,
+ Q => cdb2vhdl_tmp_1(11),
+ RST => reset
+ );
+end counter_12;
+--
+
+-- 12-bit digital comparator model
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity dig_cmp is
+port
+(
+ eq : out std_logic := '0';
+ in1 : in std_logic_vector (0 to 11);
+ in2 : in std_logic_vector (0 to 11);
+ latch_in1 : in std_logic := '0'; -- Currently unused
+ latch_in2 : in std_logic := '0';
+ cmp : in std_logic := '0';
+ clk : in std_logic
+ );
+
+end entity dig_cmp ;
+
+architecture simple of dig_cmp is
+
+begin
+
+ compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
+ variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
+ BEGIN
+ if latch_in2 = '1' then -- in2 data is latched and stored
+ in2_hold := in2;
+ end if;
+ if cmp = '1' then
+ if in1 = in2_hold then -- latched in2 checked against current in1
+ eq <= '0';
+ else eq <= '1';
+ end if;
+ end if;
+ END PROCESS;
+end architecture simple;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical Resistor Model
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY resistor IS
+
+-- Initialize parameters
+ GENERIC (
+ res : RESISTANCE); -- resistance (no initial value)
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL p1, p2 : ELECTRICAL);
+
+END ENTITY resistor;
+
+-- Ideal Architecture (V = I*R)
+ARCHITECTURE ideal OF resistor IS
+
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH p1 TO p2;
+
+BEGIN
+
+-- Characteristic equations
+ v == i*res;
+
+END ARCHITECTURE ideal;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Digital clock with 50% duty cycle and enable pin
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock_en IS
+ GENERIC (
+ pw : time); -- Clock pulse width
+
+ PORT (
+ enable : IN std_logic ;
+ clock_out : INOUT std_logic := '0');
+
+END ENTITY clock_en;
+
+ARCHITECTURE ideal OF clock_en IS
+
+BEGIN
+
+-- clock process
+ process (clock_out, enable) is
+ begin
+ if clock_out = '0' AND enable = '1' THEN
+ clock_out <= '1' after pw, '0' after 2*pw;
+ end if;
+ end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- Set/reset flip flop
+-- When S goes high, Q is set high until reset
+-- When R goes high, Q is set low until set
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sr_ff is
+port
+(
+ S : in std_logic ;
+ R : in std_logic ;
+ Q : out std_logic
+);
+
+end sr_ff ;
+
+architecture simple of sr_ff is
+begin
+
+ set_reset: PROCESS(S, R) IS
+
+ BEGIN
+-- assert S='1' nand R='1' -- Warning if both inputs are high
+-- report "S and R are both active. Use with caution"
+-- severity warning;
+ if S'event AND S = '1' then
+ Q <= '1';
+ end if;
+ if R'event AND R = '1' then
+ Q <= '0';
+ end if;
+ END PROCESS set_reset;
+
+end;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Inverter
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY inverter IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ input : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY inverter;
+
+ARCHITECTURE ideal OF inverter IS
+BEGIN
+ output <= NOT input AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+--//////////////////////////////////////////////////////////////////
+-- NOTE: This is an intermediate file for HDL inspection only.
+-- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach_rcvr.sdg.
+-- Generated by sde2hdl version 16.1.0.2
+--//////////////////////////////////////////////////////////////////
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+
+ENTITY state_mach_rcvr IS
+ PORT (
+ clk_50 : IN std_logic;
+ clk_100k : IN std_logic;
+ ser_done : IN std_logic;
+ par_det : IN std_logic;
+ frm_det : IN std_logic;
+ clk_6k : IN std_logic;
+ start_pulse : IN std_logic;
+ dly_done : IN std_logic;
+ s2p_rst : OUT std_logic;
+ s2p_en : OUT std_logic;
+ cnt1_en : OUT std_logic;
+ cnt1_rst : OUT std_logic;
+ cmp1_ltch1 : OUT std_logic;
+ cmp1_ltch2 : OUT std_logic;
+ cnt2_en : OUT std_logic;
+ cnt2_rst : OUT std_logic;
+ cmp2_ltch1 : OUT std_logic;
+ cmp2_ltch2 : OUT std_logic;
+ da_latch : OUT std_logic;
+ ser_cnt : OUT std_logic;
+ dly_cnt : OUT std_logic;
+ par_oe : OUT std_logic);
+
+END state_mach_rcvr;
+
+ARCHITECTURE state_diagram OF state_mach_rcvr IS
+
+ ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+ TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
+ , s_bit, par1, par2);
+ SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
+
+
+BEGIN
+
+sm1:
+ PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det)
+ BEGIN
+
+ CASE CS_state_mach_rcvr_sm1 IS
+ WHEN V_begin =>
+ cnt1_en <= ('0');
+ cnt1_rst <= ('1');
+ cmp1_ltch1 <= ('0');
+ cmp1_ltch2 <= ('0');
+ cnt2_en <= ('0');
+ cnt2_rst <= ('1');
+ cmp2_ltch1 <= ('0');
+ cmp2_ltch2 <= ('0');
+ s2p_en <= ('1');
+ s2p_rst <= ('0');
+ da_latch <= ('0');
+ ser_cnt <= ('0');
+ dly_cnt <= ('0');
+ par_oe <= ('0');
+
+ IF ((frm_det = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= s_bit;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= V_begin;
+ END IF;
+
+ WHEN cnt =>
+ ser_cnt <= ('1');
+ cnt1_rst <= ('0');
+ cnt2_rst <= ('0');
+
+ IF ((ser_done = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= par1;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= cnt;
+ END IF;
+
+ WHEN ch1 =>
+ cmp1_ltch2 <= ('1');
+ ser_cnt <= ('0');
+ dly_cnt <= ('1');
+
+ IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
+ NS_state_mach_rcvr_sm1 <= rst1;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= ch1;
+ END IF;
+
+ WHEN rst1 =>
+ cmp1_ltch2 <= ('0');
+ ser_cnt <= ('1');
+ dly_cnt <= ('0');
+ par_oe <= ('0');
+
+ IF ((ser_done = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= par2;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= rst1;
+ END IF;
+
+ WHEN ch2 =>
+ cmp2_ltch2 <= ('1');
+ ser_cnt <= ('0');
+ da_latch <= ('1');
+ NS_state_mach_rcvr_sm1 <= rst2;
+
+ WHEN rst2 =>
+ cmp2_ltch2 <= ('0');
+ s2p_en <= ('0');
+ par_oe <= ('0');
+ da_latch <= ('0');
+ NS_state_mach_rcvr_sm1 <= cnt_cmp;
+
+ WHEN cnt_cmp =>
+ cnt1_en <= ('1');
+ cmp1_ltch1 <= ('1');
+ cnt2_en <= ('1');
+ cmp2_ltch1 <= ('1');
+ NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+ WHEN rst_cnt =>
+ cnt1_en <= ('0');
+ cmp1_ltch1 <= ('0');
+ cnt2_en <= ('0');
+ cmp2_ltch1 <= ('0');
+ NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+ WHEN s_bit =>
+
+ IF ((start_pulse = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= cnt;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= s_bit;
+ END IF;
+
+ WHEN par1 =>
+ par_oe <= ('1');
+
+ IF ((par_det = '0')) THEN
+ NS_state_mach_rcvr_sm1 <= ch1;
+ ELSIF ((par_det = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= rst1;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= par1;
+ END IF;
+
+ WHEN par2 =>
+ par_oe <= ('1');
+
+ IF ((par_det = '0')) THEN
+ NS_state_mach_rcvr_sm1 <= ch2;
+ ELSIF ((par_det = '1')) THEN
+ NS_state_mach_rcvr_sm1 <= rst2;
+ ELSE
+ NS_state_mach_rcvr_sm1 <= par2;
+ END IF;
+
+ END CASE;
+
+ END PROCESS;
+
+sm1_CTL:
+ PROCESS (clk_100k, clk_50)
+ BEGIN
+
+ IF (clk_100k'event AND clk_100k='1') THEN
+ IF (clk_50= '1' ) THEN
+ CS_state_mach_rcvr_sm1 <= V_begin;
+ ELSE
+ CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
+ END IF;
+ END IF;
+
+ END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt_rcvr is
+ port(
+ cmp1_ltch1 : out std_logic;
+ cmp2_ltch1 : out std_logic;
+ s2p_en : out std_logic;
+ s2p_rst : out std_logic;
+ frm_det : in std_logic;
+ par_det : in std_logic;
+ clk_100k : in std_logic;
+ clk_6k : in std_logic;
+ clk_50 : in std_logic;
+ start_pulse : in std_logic;
+ cnt1_en : out std_logic;
+ cnt1_rst : out std_logic;
+ cmp1_ltch2 : out std_logic;
+ cnt2_en : out std_logic;
+ cnt2_rst : out std_logic;
+ cmp2_ltch2 : out std_logic;
+ da_latch : out std_logic;
+ par_oe : out std_logic
+ );
+end sm_cnt_rcvr;
+
+architecture sm_cnt_rcvr of sm_cnt_rcvr is
+ -- Component declarations
+ -- Signal declarations
+ terminal dly_cnt_a : electrical;
+ terminal dly_done_a : electrical;
+ terminal ser_cnt_a : electrical;
+ terminal ser_done_a : electrical;
+ signal XSIG010001 : std_logic;
+ signal XSIG010002 : std_logic;
+ signal XSIG010145 : std_logic;
+ signal XSIG010146 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ XCMP1 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010001,
+ A => ser_cnt_a
+ );
+ XCMP2 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010002,
+ A => ser_done_a
+ );
+ bit_cnt3 : entity work.bit_cnt(behavioral)
+ generic map(
+ count => 2
+ )
+ port map(
+ bit_in => XSIG010145,
+ clk => clk_6k,
+ dly_out => XSIG010146
+ );
+ bit_cnt4 : entity work.bit_cnt(behavioral)
+ generic map(
+ count => 10
+ )
+ port map(
+ bit_in => XSIG010001,
+ clk => clk_6k,
+ dly_out => XSIG010002
+ );
+ XCMP8 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010145,
+ A => dly_cnt_a
+ );
+ XCMP9 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010146,
+ A => dly_done_a
+ );
+ state_mach_rcvr8 : entity work.state_mach_rcvr
+ port map(
+ clk_100k => clk_100k,
+ clk_50 => clk_50,
+ s2p_rst => s2p_rst,
+ s2p_en => s2p_en,
+ cnt1_en => cnt1_en,
+ cnt1_rst => cnt1_rst,
+ cmp1_ltch1 => cmp1_ltch1,
+ cmp1_ltch2 => cmp1_ltch2,
+ cnt2_en => cnt2_en,
+ cnt2_rst => cnt2_rst,
+ cmp2_ltch1 => cmp2_ltch1,
+ cmp2_ltch2 => cmp2_ltch2,
+ da_latch => da_latch,
+ ser_cnt => XSIG010001,
+ ser_done => XSIG010002,
+ par_det => par_det,
+ frm_det => frm_det,
+ clk_6k => clk_6k,
+ start_pulse => start_pulse,
+ dly_done => XSIG010146,
+ dly_cnt => XSIG010145,
+ par_oe => par_oe
+ );
+end sm_cnt_rcvr;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- level_set.vhd
+-- Set digital output "level" with parameter "logic_val" (default is '1')
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set IS
+
+ GENERIC (
+ logic_val : std_logic := '1');
+
+ PORT (
+ level : OUT std_logic);
+
+END ENTITY level_set;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set IS
+
+BEGIN
+
+ level <= logic_val;
+
+END ARCHITECTURE ideal;
+
+--
+
+-- Serial to parallel data converter
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity ser2par is
+port
+(
+ par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
+ clk : in std_logic ;
+ load_en : in std_logic ;
+ ser_in : in std_logic ;
+ reset : in std_logic
+);
+
+begin
+
+end ser2par;
+
+architecture a1 of ser2par is
+BEGIN
+ sr_sm: PROCESS (load_en, clk, reset, ser_in)
+ BEGIN
+ if (reset = '1' and load_en = '1') then
+ par_out <= "000000000000"; -- Reset the parallel data out
+
+ elsif (clk'event and clk = '1') then
+ if (load_en ='1') then
+
+ -- The register will shift when load is enabled
+ -- and will shift at rising edge of clock
+
+ par_out(0) <= ser_in; -- Input data shifts into bit 0
+ par_out(1) <= par_out(0);
+ par_out(2) <= par_out(1);
+ par_out(3) <= par_out(2);
+ par_out(4) <= par_out(3);
+ par_out(5) <= par_out(4);
+ par_out(6) <= par_out(5);
+ par_out(7) <= par_out(6);
+ par_out(8) <= par_out(7);
+ par_out(9) <= par_out(8);
+ par_out(10) <= par_out(9);
+ par_out(11) <= par_out(10);
+
+ else
+ -- The otput data will not change
+ -- if load_en is not enabled
+ par_out <= "ZZZZZZZZZZZZ";
+ end if;
+ end if;
+ END PROCESS;
+end;
+--
+
+-- This model ouputs a '1' when a specific bit pattern is encountered
+-- Otherwise, it outputs a zero
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_det is
+port
+(
+ bus_in : in std_logic_vector (0 to 11);
+ clk : in std_logic;
+ frm_bit : out std_logic := '0' -- Initialize output to zero
+ );
+
+end entity frame_det;
+
+architecture simple of frame_det is
+begin
+ enbl: PROCESS (bus_in, clk) -- Sensitivity list
+ BEGIN
+ if bus_in = "010101010101" then -- This is the pre-defined bit pattern
+ if clk'event AND clk = '0' then -- Output updated synchronously
+ frm_bit <= '1';
+ end if;
+ else frm_bit <= '0';
+ end if;
+ END PROCESS;
+end architecture simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_det is
+ port(
+ bus_in : in std_logic_vector(0 to 11);
+ par_bit : out std_logic;
+ oe : in std_logic
+ );
+end parity_det;
+
+architecture parity_det of parity_det is
+ -- Component declarations
+ -- Signal declarations
+ signal cdb2vhdl_tmp_1 : std_logic;
+ terminal par_bit_a : electrical;
+ signal XSIG010010 : std_logic;
+ signal XSIG010011 : std_logic;
+ signal XSIG010012 : std_logic;
+ signal XSIG010013 : std_logic;
+ signal XSIG010014 : std_logic;
+ signal XSIG010015 : std_logic;
+ signal XSIG010016 : std_logic;
+ signal XSIG010017 : std_logic;
+ signal XSIG010019 : std_logic;
+ signal XSIG010057 : std_logic;
+begin
+ -- Signal assignments
+ par_bit <= cdb2vhdl_tmp_1;
+ -- Component instances
+ XCMP1 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(1),
+ in2 => bus_in(2),
+ output => XSIG010010
+ );
+ XCMP2 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(3),
+ in2 => bus_in(4),
+ output => XSIG010011
+ );
+ XCMP3 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(5),
+ in2 => bus_in(6),
+ output => XSIG010012
+ );
+ XCMP4 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(7),
+ in2 => bus_in(8),
+ output => XSIG010013
+ );
+ XCMP5 : entity work.xor2(ideal)
+ port map(
+ in1 => bus_in(9),
+ in2 => bus_in(10),
+ output => XSIG010016
+ );
+ XCMP6 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010010,
+ in2 => XSIG010011,
+ output => XSIG010014
+ );
+ XCMP7 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010012,
+ in2 => XSIG010013,
+ output => XSIG010015
+ );
+ XCMP8 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010014,
+ in2 => XSIG010015,
+ output => XSIG010017
+ );
+ XCMP9 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010017,
+ in2 => XSIG010016,
+ output => XSIG010019
+ );
+ XCMP10 : entity work.xor2(ideal)
+ port map(
+ in1 => XSIG010019,
+ in2 => bus_in(0),
+ output => XSIG010057
+ );
+ XCMP11 : entity work.d2a_bit(ideal)
+ port map(
+ D => cdb2vhdl_tmp_1,
+ A => par_bit_a
+ );
+ XCMP12 : entity work.and2(ideal)
+ port map(
+ in1 => oe,
+ in2 => XSIG010057,
+ output => cdb2vhdl_tmp_1
+ );
+end parity_det;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY d2a_nbit IS
+
+ GENERIC (
+ vmax : real := 5.0; -- High output
+ vmin : real := 0.0; -- Low output
+ high_bit : integer := 9; -- High end of bit range for D/A
+ low_bit : integer := 0); -- Low end of bit range for D/A
+
+ PORT (
+ SIGNAL bus_in : IN STD_LOGIC_VECTOR; -- variable width vector input
+ SIGNAL latch : IN STD_LOGIC;
+ TERMINAL ana_out : electrical); -- analog output
+
+END ENTITY d2a_nbit ;
+
+ARCHITECTURE behavioral OF d2a_nbit IS
+
+ SIGNAL sout : real := 0.0;
+ QUANTITY vout across iout through ana_out TO electrical_ref;
+
+BEGIN -- ARCHITECTURE behavioral
+
+ proc : PROCESS
+
+ VARIABLE v_sum : real; -- Sum of voltage contribution from each bit
+ VARIABLE delt_v : real; -- Represents the voltage value of each bit
+
+ BEGIN
+ WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
+ v_sum := vmin;
+ delt_v := vmax - vmin;
+
+ FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
+ delt_v := delt_v / 2.0;
+ IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
+ v_sum := v_sum + delt_v;
+ END IF;
+ END LOOP;
+
+ sout <= v_sum;
+ END PROCESS;
+
+ vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
+
+END ARCHITECTURE behavioral;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TDM_Demux_dbg is
+ port(
+ s2p_en : in std_logic;
+ tdm_in : in std_logic;
+ clk_6k : in std_logic;
+ s2p_rst : in std_logic;
+ par_det : out std_logic;
+ frm_det : out std_logic;
+ da_latch : in std_logic;
+ par_oe : in std_logic;
+ data_bus : out std_logic_vector(1 to 10);
+ start_bit : out std_logic
+ );
+end TDM_Demux_dbg;
+
+architecture TDM_Demux_dbg of TDM_Demux_dbg is
+ -- Component declarations
+ -- Signal declarations
+ terminal d2a_out : electrical;
+ signal rcvr_bus : std_logic_vector(0 to 11);
+begin
+ -- Signal assignments
+ data_bus(1) <= rcvr_bus(1);
+ data_bus(2) <= rcvr_bus(2);
+ data_bus(3) <= rcvr_bus(3);
+ data_bus(4) <= rcvr_bus(4);
+ data_bus(5) <= rcvr_bus(5);
+ data_bus(6) <= rcvr_bus(6);
+ data_bus(7) <= rcvr_bus(7);
+ data_bus(8) <= rcvr_bus(8);
+ data_bus(9) <= rcvr_bus(9);
+ data_bus(10) <= rcvr_bus(10);
+ start_bit <= rcvr_bus(0);
+ -- Component instances
+ s2p1 : entity work.ser2par(a1)
+ port map(
+ par_out => rcvr_bus,
+ clk => clk_6k,
+ load_en => s2p_en,
+ ser_in => tdm_in,
+ reset => s2p_rst
+ );
+ frm_det1 : entity work.frame_det(simple)
+ port map(
+ bus_in => rcvr_bus,
+ frm_bit => frm_det,
+ clk => clk_6k
+ );
+ par_det1 : entity work.parity_det
+ port map(
+ bus_in => rcvr_bus,
+ par_bit => par_det,
+ oe => par_oe
+ );
+ XCMP113 : entity work.d2a_nbit(behavioral)
+ generic map(
+ low_bit => 1,
+ high_bit => 10,
+ vmax => 4.8
+ )
+ port map(
+ bus_in => rcvr_bus(1 to 10),
+ ana_out => d2a_out,
+ latch => da_latch
+ );
+end TDM_Demux_dbg;
+--
+
+-- Manchester Decoder with clock recovery using 8x referenced clock
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity mdec_rsc is
+-- port ( din: in real; -- real input
+ port ( din: in std_logic; -- real input
+ clk16x: in std_logic; -- 16x referenced clock
+ reset: in std_logic; -- not reset
+ bout: out std_logic := '0'; -- digital output
+ clk_out: inout std_logic := '0'); -- recovered clock
+end entity mdec_rsc;
+
+architecture bhv of mdec_rsc is
+-- signal bhigh:real:= 1.0; -- bit decoding
+-- signal blow:real:= -1.0; -- bit decoding
+-- signal bnormal:real:=0.0; -- bit decoding
+ signal bhigh:std_logic:= '1'; -- bit decoding
+ signal blow:std_logic:= '0'; -- bit decoding
+ signal bout1:std_logic;
+ signal clk_div:std_logic_vector(3 downto 0):="0000"; -- clock counter
+ signal trans:std_logic; -- transisition trigger
+begin
+ -- bit decoding
+ proc1: process (reset,din,clk16x)
+ begin
+ if (reset = '1') then
+ bout1 <= 'X';
+ elsif (clk16x'event and clk16x = '1') then
+ if (din = bhigh) then
+ bout1 <= '1';
+ elsif (din = blow) then
+ bout1 <= '0';
+ else
+ bout1 <= 'X';
+ end if;
+ end if;
+ end process;
+
+ -- clock counter
+ proc2: process (reset, clk16x, clk_div)
+ begin
+
+ if (reset = '1') then
+ clk_div <= "0000";
+ elsif (clk16x'event and clk16x = '1') then
+ clk_div <= clk_div + "0001";
+ end if;
+ end process;
+
+ -- recovered clock
+ -- clk_out <= not clk_div(3);
+ clk_out <= clk_div(3);
+
+ -- transition trigger
+trans <= ((not clk_div(3)) and (not clk_div(2)) and clk_div(1) and clk_div(0)) or
+ (clk_div(3) and clk_div(2) and (not clk_div(1)) and (not clk_div(0)));
+
+ -- Manchester decoder
+ proc3: process (reset, trans, bout1, clk_out, clk16x)
+ begin
+ if (reset = '1') then
+ bout <= '0';
+ elsif (clk16x'event and clk16x = '1') then
+ if (trans = '1') then
+ bout <= bout1 XOR clk_out;
+ end if;
+ end if;
+ end process;
+
+end architecture bhv;
+
+architecture bhv_8 of mdec_rsc is
+-- signal bhigh:real:= 1.0; -- bit decoding
+-- signal blow:real:= -1.0; -- bit decoding
+-- signal bnormal:real:=0.0; -- bit decoding
+ signal bhigh:std_logic:= '1'; -- bit decoding
+ signal blow:std_logic:= '0'; -- bit decoding
+ signal bout1:std_logic;
+ signal clk_div:std_logic_vector(2 downto 0):="000"; -- clock counter
+ signal trans:std_logic; -- transisition trigger
+begin
+ -- bit decoding
+ proc1: process (reset,din,clk16x)
+ begin
+ if (reset = '1') then
+ bout1 <= 'X';
+ elsif (clk16x'event and clk16x = '1') then
+ if (din = bhigh) then
+ bout1 <= '1';
+ elsif (din = blow) then
+ bout1 <= '0';
+ else
+ bout1 <= 'X';
+ end if;
+ end if;
+ end process;
+
+ -- clock counter
+ proc2: process (reset, clk16x, clk_div)
+ begin
+
+ if (reset = '1') then
+ clk_div <= "000";
+ elsif (clk16x'event and clk16x = '1') then
+ clk_div <= clk_div + "001";
+ end if;
+ end process;
+
+ -- recovered clock
+ clk_out <= not clk_div(2);
+
+ -- transition trigger
+ trans <= ((not clk_div(1)) and clk_div(0)) or (clk_div(1) and (not clk_div(0)));
+
+ -- Manchester decoder
+ proc3: process (reset, trans, bout1, clk_out, clk16x)
+ begin
+ if (reset = '1') then
+ bout <= '0';
+ elsif (clk16x'event and clk16x = '1') then
+ if (trans = '1') then
+ bout <= bout1 XOR clk_out;
+ end if;
+ end if;
+ end process;
+
+end architecture bhv_8;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Decode_PW_Man is
+ port(
+ terminal power : electrical;
+ terminal ch1_pw : electrical;
+ terminal ch2_pw : electrical;
+ bit_stream_in : in std_logic
+ );
+end Decode_PW_Man;
+
+architecture Decode_PW_Man of Decode_PW_Man is
+ -- Component declarations
+ -- Signal declarations
+ signal bit_stream_in_mdec : std_logic;
+ signal clk16x : std_logic;
+ signal clk6k : std_logic;
+ signal clk_100k : std_logic;
+ signal cmp_bus : std_logic_vector(0 to 11);
+ signal cnt1 : std_logic_vector(0 to 11);
+ signal cnt2 : std_logic_vector(0 to 11);
+ signal mdec_clk : std_logic;
+ signal mdec_out : std_logic;
+ signal reset : std_logic;
+ signal reset_m : std_logic;
+ signal XSIG010228 : std_logic;
+ signal XSIG010229 : std_logic;
+ signal XSIG010256 : std_logic;
+ signal XSIG010263 : std_logic;
+ signal XSIG010264 : std_logic;
+ signal XSIG010266 : std_logic;
+ signal XSIG010267 : std_logic;
+ signal XSIG010268 : std_logic;
+ signal XSIG010320 : std_logic;
+ signal XSIG010330 : std_logic;
+ signal XSIG010334 : std_logic;
+ signal XSIG010339 : std_logic;
+ signal XSIG010349 : std_logic;
+ signal XSIG010357 : std_logic;
+ signal XSIG010371 : std_logic;
+ signal XSIG010372 : std_logic;
+ signal XSIG010373 : std_logic;
+ signal XSIG010383 : std_logic;
+ signal XSIG010384 : std_logic;
+ signal XSIG010385 : std_logic;
+ signal XSIG010386 : std_logic;
+ signal XSIG010390 : std_logic;
+ signal XSIG010433 : std_logic;
+begin
+ -- Signal assignments
+ bit_stream_in_mdec <= bit_stream_in;
+ -- Component instances
+ cntr1 : entity work.counter_12
+ port map(
+ enable => XSIG010384,
+ cnt => cnt1,
+ reset => XSIG010357,
+ clk => XSIG010433
+ );
+ cntr2 : entity work.counter_12
+ port map(
+ enable => XSIG010349,
+ cnt => cnt2,
+ reset => XSIG010385,
+ clk => XSIG010320
+ );
+ cmp1 : entity work.dig_cmp(simple)
+ port map(
+ in1 => cnt1,
+ eq => XSIG010371,
+ clk => XSIG010433,
+ in2 => cmp_bus,
+ cmp => XSIG010384,
+ latch_in1 => XSIG010256,
+ latch_in2 => XSIG010383
+ );
+ cmp2 : entity work.dig_cmp(simple)
+ port map(
+ in1 => cnt2,
+ eq => XSIG010372,
+ clk => XSIG010320,
+ in2 => cmp_bus,
+ cmp => XSIG010349,
+ latch_in1 => XSIG010263,
+ latch_in2 => XSIG010264
+ );
+ XCMP109 : entity work.resistor(ideal)
+ generic map(
+ res => 1000000.0
+ )
+ port map(
+ p1 => power,
+ p2 => ELECTRICAL_REF
+ );
+ clk_1M2 : entity work.clock_en(ideal)
+ generic map(
+ pw => 500 ns
+ )
+ port map(
+ CLOCK_OUT => XSIG010320,
+ enable => XSIG010349
+ );
+ clk_1M1 : entity work.clock_en(ideal)
+ generic map(
+ pw => 500 ns
+ )
+ port map(
+ CLOCK_OUT => XSIG010433,
+ enable => XSIG010384
+ );
+ XCMP134 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010371,
+ A => ch1_pw
+ );
+ XCMP135 : entity work.d2a_bit(ideal)
+ port map(
+ D => XSIG010372,
+ A => ch2_pw
+ );
+ XCMP137 : entity work.SR_FF(simple)
+ port map(
+ S => XSIG010330,
+ R => XSIG010334,
+ Q => XSIG010349
+ );
+ XCMP138 : entity work.inverter(ideal)
+ port map(
+ input => XSIG010372,
+ output => XSIG010334
+ );
+ XCMP139 : entity work.SR_FF(simple)
+ port map(
+ S => XSIG010373,
+ R => XSIG010339,
+ Q => XSIG010384
+ );
+ XCMP140 : entity work.inverter(ideal)
+ port map(
+ input => XSIG010371,
+ output => XSIG010339
+ );
+ rc_clk2 : entity work.rc_clk
+ port map(
+ clk_50 => reset,
+ clk_6K => clk6k,
+ clk_100k => clk_100k
+ );
+ sm_rcvr1 : entity work.sm_cnt_rcvr
+ port map(
+ cnt1_en => XSIG010373,
+ cmp1_ltch1 => XSIG010256,
+ cnt2_rst => XSIG010385,
+ clk_100k => clk_100k,
+ cnt1_rst => XSIG010357,
+ cnt2_en => XSIG010330,
+ cmp2_ltch1 => XSIG010263,
+ frm_det => XSIG010229,
+ par_det => XSIG010228,
+ s2p_en => XSIG010266,
+ s2p_rst => XSIG010267,
+ clk_6k => mdec_clk,
+ clk_50 => reset,
+ da_latch => XSIG010268,
+ cmp1_ltch2 => XSIG010383,
+ cmp2_ltch2 => XSIG010264,
+ start_pulse => XSIG010390,
+ par_oe => XSIG010386
+ );
+ XCMP155 : entity work.level_set(ideal)
+ generic map(
+ logic_val => '0'
+ )
+ port map(
+ level => cmp_bus(11)
+ );
+ XCMP157 : entity work.TDM_Demux_dbg
+ port map(
+ data_bus => cmp_bus(0 to 9),
+ tdm_in => mdec_out,
+ clk_6k => mdec_clk,
+ s2p_en => XSIG010266,
+ s2p_rst => XSIG010267,
+ da_latch => XSIG010268,
+ frm_det => XSIG010229,
+ par_det => XSIG010228,
+ par_oe => XSIG010386,
+ start_bit => XSIG010390
+ );
+ XCMP172 : entity work.level_set(ideal)
+ generic map(
+ logic_val => '1'
+ )
+ port map(
+ level => cmp_bus(10)
+ );
+ clock1 : entity work.clock(ideal)
+ generic map(
+ period => 9.375us
+ )
+ port map(
+ CLK_OUT => clk16x
+ );
+ mdec_rsc7 : entity work.mdec_rsc(bhv)
+ port map(
+ din => bit_stream_in_mdec,
+ clk16x => clk16x,
+ reset => reset_m,
+ bout => mdec_out,
+ clk_out => mdec_clk
+ );
+ XCMP181 : entity work.clock_duty(ideal)
+ generic map(
+ off_time => 19.98 sec
+ )
+ port map(
+ CLOCK_OUT => reset_m
+ );
+end Decode_PW_Man;
+--
+
+-------------------------------------------------------------------------------
+-- Second Order Lowpass filter
+--
+-- Transfer Function:
+--
+-- w1*w2
+-- H(s) = k * ----------------
+-- (s + w1)(s + w2)
+--
+-- DC Gain = k
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lpf_2_e is
+ generic (
+ k: real := 1.0; -- Gain multiplier
+ f1: real := 10.0; -- First break frequency (pole)
+ f2: real := 100.0); -- Second break frequency (pole)
+ port ( terminal input: electrical;
+ terminal output: electrical);
+end entity lpf_2_e;
+
+architecture simple of lpf_2_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ quantity vin_temp : real;
+ constant w1 : real := f1*math_2_pi;
+ constant w2 : real := f2*math_2_pi;
+-- constant num : real := k;
+ constant num : real_vector := (0 => w1*w2*k); -- 0=> is needed to give
+ -- index when only a single
+ -- element is used.
+ constant den : real_vector := (w1*w2, w1+w2, 1.0);
+begin
+ vin_temp == vin; -- intermediate variable (vin) req'd for now
+ vout == vin_temp'ltf(num, den);
+end architecture simple;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- ideal one bit A/D converter
+
+LIBRARY IEEE;
+USE IEEE.math_real.ALL;
+USE IEEE.std_logic_1164.ALL;
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY a2d_bit IS
+
+ GENERIC (
+ thres : real := 2.5); -- Threshold to determine logic output
+
+ PORT (
+ TERMINAL a : electrical; -- analog input
+ SIGNAL d : OUT std_logic); -- digital (std_logic) output
+
+END ENTITY a2d_bit;
+
+
+ARCHITECTURE ideal OF a2d_bit IS
+
+ QUANTITY vin ACROSS a;
+
+ BEGIN -- threshold
+-- Process needed to detect threshold crossing and assign output (d)
+ PROCESS (vin'ABOVE(thres)) IS
+ BEGIN -- PROCESS
+ IF vin'ABOVE(thres) THEN
+ d <= '1';
+ ELSE
+ d <= '0';
+ END IF;
+ END PROCESS;
+
+END ideal;
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input OR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY or2 IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ in1, in2 : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY or2;
+
+ARCHITECTURE ideal OF or2 IS
+BEGIN
+ output <= in1 OR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pw2ana is
+ port(
+ terminal ana_out : electrical;
+ terminal pw_in : electrical
+ );
+end pw2ana;
+
+architecture pw2ana of pw2ana is
+ -- Component declarations
+ -- Signal declarations
+ signal bus_servo : std_logic_vector(0 to 11);
+ signal XSIG010008 : std_logic;
+ signal XSIG010013 : std_logic;
+ signal XSIG010019 : std_logic;
+ signal XSIG010020 : std_logic;
+ signal XSIG010021 : std_logic;
+ signal XSIG010022 : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ counter_rudder : entity work.counter_12
+ port map(
+ enable => XSIG010022,
+ cnt => bus_servo,
+ reset => XSIG010021,
+ clk => XSIG010008
+ );
+ XCMP3 : entity work.a2d_bit(ideal)
+ port map(
+ D => XSIG010022,
+ A => pw_in
+ );
+ clk_en_rudder : entity work.clock_en(ideal)
+ generic map(
+ pw => 500ns
+ )
+ port map(
+ CLOCK_OUT => XSIG010008,
+ enable => XSIG010022
+ );
+ XCMP5 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => XSIG010022,
+ output => XSIG010013
+ );
+ XCMP8 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => XSIG010020,
+ output => XSIG010021
+ );
+ XCMP9 : entity work.inverter(ideal)
+ generic map(
+ delay => 2us
+ )
+ port map(
+ input => XSIG010022,
+ output => XSIG010019
+ );
+ or_rudder : entity work.or2(ideal)
+ port map(
+ in1 => XSIG010022,
+ in2 => XSIG010019,
+ output => XSIG010020
+ );
+ XCMP11 : entity work.d2a_nbit(behavioral)
+ generic map(
+ vmax => 4.8,
+ high_bit => 9,
+ low_bit => 0
+ )
+ port map(
+ bus_in => bus_servo,
+ ana_out => ana_out,
+ latch => XSIG010013
+ );
+end pw2ana;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : v_pulse.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/07/09
+-------------------------------------------------------------------------------
+-- Description: Voltage Pulse Source
+-- Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
+-- time. Uses time2real function.
+-- Pulsewidth no longer includes
+-- rise and fall times.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_pulse is
+
+ generic (
+ initial : voltage := 0.0; -- initial value [Volts]
+ pulse : voltage; -- pulsed value [Volts]
+ ti2p : time := 1ns; -- initial to pulse [Sec]
+ tp2i : time := 1ns; -- pulse to initial [Sec]
+ delay : time := 0ms; -- delay time [Sec]
+ width : time; -- duration of pulse [Sec]
+ period : time; -- period [Sec]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port (
+ terminal pos, neg : electrical);
+
+end entity v_pulse;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_pulse is
+
+-- Declare Through and Across Branch Quantities
+ quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+-- Signal used in CreateEvent process below
+ signal pulse_signal : voltage := initial;
+
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+-- Note: these lines gave an error during simulation. Had to use a
+-- function call instead.
+-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
+-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
+
+-- Function to convert numbers of type TIME to type REAL
+ function time2real(tt : time) return real is
+ begin
+ return time'pos(tt) * 1.0e-15;
+ end time2real;
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+ constant ri2p : real := time2real(ti2p);
+ constant rp2i : real := time2real(tp2i);
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+ v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
+ else
+ v == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+-- purpose: Create events to define pulse shape
+-- type : combinational
+-- inputs :
+-- outputs: pulse_signal
+CreateEvent : process
+begin
+ wait for delay;
+ loop
+ pulse_signal <= pulse;
+ wait for (width + ti2p);
+ pulse_signal <= initial;
+ wait for (period - width - ti2p);
+ end loop;
+end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.math_real.all;
+package pwl_functions is
+
+-- This function returns the incremental value to the next element in a real vector
+ function next_increment(x : in real; xdata : in real_vector )
+ return real;
+ function interpolate (x,y2,y1,x2,x1 : in real)
+ return real;
+ function extrapolate (x,y2,y1,x2,x1 : in real)
+ return real;
+ function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector )
+ return real;
+end package pwl_functions;
+
+package body pwl_functions is
+ function next_increment(x : in real; xdata : in real_vector)
+ return real is
+ variable i : integer;
+ begin
+ i := 0;
+ while i <= xdata'right loop
+ if x >= xdata(i) - 6.0e-15 then -- The value 6.0e-15 envelopes round-off error
+ -- of real-to-time conversion in calling model
+ i := i + 1;
+ else
+ return xdata(i) - xdata(i - 1);
+ end if;
+ end loop;
+ return 1.0; -- Returns a "large number" relative to expected High-Speed time scale
+ end function next_increment;
+
+ function interpolate (x,y2,y1,x2,x1 : in real)
+ return real is
+ variable m, yvalue : real;
+ begin
+ assert (x1 /= x2)
+ report "interpolate: x1 cannot be equal to x2"
+ severity error;
+ assert (x >= x1) and (x <= x2)
+ report "interpolate: x must be between x1 and x2, inclusively "
+ severity error;
+
+ m := (y2 - y1)/(x2 - x1);
+ yvalue := y1 + m*(x - x1);
+ return yvalue;
+ end function interpolate;
+
+ function extrapolate (x,y2,y1,x2,x1 : in real)
+ return real is
+ variable m, yvalue : real;
+ begin
+ assert (x1 /= x2)
+ report "extrapolate: x1 cannot be equal to x2"
+ severity error;
+ assert (x <= x1) or (x >= x2)
+ report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
+ severity warning;
+
+ m := (y2 - y1)/(x2 - x1);
+ yvalue := y1 + m*(x - x1);
+ return yvalue;
+ end function extrapolate;
+
+ -- Created a new pwl_dim1_flat function that returns a constant
+ -- value of ydata(0) if x < xdata(0), or ydata(ydata'right) if x > xdata(xdata'right)
+
+ function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector )
+ return real is
+ variable xvalue, yvalue, m : real;
+ variable start, fin, mid: integer;
+ begin
+ if x >= xdata(xdata'right) then
+ yvalue := ydata(ydata'right);
+ return yvalue;
+ end if;
+ if x <= xdata(0) then
+ yvalue := ydata(0);
+ return yvalue;
+ end if;
+ start:=0;
+ fin:=xdata'right;
+-- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive.
+-- so fin==n-1 in C terms (where n is the size of the array).
+ while start <=fin loop
+ mid:=(start+fin)/2;
+ if xdata(mid) < x
+ then start:=mid+1;
+ else fin:=mid-1;
+ end if;
+ end loop;
+
+ if xdata(mid) > x
+ then mid:=mid-1;
+ end if;
+ yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));
+
+ return yvalue;
+ end function pwl_dim1_flat;
+end package body pwl_functions;
+
+-- Not sure the sync_tdata process is necessary. Requires the tdata set contain
+-- a larger value than the actual simulation time.
+
+-- Piece-wise linear voltage source model
+
+library IEEE; use IEEE.std_logic_1164.all;
+Library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+use work.pwl_functions.all;
+
+entity v_pwl is
+generic (
+ vdata : real_vector; -- v-pulse data
+ tdata : real_vector -- time-data for v-pulse
+ );
+
+port (
+ terminal pos, neg : electrical
+ );
+end entity v_pwl;
+
+architecture ideal of v_pwl is
+
+QUANTITY v across i through pos TO neg;
+signal tick : std_logic := '0'; -- Sync signal for tdata "tracking"
+
+begin
+
+sync_tdata: process is
+variable next_tick_delay : real := 0.0; -- Time increment to the next time-point in tdata
+begin
+ wait until domain = time_domain;
+ loop
+ next_tick_delay := next_increment(NOW,tdata);
+ tick <= (not tick) after (integer(next_tick_delay * 1.0e15) * 1 fs);
+ wait on tick;
+ end loop;
+end process sync_tdata;
+
+break on tick; -- Forces analog solution point at all tdata time-points
+ v == pwl_dim1_flat(NOW, tdata, vdata);
+end architecture ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity plane_pos_src is
+ port(
+ terminal plane_pos : electrical;
+ terminal rudder_fb : electrical
+ );
+end plane_pos_src;
+
+architecture plane_pos_src of plane_pos_src is
+ -- Component declarations
+ -- Signal declarations
+ terminal flight_deviation : electrical;
+ terminal plane_sum_out : electrical;
+ terminal wind : electrical;
+ terminal wind_neg : electrical;
+ terminal XSIG010020 : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ sum1 : entity work.sum2_e(simple)
+ generic map(
+ k1 => 1.0
+ )
+ port map(
+ in1 => wind,
+ in2 => rudder_fb,
+ output => plane_sum_out
+ );
+ dir_out : entity work.gain_e(simple)
+ generic map(
+ k => -1.0
+ )
+ port map(
+ input => plane_sum_out,
+ output => plane_pos
+ );
+ wind_neg_gain : entity work.gain_e(simple)
+ generic map(
+ k => -1.0
+ )
+ port map(
+ input => wind,
+ output => wind_neg
+ );
+ sum2 : entity work.sum2_e(simple)
+ generic map(
+ k2 => 1.89,
+ k1 => 1.0
+ )
+ port map(
+ in1 => wind,
+ in2 => rudder_fb,
+ output => flight_deviation
+ );
+ R2 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => ELECTRICAL_REF,
+ p2 => XSIG010020
+ );
+ v3 : entity work.v_pulse(ideal)
+ generic map(
+ period => 3 sec,
+ width => 100 ms,
+ delay => 100 ms,
+ tp2i => 1 sec,
+ ti2p => 1 sec,
+ pulse => -4.8,
+ initial => 0.0
+ )
+ port map(
+ pos => XSIG010020,
+ neg => ELECTRICAL_REF
+ );
+ PWL_Wind : entity work.v_pwl(ideal)
+ generic map(
+ tdata => (0.0,100.0e-3,110.0e-3,500.0e-3,510.0e-3,800.0e-3, 810.0e-3),
+ vdata => (0.0,0.0,-2.4,-2.4,-4.7,-4.7,0.0)
+ )
+ port map(
+ pos => wind,
+ neg => ELECTRICAL_REF
+ );
+end plane_pos_src;
+--
+
+-------------------------------------------------------------------------------
+-- Integrator
+--
+-- Transfer Function:
+--
+-- k
+-- H(s) = ---------
+-- s
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity integ_1_e is
+ generic (
+ k: real := 1.0; -- Gain
+-- init: real := real'low); -- Initial value of output
+ init: real := 0.0); -- Initial value of output
+ port (terminal input: electrical;
+ terminal output: electrical);
+end entity integ_1_e;
+
+architecture simple of integ_1_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ quantity vin_temp : real;
+begin
+ vin_temp == vin;
+-- IF domain = QUIESCENT_DOMAIN AND init /= real'low USE
+ IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE
+ vout == init;
+ ELSE
+ vout == k*vin_temp'INTEG;
+
+ END USE;
+
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- First Order Lowpass filter
+--
+-- Transfer Function:
+--
+-- w1
+-- H(s) = k * -----------
+-- s + w1
+--
+-- DC Gain = k
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lpf_1_e is
+ generic (
+ fp : real; -- pole freq in Hertz
+ gain : real := 1.0); -- filter gain
+
+ port ( terminal input: electrical;
+ terminal output: electrical);
+end entity lpf_1_e;
+
+architecture simple of lpf_1_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ constant wp : real := math_2_pi*fp;
+ constant num : real_vector := (0 => wp*gain); -- 0=> is needed to give
+ -- index when only a single
+ -- element is used.
+ constant den : real_vector := (wp, 1.0);
+ quantity vin_temp : real;
+
+begin
+ vin_temp == vin; -- intermediate variable (vin) req'd for now
+ vout == vin_temp'ltf(num, den);
+end architecture simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity hcl is
+ port(
+ terminal output : electrical;
+ terminal plane_pos : electrical
+ );
+end hcl;
+
+architecture hcl of hcl is
+ -- Component declarations
+ -- Signal declarations
+ terminal hcl_err_in : electrical;
+ terminal heading : electrical;
+ terminal XSIG010001 : electrical;
+ terminal XSIG010002 : electrical;
+ terminal XSIG010003 : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ prop_gain : entity work.gain_e(simple)
+ generic map(
+ k => 1.0
+ )
+ port map(
+ input => hcl_err_in,
+ output => XSIG010002
+ );
+ integ : entity work.integ_1_e(simple)
+ generic map(
+ init => 0.0,
+ k => 0.1
+ )
+ port map(
+ input => hcl_err_in,
+ output => XSIG010003
+ );
+ lowpass : entity work.lpf_1_e(simple)
+ generic map(
+ fp => 4.0
+ )
+ port map(
+ input => XSIG010001,
+ output => output
+ );
+ sum2 : entity work.sum2_e(simple)
+ port map(
+ in1 => XSIG010002,
+ in2 => XSIG010003,
+ output => XSIG010001
+ );
+ set_src : entity work.v_constant(ideal)
+ generic map(
+ level => 0.0
+ )
+ port map(
+ pos => heading,
+ neg => ELECTRICAL_REF
+ );
+ sum1 : entity work.sum2_e(simple)
+ port map(
+ in1 => heading,
+ in2 => plane_pos,
+ output => hcl_err_in
+ );
+end hcl;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CS5_HCL is
+end tb_CS5_HCL;
+
+architecture TB_CS5_HCL of tb_CS5_HCL is
+ -- Component declarations
+ -- Signal declarations
+ signal bitstream1 : std_logic;
+ signal bitstream2 : std_logic;
+ terminal ch1_in : electrical;
+ terminal ch1_pw_out : electrical;
+ terminal ch2_in : electrical;
+ terminal ch2_pw_out : electrical;
+ terminal gear_hrn_out : translational;
+ terminal gear_in : rotational_v;
+ terminal gear_out : rotational;
+ terminal mtr_in : electrical;
+ terminal plane_dir : electrical;
+ terminal prop_in : electrical;
+ terminal rot2v_out : electrical;
+ terminal rudder : rotational;
+ terminal rudder_fb : electrical;
+ terminal rudder_hrn_in : translational;
+ terminal servo_fltr_in : electrical;
+ terminal servo_in : electrical;
+ terminal XSIG010018 : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ rudder_servo1 : entity work.rudder_servo
+ port map(
+ servo_out => mtr_in,
+ servo_in => servo_in,
+ pos_fb => rot2v_out
+ );
+ gear1 : entity work.gear_rv_r(ideal)
+ generic map(
+ ratio => 0.01
+ )
+ port map(
+ rotv1 => gear_in,
+ rot2 => gear_out
+ );
+ potentiometer1 : entity work.rot2v(bhv)
+ generic map(
+ k => 1.0
+ )
+ port map(
+ output => rot2v_out,
+ input => gear_out
+ );
+ gear_horn : entity work.horn_r2t(bhv)
+ port map(
+ theta => gear_out,
+ pos => gear_hrn_out
+ );
+ rudder_horn : entity work.horn_t2r(bhv)
+ port map(
+ theta => rudder,
+ pos => rudder_hrn_in
+ );
+ motor1 : entity work.DC_Motor(basic)
+ generic map(
+ j => 168.0e-9,
+ d => 5.63e-6,
+ l => 2.03e-3,
+ kt => 3.43e-3,
+ r_wind => 2.2
+ )
+ port map(
+ p1 => mtr_in,
+ p2 => ELECTRICAL_REF,
+ shaft_rotv => gear_in
+ );
+ stop1 : entity work.stop_r(ideal)
+ generic map(
+ ang_min => -1.05,
+ ang_max => 1.05,
+ k_stop => 1.0e6,
+ damp_stop => 1.0e2
+ )
+ port map(
+ ang1 => gear_out,
+ ang2 => ROTATIONAL_REF
+ );
+ \linkage\ : entity work.tran_linkage(a1)
+ port map(
+ p2 => rudder_hrn_in,
+ p1 => gear_hrn_out
+ );
+ rudder_1 : entity work.rudder(bhv)
+ generic map(
+ k => 0.2
+ )
+ port map(
+ rot => rudder
+ );
+ XCMP6 : entity work.v_constant(ideal)
+ generic map(
+ level => 5.0
+ )
+ port map(
+ pos => XSIG010018,
+ neg => ELECTRICAL_REF
+ );
+ Throttle : entity work.stick(ideal)
+ generic map(
+ freq => 1.0,
+ amplitude => 2.397,
+ phase => 0.0,
+ offset => 2.397
+ )
+ port map(
+ v_out => ch1_in
+ );
+ rf_tx_rx : entity work.rf_xmtr_rcvr(behavioral)
+ port map(
+ tdm_in => bitstream1,
+ tdm_out => bitstream2
+ );
+ Digitize_Encode1 : entity work.Digitize_Encode_Man
+ port map(
+ ch2_in => ch2_in,
+ ch1_in => ch1_in,
+ tdm_out => bitstream1
+ );
+ Decode_PW_Man3 : entity work.Decode_PW_Man
+ port map(
+ bit_stream_in => bitstream2,
+ ch2_pw => ch2_pw_out,
+ ch1_pw => ch1_pw_out,
+ power => XSIG010018
+ );
+ lpf2 : entity work.lpf_2_e(simple)
+ generic map(
+ f1 => 10.0,
+ f2 => 10.0
+ )
+ port map(
+ input => servo_fltr_in,
+ output => servo_in
+ );
+ pw2ana_throttle : entity work.pw2ana
+ port map(
+ ana_out => prop_in,
+ pw_in => ch1_pw_out
+ );
+ pw2ana_rudder : entity work.pw2ana
+ port map(
+ ana_out => servo_fltr_in,
+ pw_in => ch2_pw_out
+ );
+ rot2v_rudder : entity work.rot2v(bhv)
+ generic map(
+ k => 4.57
+ )
+ port map(
+ output => rudder_fb,
+ input => rudder
+ );
+ plane11 : entity work.plane_pos_src
+ port map(
+ plane_pos => plane_dir,
+ rudder_fb => rudder_fb
+ );
+ hcl_1 : entity work.hcl
+ port map(
+ output => ch2_in,
+ plane_pos => plane_dir
+ );
+end TB_CS5_HCL;
+--
+
+
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd
new file mode 100644
index 000000000..67db1b9f2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd
@@ -0,0 +1,990 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : DC_Motor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+ generic (
+ r_wind : resistance; -- Motor winding resistance [Ohm]
+ kt : real; -- Torque coefficient [N*m/Amp]
+ l : inductance; -- Winding inductance [Henrys]
+ d : real; -- Damping coefficient [N*m/(rad/sec)]
+ j : mmoment_i); -- Moment of inertia [kg*meter**2]
+
+ port (terminal p1, p2 : electrical;
+ terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
+-- T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+ quantity v across i through p1 to p2;
+ quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+ torq == -1.0*kt*i + d*w + j*w'dot;
+ v == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Constant Voltage Source (Includes Frequency Domain settings)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY v_constant IS
+
+-- Initialize parameters
+ GENERIC (
+ level : VOLTAGE; -- Constant voltage value (V)
+ ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
+ ac_phase : real := 0.0); -- AC phase (degrees)
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL pos, neg : ELECTRICAL);
+
+END ENTITY v_constant;
+
+-- Ideal Architecture (I = constant)
+ARCHITECTURE ideal OF v_constant IS
+
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH pos TO neg;
+-- Declare quantity in frequency domain for AC analysis
+ QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+
+ IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
+ v == level;
+ ELSE
+ v == ac_spec; -- used for Frequency (AC) analysis
+ END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-- C:\Rehan\Cs5\design_definition\hdl\vhdl\switch_dig_log.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity switch_dig_log is
+generic
+(
+ trans_time : real := 1.0e-9;
+ r_closed : resistance := 1.0e-3;
+ r_open : resistance := 1.0e6
+);
+port
+(
+ terminal p1 : electrical ;
+ sw_state : in std_logic ;
+ terminal p2 : electrical
+);
+
+begin
+
+end switch_dig_log ;
+
+-----------------------------------------------------------------------------------------
+architecture linear of switch_dig_log is
+ signal r_sig : resistance := r_open; -- create internal signal for CreateState process
+ quantity v across i through p1 to p2;
+ quantity r : resistance;
+
+begin
+ -- purpose: Detect Switch state and assign resistance value to r_sig
+ -- type : combinational
+ -- inputs : sw_state
+ -- outputs: r_sig
+ DetectState: process (sw_state)
+ begin -- process DetectState
+ if (sw_state'event and sw_state = '0') then
+ r_sig <= r_open;
+ elsif (sw_state'event and sw_state = '1') then
+ r_sig <= r_closed;
+ end if;
+ end process DetectState;
+
+-- Characteristic equations
+ r == r_sig'ramp(trans_time, trans_time);
+ v == r*i;
+end architecture linear;
+
+-------------------------------------------------------------------------------------------
+architecture log of switch_dig_log is
+ constant log10_r_open : real := log10(r_open);
+ constant log10_r_closed : real := log10(r_closed);
+ signal log10_r_sig : resistance := log10_r_open; -- create internal signal for CreateState process
+ quantity v across i through p1 to p2;
+ quantity r : resistance;
+ quantity log10_r : real;
+
+begin
+ -- purpose: Detect Switch state and assign resistance value to r_sig
+ -- type : combinational
+ -- inputs : sw_state
+ -- outputs: r_sig
+ DetectState: process (sw_state)
+ begin -- process DetectState
+ if (sw_state'event and sw_state = '0') then
+ log10_r_sig <= log10_r_open;
+ elsif (sw_state'event and sw_state = '1') then
+ log10_r_sig <= log10_r_closed;
+ end if;
+ end process DetectState;
+
+-- Characteristic equations
+ log10_r == log10_r_sig'ramp(trans_time, trans_time);
+ r == 10**log10_r;
+ v == r*i;
+end architecture log;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : opamp.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: 3-pin OpAmp model with behavioral architecture
+-- Uses Q'LTF function to define open-loop response
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity opamp is
+-- Initialize parameters
+ generic (rin : resistance := 1.0e6; -- Input resistance [Ohms]
+ rout : resistance := 100.0; -- Output resistance (Ohms]
+ avol : real := 100.0e3; -- Open loop gain
+ f_0dB : real := 1.0e6 -- Unity Gain Frequency [Hz]
+ );
+-- Define ports as electrical terminals
+ port (
+ terminal in_pos, in_neg, output : electrical);
+
+end entity opamp;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Characteristics modeled:
+-- 1. Open loop gain
+-- 2. Frequency characteristics (single pole response)
+-- 3. Input and output resistance
+-- Uses Q'Ltf function to create open loop gain and roll off
+-------------------------------------------------------------------------------
+architecture basic of opamp is
+ -- Declare constants
+ constant f_3db : real := f_0db / avol; -- -3dB frequency
+ constant w_3dB : real := math_2_pi*f_3dB; -- -3dB freq in radians
+ -- Numerator and denominator for Q'LTF function
+ constant num : real_vector := (0 => avol);
+ constant den : real_vector := (1.0, 1.0/w_3dB);
+ -- Declare input and output quantities
+ quantity v_in across i_in through in_pos to in_neg;
+ quantity v_out across i_out through output;
+
+begin -- ARCHITECTURE basic
+
+ i_in == v_in / rin; -- input current
+ v_out == v_in'ltf(num, den) + i_out*rout; -- output voltage
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical Resistor Model
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY resistor IS
+
+-- Initialize parameters
+ GENERIC (
+ res : RESISTANCE); -- resistance (no initial value)
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL p1, p2 : ELECTRICAL);
+
+END ENTITY resistor;
+
+-- Ideal Architecture (V = I*R)
+ARCHITECTURE ideal OF resistor IS
+
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH p1 TO p2;
+
+BEGIN
+
+-- Characteristic equations
+ v == i*res;
+
+END ARCHITECTURE ideal;
+
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : comparator_d.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/08/03
+-- Last update: 2001/08/03
+-------------------------------------------------------------------------------
+-- Description: Voltage comparator with digital output
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/08/03 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use IEEE natures and packages
+library IEEE;
+use ieee.std_logic_1164.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+use IEEE_proposed.ENERGY_SYSTEMS.all;
+
+entity comparator_d is
+
+ port (
+ terminal in_pos : electrical;
+ terminal in_neg : electrical;
+ signal output : out std_logic := '1' -- Digital output
+ );
+
+end comparator_d;
+-------------------------------------------------------------------------------
+-- Behavioral architecture
+-------------------------------------------------------------------------------
+architecture behavioral of comparator_d is
+ quantity Vin across in_pos;
+ quantity Vref across in_neg;
+
+begin -- behavioral
+
+ -- purpose: Detect threshold crossing and assign event on output
+ -- type : combinational
+ -- inputs : vin'above(thres)
+ -- outputs: pulse_signal
+ process (Vin'above(Vref)) is
+ begin -- PROCESS
+ if Vin'above(Vref) then
+ output <= '1' after 1us;
+ else
+ output <= '0' after 1us;
+ end if;
+ end process;
+
+end behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : v_pulse.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/07/09
+-------------------------------------------------------------------------------
+-- Description: Voltage Pulse Source
+-- Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
+-- time. Uses time2real function.
+-- Pulsewidth no longer includes
+-- rise and fall times.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_pulse is
+
+ generic (
+ initial : voltage := 0.0; -- initial value [Volts]
+ pulse : voltage; -- pulsed value [Volts]
+ ti2p : time := 1ns; -- initial to pulse [Sec]
+ tp2i : time := 1ns; -- pulse to initial [Sec]
+ delay : time := 0ms; -- delay time [Sec]
+ width : time; -- duration of pulse [Sec]
+ period : time; -- period [Sec]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port (
+ terminal pos, neg : electrical);
+
+end entity v_pulse;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_pulse is
+
+-- Declare Through and Across Branch Quantities
+ quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+-- Signal used in CreateEvent process below
+ signal pulse_signal : voltage := initial;
+
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+-- Note: these lines gave an error during simulation. Had to use a
+-- function call instead.
+-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
+-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
+
+-- Function to convert numbers of type TIME to type REAL
+ function time2real(tt : time) return real is
+ begin
+ return time'pos(tt) * 1.0e-15;
+ end time2real;
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+ constant ri2p : real := time2real(ti2p);
+ constant rp2i : real := time2real(tp2i);
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+ v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
+ else
+ v == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+-- purpose: Create events to define pulse shape
+-- type : combinational
+-- inputs :
+-- outputs: pulse_signal
+CreateEvent : process
+begin
+ wait for delay;
+ loop
+ pulse_signal <= pulse;
+ wait for (width + ti2p);
+ pulse_signal <= initial;
+ wait for (period - width - ti2p);
+ end loop;
+end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pwm_mac is
+ port(
+ terminal inp : electrical;
+ terminal inm : electrical;
+ dig_out : out std_logic
+ );
+end pwm_mac;
+
+architecture pwm_mac of pwm_mac is
+ -- Component declarations
+ -- Signal declarations
+ terminal cmp_in : electrical;
+ terminal plse_in : electrical;
+ terminal XSIG010002 : electrical;
+ terminal XSIG010003 : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ U1 : entity work.opamp(basic)
+ port map(
+ in_neg => XSIG010002,
+ in_pos => inm,
+ output => cmp_in
+ );
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => XSIG010002,
+ p2 => cmp_in
+ );
+ v2 : entity work.v_constant(ideal)
+ generic map(
+ level => 0.0
+ )
+ port map(
+ pos => XSIG010003,
+ neg => ELECTRICAL_REF
+ );
+ R2 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => plse_in,
+ p2 => XSIG010002
+ );
+ R3 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => inp,
+ p2 => XSIG010002
+ );
+ XCMP4 : entity work.comparator_d(behavioral)
+ port map(
+ output => dig_out,
+ in_pos => XSIG010003,
+ in_neg => cmp_in
+ );
+ v9 : entity work.v_pulse(ideal)
+ generic map(
+ initial => -4.7,
+ pulse => 4.7,
+ ti2p => 200 us,
+ tp2i => 200 us,
+ delay => 1 us,
+ width => 1 us,
+ period => 405 us
+ )
+ port map(
+ pos => plse_in,
+ neg => ELECTRICAL_REF
+ );
+end pwm_mac;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : prop_pwl.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Propeller Load (Rotational_V domain)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.math_real.all;
+package pwl_functions is
+function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector )
+ return real;
+function interpolate (x,y2,y1,x2,x1 : in real)
+ return real;
+function extrapolate (x,y2,y1,x2,x1 : in real)
+ return real;
+end package pwl_functions;
+
+package body pwl_functions is
+ function interpolate (x,y2,y1,x2,x1 : in real)
+ return real is
+ variable m, yvalue : real;
+ begin
+ assert (x1 /= x2)
+ report "interpolate: x1 cannot be equal to x2"
+ severity error;
+ assert (x >= x1) and (x <= x2)
+ report "interpolate: x must be between x1 and x2, inclusively "
+ severity error;
+
+ m := (y2 - y1)/(x2 - x1);
+ yvalue := y1 + m*(x - x1);
+ return yvalue;
+ end function interpolate;
+
+ function extrapolate (x,y2,y1,x2,x1 : in real)
+ return real is
+ variable m, yvalue : real;
+ begin
+ assert (x1 /= x2)
+ report "extrapolate: x1 cannot be equal to x2"
+ severity error;
+ assert (x <= x1) or (x >= x2)
+ report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
+ severity warning;
+
+ m := (y2 - y1)/(x2 - x1);
+ yvalue := y1 + m*(x - x1);
+ return yvalue;
+ end function extrapolate;
+
+-- Created a new pwl_dim1_extrap function that returns extrapolated yvalue for "out-of-range" x value.
+
+ function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector )
+ return real is
+ variable xvalue, yvalue, m : real;
+ variable start, fin, mid: integer;
+ begin
+ if x <= xdata(0) then
+ yvalue := extrapolate(x,ydata(1),ydata(0),xdata(1),xdata(0));
+ return yvalue;
+ end if;
+ if x >= xdata(xdata'right) then
+ yvalue := extrapolate(x,ydata(ydata'right),ydata(ydata'right-1),xdata(xdata'right),xdata(xdata'right-1));
+ return yvalue;
+ end if;
+ start:=0;
+ fin:=xdata'right;
+-- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive.
+-- so fin==n-1 in C terms (where n is the size of the array).
+ while start <=fin loop
+ mid:=(start+fin)/2;
+ if xdata(mid) < x
+ then start:=mid+1;
+ else fin:=mid-1;
+ end if;
+ end loop;
+
+ if xdata(mid) > x
+ then mid:=mid-1;
+ end if;
+ yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));
+
+ return yvalue;
+ end function pwl_dim1_extrap;
+end package body pwl_functions;
+
+library IEEE_proposed; use IEEE_proposed.mechanical_systems.all;
+library ieee; use ieee.math_real.all;
+use work.pwl_functions.all;
+
+entity prop_pwl is
+generic (
+ ydata : real_vector; -- torque data
+ xdata : real_vector -- velocity data
+ );
+ port (terminal shaft1 : rotational_v);
+end entity prop_pwl;
+
+architecture ideal of prop_pwl is
+ quantity w across torq through shaft1 to rotational_v_ref;
+begin
+ torq == pwl_dim1_extrap(w, xdata, ydata);
+end architecture ideal;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : diode_pwl.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Diode model with ideal architecture
+-- Currently no Generics due to bug in DV
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
+use IEEE_proposed.energy_systems.all;
+
+ENTITY diode_pwl IS
+ GENERIC (
+ ron : real; -- equivalent series resistance
+ roff : real); -- leakage resistance
+ PORT (
+ TERMINAL p, -- positive pin
+ m : electrical); -- minus pin
+END ENTITY diode_pwl;
+
+ARCHITECTURE simple OF diode_pwl IS
+ QUANTITY v across i through p TO m;
+
+BEGIN -- simple ARCHITECTURE
+ if v'Above(0.0) use
+ i == v/ron;
+ elsif not v'Above(0.0) use
+ i == v/roff;
+ else
+ i == 0.0;
+ end use;
+ break on v'Above(0.0);
+END ARCHITECTURE simple;
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical sinusoidal voltage source (v_sine.vhd)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+
+ENTITY v_sine IS
+
+-- Initialize parameters
+ GENERIC (
+ freq : real; -- frequency, [Hertz]
+ amplitude : real; -- amplitude, [Volt]
+ phase : real := 0.0; -- initial phase, [Degree]
+ offset : real := 0.0; -- DC value, [Volt]
+ df : real := 0.0; -- damping factor, [1/second]
+ ac_mag : real := 1.0; -- AC magnitude, [Volt]
+ ac_phase : real := 0.0); -- AC phase, [Degree]
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL pos, neg : ELECTRICAL);
+
+END ENTITY v_sine;
+
+-- Ideal Architecture
+ARCHITECTURE ideal OF v_sine IS
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH pos TO neg;
+-- Declare Quantity for Phase in radians (calculated below)
+ QUANTITY phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+ QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+-- Convert phase to radians
+ phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+ IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
+ v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+ ELSE
+ v == ac_spec; -- used for Frequency (AC) analysis
+ END USE;
+
+END ARCHITECTURE ideal;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CS5_Prop is
+end tb_CS5_Prop;
+
+architecture TB_CS5_Prop of tb_CS5_Prop is
+ -- Component declarations
+ -- Signal declarations
+ terminal prop : rotational_v;
+ terminal prop_amp_in : electrical;
+ terminal prop_mtr_in : electrical;
+ terminal prop_pwr : electrical;
+ signal pwm_out : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ motor2 : entity work.DC_Motor(basic)
+ generic map(
+ kt => 30.1e-3,
+ l => 40.0e-6,
+ d => 5.63e-12,
+ j => 315.0e-6,
+ r_wind => 0.16
+ )
+ port map(
+ p1 => prop_mtr_in,
+ p2 => ELECTRICAL_REF,
+ shaft_rotv => prop
+ );
+ v4 : entity work.v_constant(ideal)
+ generic map(
+ level => 42.0
+ )
+ port map(
+ pos => prop_pwr,
+ neg => ELECTRICAL_REF
+ );
+ sw2 : entity work.switch_dig_log
+ port map(
+ sw_state => pwm_out,
+ p2 => prop_mtr_in,
+ p1 => prop_pwr
+ );
+ pwm1 : entity work.pwm_mac
+ port map(
+ inp => prop_amp_in,
+ dig_out => pwm_out,
+ inm => ELECTRICAL_REF
+ );
+ XCMP37 : entity work.prop_pwl(ideal)
+ generic map(
+ ydata => (0.233, 0.2865, 0.347, 0.4138, 0.485, 0.563, 0.645, 0.735, 0.830, 0.93, 1.08),
+ xdata => (471.2, 523.6, 576.0, 628.3, 680.7, 733.0, 785.4, 837.7, 890.0, 942.5, 994.8)
+ )
+ port map(
+ shaft1 => prop
+ );
+ D4 : entity work.diode_pwl(simple)
+ generic map(
+ ron => 0.001,
+ roff => 100.0e3
+ )
+ port map(
+ p => ELECTRICAL_REF,
+ m => prop_mtr_in
+ );
+ v8 : entity work.v_sine(ideal)
+ generic map(
+ freq => 1.0,
+ amplitude => 2.3,
+ phase => 0.0,
+ offset => 2.3
+ )
+ port map(
+ pos => prop_amp_in,
+ neg => ELECTRICAL_REF
+ );
+end TB_CS5_Prop;
+--
+
+
+
+
+
+
+
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd
new file mode 100644
index 000000000..c520bf9d5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd
@@ -0,0 +1,1974 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+ generic (k1, k2: real := 1.0); -- Gain multipliers
+ port ( terminal in1, in2: electrical;
+ terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+ QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+ QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+ generic (
+ k: REAL := 1.0); -- Gain multiplier
+ port ( terminal input : electrical;
+ terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+ vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+ generic (
+ limit_high : real := 4.8; -- upper limit
+ limit_low : real := -4.8); -- lower limit
+ port (
+ terminal input: electrical;
+ terminal output: electrical);
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+ constant slope : real := 1.0e-4;
+begin
+ if vin > limit_high use -- Upper limit exceeded, so limit input signal
+ vout == limit_high + slope*(vin - limit_high);
+ elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
+ vout == limit_low + slope*(vin - limit_low);
+ else -- No limit exceeded, so pass input signal as is
+ vout == vin;
+ end use;
+ break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+-- Transfer Function:
+--
+-- (s + w1)
+-- H(s) = k * ----------
+-- (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lead_lag_e is
+ generic (
+ k: real := 1.0; -- Gain multiplier
+ f1: real := 10.0; -- First break frequency (zero)
+ f2: real := 100.0); -- Second break frequency (pole)
+ port ( terminal input: electrical;
+ terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+ QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+ QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+ quantity vin_temp : real;
+ constant w1 : real := f1*math_2_pi;
+ constant w2 : real := f2*math_2_pi;
+ constant num : real_vector := (w1, 1.0);
+ constant den : real_vector := (w2, 1.0);
+begin
+ vin_temp == vin;
+ vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo is
+ port(
+ terminal servo_in : electrical;
+ terminal pos_fb : electrical;
+ terminal servo_out : electrical
+ );
+end rudder_servo;
+
+architecture rudder_servo of rudder_servo is
+ -- Component declarations
+ -- Signal declarations
+ terminal error : electrical;
+ terminal ll_in : electrical;
+ terminal ll_out : electrical;
+ terminal summer_fb : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ summer : entity work.sum2_e(simple)
+ port map(
+ in1 => servo_in,
+ in2 => summer_fb,
+ output => error
+ );
+ forward_gain : entity work.gain_e(simple)
+ generic map(
+ k => 100.0
+ )
+ port map(
+ input => error,
+ output => ll_in
+ );
+ fb_gain : entity work.gain_e(simple)
+ generic map(
+ k => -4.57
+ )
+ port map(
+ input => pos_fb,
+ output => summer_fb
+ );
+ servo_limiter : entity work.limiter_2_e(simple)
+ generic map(
+ limit_high => 4.8,
+ limit_low => -4.8
+ )
+ port map(
+ input => ll_out,
+ output => servo_out
+ );
+ lead_lag : entity work.lead_lag_e(simple)
+ generic map(
+ k => 400.0,
+ f1 => 5.0,
+ f2 => 2000.0
+ )
+ port map(
+ input => ll_in,
+ output => ll_out
+ );
+end rudder_servo;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : gear_rv_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/10/10 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+ generic(
+ ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+ -- Note: can be negative, if shaft polarity changes
+
+ port ( terminal rotv1 : rotational_v;
+ terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+ quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
+ quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+-- w2 == w1*ratio;
+ theta == ratio*w1'integ;
+ torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+
+ generic (
+ k : real := 1.0); -- optional gain
+
+ port (
+ terminal input : rotational; -- input terminal
+ terminal output : electrical); -- output terminal
+
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref; -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+ begin -- bhv
+ v_out == k*rot_in;
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- tran = R*sin(rot)
+--
+-- Where pos = output translational position,
+-- R = horn radius,
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+
+ generic (
+ R : real := 1.0); -- horn radius
+
+ port (
+ terminal theta : ROTATIONAL; -- input angular position port
+ terminal pos : TRANSLATIONAL); -- output translational position port
+
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+ begin -- bhv
+ tran == R*sin(rot); -- Convert angle in to translational out
+ tran_frc == -rot_tq/R; -- Convert torque in to force out
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+-- Transfer Function:
+--
+-- theta = arcsin(pos/R)
+--
+-- Where pos = input translational position,
+-- R = horn radius,
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+
+ generic (
+ R : real := 1.0); -- Rudder horn radius
+
+ port (
+ terminal pos : translational; -- input translational position port
+ terminal theta : rotational); -- output angular position port
+
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+ QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+ QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+ begin -- bhv
+ rot == arcsin(tran/R); -- Convert translational to angle
+ rot_tq == -tran_frc*R; -- Convert force to torque
+
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : DC_Motor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+ generic (
+ r_wind : resistance; -- Motor winding resistance [Ohm]
+ kt : real; -- Torque coefficient [N*m/Amp]
+ l : inductance; -- Winding inductance [Henrys]
+ d : real; -- Damping coefficient [N*m/(rad/sec)]
+ j : mmoment_i); -- Moment of inertia [kg*meter**2]
+
+ port (terminal p1, p2 : electrical;
+ terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
+-- T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+ quantity v across i through p1 to p2;
+ quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+ torq == -1.0*kt*i + d*w + j*w'dot;
+ v == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : stop_r.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+entity stop_r is
+
+ generic (
+ k_stop : real;
+-- ang_max : angle;
+-- ang_min : angle := 0.0;
+ ang_max : real;
+ ang_min : real := 0.0;
+ damp_stop : real := 0.000000001
+ );
+
+ port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+ quantity velocity : velocity;
+ quantity ang across trq through ang1 to ang2;
+
+begin
+
+ velocity == ang'dot;
+
+ if ang'above(ang_max) use
+ trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+ elsif ang'above(ang_min) use
+ trq == 0.0;
+ else
+ trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
+ end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+ terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+ QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+ QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+ pos_2 == pos_1; -- Pass position
+ frc_2 == -frc_1; -- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+-- Transfer Function:
+--
+-- torq = -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+
+ generic (
+ k : real := 1.0; -- Spring constant
+ theta_0 : real := 0.0);
+
+ port (
+ terminal rot : rotational); -- input rotational angle
+
+end entity rudder;
+
+architecture bhv of rudder is
+
+ QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+ begin -- bhv
+
+ torq == k*(theta - theta_0); -- Convert force to torque
+
+end bhv;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity switch_dig_log is
+generic
+(
+ trans_time : real := 1.0e-9;
+ r_closed : resistance := 1.0e-3;
+ r_open : resistance := 1.0e6
+);
+port
+(
+ terminal p1 : electrical ;
+ sw_state : in std_logic ;
+ terminal p2 : electrical
+);
+
+begin
+
+end switch_dig_log ;
+
+-----------------------------------------------------------------------------------------
+architecture linear of switch_dig_log is
+ signal r_sig : resistance := r_open; -- create internal signal for CreateState process
+ quantity v across i through p1 to p2;
+ quantity r : resistance;
+
+begin
+ -- purpose: Detect Switch state and assign resistance value to r_sig
+ -- type : combinational
+ -- inputs : sw_state
+ -- outputs: r_sig
+ DetectState: process (sw_state)
+ begin -- process DetectState
+ if (sw_state'event and sw_state = '0') then
+ r_sig <= r_open;
+ elsif (sw_state'event and sw_state = '1') then
+ r_sig <= r_closed;
+ end if;
+ end process DetectState;
+
+-- Characteristic equations
+ r == r_sig'ramp(trans_time, trans_time);
+ v == r*i;
+end architecture linear;
+
+-------------------------------------------------------------------------------------------
+architecture log of switch_dig_log is
+ constant log10_r_open : real := log10(r_open);
+ constant log10_r_closed : real := log10(r_closed);
+ signal log10_r_sig : resistance := log10_r_open; -- create internal signal for CreateState process
+ quantity v across i through p1 to p2;
+ quantity r : resistance;
+ quantity log10_r : real;
+
+begin
+ -- purpose: Detect Switch state and assign resistance value to r_sig
+ -- type : combinational
+ -- inputs : sw_state
+ -- outputs: r_sig
+ DetectState: process (sw_state)
+ begin -- process DetectState
+ if (sw_state'event and sw_state = '0') then
+ log10_r_sig <= log10_r_open;
+ elsif (sw_state'event and sw_state = '1') then
+ log10_r_sig <= log10_r_closed;
+ end if;
+ end process DetectState;
+
+-- Characteristic equations
+ log10_r == log10_r_sig'ramp(trans_time, trans_time);
+ r == 10**log10_r;
+ v == r*i;
+end architecture log;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : buff.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Simple Buffer with delay time
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity buff is
+ generic (
+ delay : time := 0 ns); -- Delay time
+
+ port (
+ input : in std_logic;
+ output : out std_logic);
+
+end entity buff;
+
+architecture ideal of buff is
+
+begin
+ output <= input after delay;
+
+end architecture ideal;
+
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Inverter
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY inverter IS
+ GENERIC (
+ delay : time := 0 ns); -- Delay time
+
+ PORT (
+ input : IN std_logic;
+ output : OUT std_logic);
+
+END ENTITY inverter;
+
+ARCHITECTURE ideal OF inverter IS
+BEGIN
+ output <= NOT input AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : opamp.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: 3-pin OpAmp model with behavioral architecture
+-- Uses Q'LTF function to define open-loop response
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity opamp is
+-- Initialize parameters
+ generic (rin : resistance := 1.0e6; -- Input resistance [Ohms]
+ rout : resistance := 100.0; -- Output resistance (Ohms]
+ avol : real := 100.0e3; -- Open loop gain
+ f_0dB : real := 1.0e6 -- Unity Gain Frequency [Hz]
+ );
+-- Define ports as electrical terminals
+ port (
+ terminal in_pos, in_neg, output : electrical);
+
+end entity opamp;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Characteristics modeled:
+-- 1. Open loop gain
+-- 2. Frequency characteristics (single pole response)
+-- 3. Input and output resistance
+-- Uses Q'Ltf function to create open loop gain and roll off
+-------------------------------------------------------------------------------
+architecture basic of opamp is
+ -- Declare constants
+ constant f_3db : real := f_0db / avol; -- -3dB frequency
+ constant w_3dB : real := math_2_pi*f_3dB; -- -3dB freq in radians
+ -- Numerator and denominator for Q'LTF function
+ constant num : real_vector := (0 => avol);
+ constant den : real_vector := (1.0, 1.0/w_3dB);
+ -- Declare input and output quantities
+ quantity v_in across i_in through in_pos to in_neg;
+ quantity v_out across i_out through output;
+
+begin -- ARCHITECTURE basic
+
+ i_in == v_in / rin; -- input current
+ v_out == v_in'ltf(num, den) + i_out*rout; -- output voltage
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical Resistor Model
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY resistor IS
+
+-- Initialize parameters
+ GENERIC (
+ res : RESISTANCE); -- resistance (no initial value)
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL p1, p2 : ELECTRICAL);
+
+END ENTITY resistor;
+
+-- Ideal Architecture (V = I*R)
+ARCHITECTURE ideal OF resistor IS
+
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH p1 TO p2;
+
+BEGIN
+
+-- Characteristic equations
+ v == i*res;
+
+END ARCHITECTURE ideal;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Constant Voltage Source (Includes Frequency Domain settings)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY v_constant IS
+
+-- Initialize parameters
+ GENERIC (
+ level : VOLTAGE; -- Constant voltage value (V)
+ ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
+ ac_phase : real := 0.0); -- AC phase (degrees)
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL pos, neg : ELECTRICAL);
+
+END ENTITY v_constant;
+
+-- Ideal Architecture (I = constant)
+ARCHITECTURE ideal OF v_constant IS
+
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH pos TO neg;
+-- Declare quantity in frequency domain for AC analysis
+ QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+
+ IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
+ v == level;
+ ELSE
+ v == ac_spec; -- used for Frequency (AC) analysis
+ END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : comparator_d.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/08/03
+-- Last update: 2001/08/03
+-------------------------------------------------------------------------------
+-- Description: Voltage comparator with digital output
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/08/03 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use IEEE natures and packages
+library IEEE;
+use ieee.std_logic_1164.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+use IEEE_proposed.ENERGY_SYSTEMS.all;
+
+entity comparator_d is
+
+ port (
+ terminal in_pos : electrical;
+ terminal in_neg : electrical;
+ signal output : out std_logic := '1' -- Digital output
+ );
+
+end comparator_d;
+-------------------------------------------------------------------------------
+-- Behavioral architecture
+-------------------------------------------------------------------------------
+architecture behavioral of comparator_d is
+ quantity Vin across in_pos;
+ quantity Vref across in_neg;
+
+begin -- behavioral
+
+ -- purpose: Detect threshold crossing and assign event on output
+ -- type : combinational
+ -- inputs : vin'above(thres)
+ -- outputs: pulse_signal
+ process (Vin'above(Vref)) is
+ begin -- PROCESS
+ if Vin'above(Vref) then
+ output <= '1' after 1us;
+ else
+ output <= '0' after 1us;
+ end if;
+ end process;
+
+end behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : v_pulse.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/07/09
+-------------------------------------------------------------------------------
+-- Description: Voltage Pulse Source
+-- Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
+-- time. Uses time2real function.
+-- Pulsewidth no longer includes
+-- rise and fall times.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_pulse is
+
+ generic (
+ initial : voltage := 0.0; -- initial value [Volts]
+ pulse : voltage; -- pulsed value [Volts]
+ ti2p : time := 1ns; -- initial to pulse [Sec]
+ tp2i : time := 1ns; -- pulse to initial [Sec]
+ delay : time := 0ms; -- delay time [Sec]
+ width : time; -- duration of pulse [Sec]
+ period : time; -- period [Sec]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port (
+ terminal pos, neg : electrical);
+
+end entity v_pulse;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_pulse is
+
+-- Declare Through and Across Branch Quantities
+ quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+-- Signal used in CreateEvent process below
+ signal pulse_signal : voltage := initial;
+
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+-- Note: these lines gave an error during simulation. Had to use a
+-- function call instead.
+-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
+-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
+
+-- Function to convert numbers of type TIME to type REAL
+ function time2real(tt : time) return real is
+ begin
+ return time'pos(tt) * 1.0e-15;
+ end time2real;
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+ constant ri2p : real := time2real(ti2p);
+ constant rp2i : real := time2real(tp2i);
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+ v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
+ else
+ v == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+-- purpose: Create events to define pulse shape
+-- type : combinational
+-- inputs :
+-- outputs: pulse_signal
+CreateEvent : process
+begin
+ wait for delay;
+ loop
+ pulse_signal <= pulse;
+ wait for (width + ti2p);
+ pulse_signal <= initial;
+ wait for (period - width - ti2p);
+ end loop;
+end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pwm_mac is
+ port(
+ terminal inp : electrical;
+ terminal inm : electrical;
+ dig_out : out std_logic
+ );
+end pwm_mac;
+
+architecture pwm_mac of pwm_mac is
+ -- Component declarations
+ -- Signal declarations
+ terminal cmp_in : electrical;
+ terminal plse_in : electrical;
+ terminal XSIG010002 : electrical;
+ terminal XSIG010003 : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ U1 : entity work.opamp(basic)
+ port map(
+ in_neg => XSIG010002,
+ in_pos => inm,
+ output => cmp_in
+ );
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => XSIG010002,
+ p2 => cmp_in
+ );
+ v2 : entity work.v_constant(ideal)
+ generic map(
+ level => 0.0
+ )
+ port map(
+ pos => XSIG010003,
+ neg => ELECTRICAL_REF
+ );
+ R2 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => plse_in,
+ p2 => XSIG010002
+ );
+ R3 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => inp,
+ p2 => XSIG010002
+ );
+ XCMP4 : entity work.comparator_d(behavioral)
+ port map(
+ output => dig_out,
+ in_pos => XSIG010003,
+ in_neg => cmp_in
+ );
+ v9 : entity work.v_pulse(ideal)
+ generic map(
+ initial => -4.7,
+ pulse => 4.7,
+ ti2p => 200 us,
+ tp2i => 200 us,
+ delay => 1 us,
+ width => 1 us,
+ period => 405 us
+ )
+ port map(
+ pos => plse_in,
+ neg => ELECTRICAL_REF
+ );
+end pwm_mac;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : diode_pwl.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Diode model with ideal architecture
+-- Currently no Generics due to bug in DV
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
+use IEEE_proposed.energy_systems.all;
+
+ENTITY diode_pwl IS
+ GENERIC (
+ ron : real; -- equivalent series resistance
+ roff : real); -- leakage resistance
+ PORT (
+ TERMINAL p, -- positive pin
+ m : electrical); -- minus pin
+END ENTITY diode_pwl;
+
+ARCHITECTURE simple OF diode_pwl IS
+ QUANTITY v across i through p TO m;
+
+BEGIN -- simple ARCHITECTURE
+ if v'Above(0.0) use
+ i == v/ron;
+ elsif not v'Above(0.0) use
+ i == v/roff;
+ else
+ i == 0.0;
+ end use;
+ break on v'Above(0.0);
+END ARCHITECTURE simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pwm_H_bridge is
+ port(
+ terminal mot_ccw : electrical;
+ terminal pwr_in : electrical;
+ terminal mot_cw : electrical;
+ terminal src_in : electrical
+ );
+end pwm_H_bridge;
+
+architecture pwm_H_bridge of pwm_H_bridge is
+ -- Component declarations
+ -- Signal declarations
+ signal pwm_out : std_logic;
+ signal sw_ccw : std_logic;
+ signal sw_cw : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ sw2 : entity work.switch_dig_log(linear)
+ generic map(
+ trans_time => 1.0e-5,
+ r_closed => 0.1
+ )
+ port map(
+ sw_state => sw_cw,
+ p2 => pwr_in,
+ p1 => mot_cw
+ );
+ sw3 : entity work.switch_dig_log(linear)
+ generic map(
+ trans_time => 1.0e-5,
+ r_closed => 0.1
+ )
+ port map(
+ sw_state => sw_ccw,
+ p2 => mot_cw,
+ p1 => ELECTRICAL_REF
+ );
+ U1 : entity work.buff(ideal)
+ port map(
+ input => pwm_out,
+ output => sw_cw
+ );
+ U2 : entity work.inverter(ideal)
+ port map(
+ input => pwm_out,
+ output => sw_ccw
+ );
+ sw5 : entity work.switch_dig_log(linear)
+ generic map(
+ trans_time => 1.0e-5,
+ r_closed => 0.1
+ )
+ port map(
+ sw_state => sw_ccw,
+ p2 => pwr_in,
+ p1 => mot_ccw
+ );
+ sw6 : entity work.switch_dig_log(linear)
+ generic map(
+ trans_time => 1.0e-5,
+ r_closed => 0.1
+ )
+ port map(
+ sw_state => sw_cw,
+ p2 => mot_ccw,
+ p1 => ELECTRICAL_REF
+ );
+ pwm : entity work.pwm_mac
+ port map(
+ inp => src_in,
+ dig_out => pwm_out,
+ inm => ELECTRICAL_REF
+ );
+ D7 : entity work.diode_pwl(simple)
+ generic map(
+ roff => 100.0e3,
+ ron => 0.001
+ )
+ port map(
+ p => mot_cw,
+ m => pwr_in
+ );
+ D8 : entity work.diode_pwl(simple)
+ generic map(
+ ron => 0.001,
+ roff => 100.0e3
+ )
+ port map(
+ p => mot_ccw,
+ m => pwr_in
+ );
+ D9 : entity work.diode_pwl(simple)
+ generic map(
+ ron => 0.001,
+ roff => 100.0e3
+ )
+ port map(
+ p => ELECTRICAL_REF,
+ m => mot_cw
+ );
+ D10 : entity work.diode_pwl(simple)
+ generic map(
+ ron => 0.001,
+ roff => 100.0e3
+ )
+ port map(
+ p => ELECTRICAL_REF,
+ m => mot_ccw
+ );
+end pwm_H_bridge;
+--
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical sinusoidal voltage source (stick.vhd)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+
+ENTITY stick IS
+
+-- Initialize parameters
+ GENERIC (
+ freq : real; -- frequency, [Hertz]
+ amplitude : real; -- amplitude, [Volt]
+ phase : real := 0.0; -- initial phase, [Degree]
+ offset : real := 0.0; -- DC value, [Volt]
+ df : real := 0.0; -- damping factor, [1/second]
+ ac_mag : real := 1.0; -- AC magnitude, [Volt]
+ ac_phase : real := 0.0); -- AC phase, [Degree]
+
+-- Define ports as electrical terminals
+ PORT (
+ TERMINAL v_out : ELECTRICAL);
+
+END ENTITY stick;
+
+-- Ideal Architecture
+ARCHITECTURE ideal OF stick IS
+-- Declare Branch Quantities
+ QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
+-- Declare Quantity for Phase in radians (calculated below)
+ QUANTITY phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+ QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+-- Convert phase to radians
+ phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+ IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
+ v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+ ELSE
+ v == ac_spec; -- used for Frequency (AC) analysis
+ END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : inductor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Electrical Inductor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity inductor is
+
+ generic (
+ ind : inductance; -- Nominal inductance
+ i_ic : real := real'low); -- Initial current (use IF statement below
+ -- to activate)
+
+ port (
+ terminal p1, p2 : electrical);
+
+end entity inductor;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture (V = L * di/dt)
+-- Includes initial condition
+-------------------------------------------------------------------------------
+architecture ideal of inductor is
+
+-- Declare Branch Quantities
+ quantity v across i through p1 to p2;
+
+begin
+
+ if domain = quiescent_domain and i_ic /= real'low use
+ i == i_ic;
+ else
+ v == ind * i'dot; -- characteristic equation
+ end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except
+-- compilations distributed in accordance with Section (d) of this license
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such
+-- version is modified; (c) any modified version must include a conspicuous
+-- notice that this model has been modified and the date of modification; and
+-- (d) any compilations sold by you that include this model must include a
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
+-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File : capacitor.vhd
+-- Author : Mentor Graphics
+-- Created : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Electrical Capacitor
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2001/06/16 1.0 Mentor Graphics Created
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity capacitor is
+
+ generic (
+ cap : capacitance; -- Capacitance [F]
+ v_ic : real := real'low; -- Initial voltage (activated by
+ -- IF statement below)
+ r_esr : resistance := 0.0); -- Equivalent Series Capicitance
+ -- (used only in ESR architecture)
+
+ port (
+ terminal p1, p2 : electrical);
+
+end entity capacitor;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture (I = C * dV/dt)
+-- Includes initial condition
+-------------------------------------------------------------------------------
+architecture ideal of capacitor is
+
+ quantity v across i through p1 to p2;
+
+begin
+
+ if domain = quiescent_domain and v_ic /= real'low use
+ v == v_ic;
+ else
+ i == cap * v'dot; -- characteristic equation
+ end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Architecture includes effects of Equivalent Series Capacitance
+-------------------------------------------------------------------------------
+architecture ESR of capacitor is
+ quantity v across i through p1 to p2;
+ quantity vc : voltage; -- Internal voltage across capacitor
+begin
+ if domain = quiescent_domain and v_ic /= real'low use
+ vc == v_ic;
+ i == 0.0;
+ else
+ vc == v - (i * r_esr);
+ i == cap * vc'dot;
+
+ end use;
+end architecture ESR;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+
+entity buck_sw is
+
+ generic (
+ Vd : voltage := 0.7; -- Diode Voltage
+ Vramp : voltage := 2.5); -- P-P amplitude of ramp voltage
+
+ port (
+ terminal input, output, ref, ctrl: electrical);
+
+end entity buck_sw;
+
+architecture average of buck_sw is
+
+ quantity Vout across Iout through output to ref;
+ quantity Vin across input to ref;
+ quantity Vctrl across ctrl to ref;
+
+begin -- bhv
+
+ Vout + Vd == Vctrl * Vin / Vramp;
+
+end average;
+
+--
+
+-- Loop control switch
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity sw_LoopCtrl is
+ generic (r_open : resistance := 1.0e6;
+ r_closed : resistance := 1.0e-3;
+ sw_state : integer := 1);
+
+ port (terminal c, p1, p2 : electrical);
+end entity sw_LoopCtrl;
+
+architecture ideal of sw_LoopCtrl is
+ quantity v1 across i1 through c to p1;
+ quantity v2 across i2 through c to p2;
+ quantity r1, r2 : resistance;
+begin
+ if (sw_state = 1) use
+ r1 == r_closed;
+ r2 == r_open;
+ elsif (sw_state = 2) use
+ r1 == r_open;
+ r2 == r_closed;
+ else
+ r1 == r_closed;
+ r2 == r_open;
+ end use;
+
+ v1 == r1*i1;
+ v2 == r2*i2;
+end architecture ideal;
+--
+
+library ieee, ieee_proposed;
+use ieee.math_real.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity comp_2p2z is
+ generic (
+ gain : real := 100.0; -- High DC gain for good load regulation
+ fp1 : real := 7.5e3; -- Pole location to achieve crossover frequency
+ fp2 : real := 531.0e3; -- Pole location to cancel effect of ESR
+ fz1 : real := 806.0; -- Zero locations to cancel LC filter poles
+ fz2 : real := 806.0);
+ port (
+ terminal input, output, ref : electrical);
+end entity comp_2p2z;
+
+architecture ltf of comp_2p2z is
+ quantity vin across input to ref;
+ quantity vout across iout through output to ref;
+ constant wp1 : real := math_2_pi*fp1; -- Pole freq (in radians)
+ constant wp2 : real := math_2_pi*fp2;
+ constant wz1 : real := math_2_pi*fz1; -- Zero freq (in radians)
+ constant wz2 : real := math_2_pi*fz2;
+ constant num : real_vector := (1.0, 1.0/wz1 + 1.0/wz2, 1.0/(wz1*wz2));
+ constant den : real_vector := (1.0e-9,1.0,1.0/wp1+1.0/wp2,1.0/(wp1*wp2));
+
+begin
+ vout == -1.0*gain*vin'ltf(num, den);
+end architecture ltf;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity ex_buck is
+ port(
+ terminal pwr_out : electrical
+ );
+end ex_buck;
+
+architecture ex_buck of ex_buck is
+ -- Component declarations
+ -- Signal declarations
+ terminal vcomp_out : electrical;
+ terminal vctrl : electrical;
+ terminal vctrl_init : electrical;
+ terminal vin : electrical;
+ terminal vmid : electrical;
+ terminal XSIG010004 : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ l1 : entity work.inductor(ideal)
+ generic map(
+ ind => 6.5e-3
+ )
+ port map(
+ p1 => vmid,
+ p2 => pwr_out
+ );
+ c1 : entity work.capacitor(ideal)
+ generic map(
+ cap => 6.0e-6,
+ r_esr => 50.0e-3
+ )
+ port map(
+ p1 => pwr_out,
+ p2 => ELECTRICAL_REF
+ );
+ buck_sw1 : entity work.buck_sw(average)
+ port map(
+ output => vmid,
+ ref => ELECTRICAL_REF,
+ ctrl => vctrl,
+ input => vin
+ );
+ sw1 : entity work.sw_LoopCtrl(ideal)
+ generic map(
+ sw_state => 1
+ )
+ port map(
+ p2 => vctrl_init,
+ c => vctrl,
+ p1 => vcomp_out
+ );
+ comp_2p2z1 : entity work.comp_2p2z(ltf)
+ port map(
+ ref => XSIG010004,
+ output => vcomp_out,
+ input => pwr_out
+ );
+ v1 : entity work.v_pulse(ideal)
+ generic map(
+ initial => 42.0,
+ pulse => 42.0,
+ delay => 10ms,
+ width => 100ms,
+ period => 1000ms
+ )
+ port map(
+ pos => vin,
+ neg => ELECTRICAL_REF
+ );
+ v2 : entity work.v_constant(ideal)
+ generic map(
+ level => 0.327
+ )
+ port map(
+ pos => vctrl_init,
+ neg => ELECTRICAL_REF
+ );
+ v3 : entity work.v_constant(ideal)
+ generic map(
+ level => 4.8
+ )
+ port map(
+ pos => XSIG010004,
+ neg => ELECTRICAL_REF
+ );
+end ex_buck;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CS5_Rudder_Power is
+end tb_CS5_Rudder_Power ;
+
+architecture TB_CS5_Rudder_Power of tb_CS5_Rudder_Power is
+ -- Component declarations
+ -- Signal declarations
+ terminal buck_out : electrical;
+ terminal gear_out : rotational;
+ terminal link_in : translational;
+ terminal link_out : translational;
+ terminal mot_ccw : electrical;
+ terminal mot_cw : electrical;
+ terminal mot_out : rotational_v;
+ terminal pos_fb_v : electrical;
+ terminal pwm_in : electrical;
+ terminal rudder : rotational;
+ terminal src_in : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ rudder_servo1 : entity work.rudder_servo
+ port map(
+ servo_out => pwm_in,
+ servo_in => src_in,
+ pos_fb => pos_fb_v
+ );
+ gear3 : entity work.gear_rv_r(ideal)
+ generic map(
+ ratio => 0.01
+ )
+ port map(
+ rotv1 => mot_out,
+ rot2 => gear_out
+ );
+ r2v : entity work.rot2v(bhv)
+ generic map(
+ k => 1.0
+ )
+ port map(
+ output => pos_fb_v,
+ input => gear_out
+ );
+ r2t : entity work.horn_r2t(bhv)
+ port map(
+ theta => gear_out,
+ pos => link_in
+ );
+ t2r : entity work.horn_t2r(bhv)
+ port map(
+ theta => rudder,
+ pos => link_out
+ );
+ motor1 : entity work.DC_Motor(basic)
+ generic map(
+ r_wind => 2.2,
+ kt => 3.43e-3,
+ l => 2.03e-3,
+ d => 5.63e-6,
+ j => 168.0e-9
+ )
+ port map(
+ p1 => mot_cw,
+ p2 => mot_ccw,
+ shaft_rotv => mot_out
+ );
+ stop1 : entity work.stop_r(ideal)
+ generic map(
+ damp_stop => 1.0e2,
+ k_stop => 1.0e6,
+ ang_max => 1.05,
+ ang_min => -1.05
+ )
+ port map(
+ ang1 => gear_out,
+ ang2 => ROTATIONAL_REF
+ );
+ \linkage\ : entity work.tran_linkage(a1)
+ port map(
+ p2 => link_out,
+ p1 => link_in
+ );
+ rudder_1 : entity work.rudder(bhv)
+ generic map(
+ k => 0.02
+ )
+ port map(
+ rot => rudder
+ );
+ pwm_H_bridge1 : entity work.pwm_H_bridge
+ port map(
+ src_in => pwm_in,
+ mot_cw => mot_cw,
+ pwr_in => buck_out,
+ mot_ccw => mot_ccw
+ );
+ XCMP65 : entity work.stick(ideal)
+ generic map(
+ freq => 1.0,
+ amplitude => 4.7,
+ phase => 0.0,
+ offset => 0.0
+ )
+ port map(
+ v_out => src_in
+ );
+ ex_buck4 : entity work.ex_buck
+ port map(
+ pwr_out => buck_out
+ );
+end TB_CS5_Rudder_Power;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/bounded_buffer_adt.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/bounded_buffer_adt.vhd
new file mode 100644
index 000000000..3041d0380
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/bounded_buffer_adt.vhd
@@ -0,0 +1,114 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package bounded_buffer_adt is
+
+ subtype byte is bit_vector(0 to 7);
+
+ type bounded_buffer_object; -- private
+
+ type bounded_buffer is access bounded_buffer_object;
+
+ function new_bounded_buffer ( size : in positive ) return bounded_buffer;
+ -- creates a bounded buffer object with 'size' bytes of storage
+
+ procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
+ is_empty : out boolean );
+ -- tests whether the bounded buffer is empty (i.e., no data to read)
+
+ procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
+ is_full : out boolean );
+ -- tests whether the bounded buffer is full (i.e., no data can be written)
+
+ procedure write ( the_bounded_buffer : inout bounded_buffer; data : in byte );
+ -- if the bounded buffer is not full, writes the data
+ -- if it is full, assertion violation with severity failure
+
+ procedure read ( the_bounded_buffer : inout bounded_buffer; data : out byte );
+ -- if the bounded buffer is not empty, read the first byte of data
+ -- if it is empty, assertion violation with severity failure
+
+----------------------------------------------------------------
+
+ -- the following types are private to the ADT
+
+ type store_array is array (natural range <>) of byte;
+
+ type store_ptr is access store_array;
+
+ type bounded_buffer_object is record
+ byte_count : natural;
+ head_index, tail_index : natural;
+ store : store_ptr;
+ end record bounded_buffer_object;
+
+end package bounded_buffer_adt;
+
+
+
+package body bounded_buffer_adt is
+
+ function new_bounded_buffer ( size : in positive ) return bounded_buffer is
+ begin
+ return new bounded_buffer_object'(
+ byte_count => 0, head_index => 0, tail_index => 0,
+ store => new store_array(0 to size - 1) );
+ end function new_bounded_buffer;
+
+ procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
+ is_empty : out boolean ) is
+ begin
+ is_empty := the_bounded_buffer.byte_count = 0;
+ end procedure test_empty;
+
+ procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
+ is_full : out boolean ) is
+ begin
+ is_full := the_bounded_buffer.byte_count = the_bounded_buffer.store'length;
+ end procedure test_full;
+
+ procedure write ( the_bounded_buffer : inout bounded_buffer; data : in byte ) is
+ variable buffer_full : boolean;
+ begin
+ test_full(the_bounded_buffer, buffer_full);
+ if buffer_full then
+ report "write to full bounded buffer" severity failure;
+ else
+ the_bounded_buffer.store(the_bounded_buffer.tail_index) := data;
+ the_bounded_buffer.tail_index := (the_bounded_buffer.tail_index + 1)
+ mod the_bounded_buffer.store'length;
+ the_bounded_buffer.byte_count := the_bounded_buffer.byte_count + 1;
+ end if;
+ end procedure write;
+
+ procedure read ( the_bounded_buffer : inout bounded_buffer; data : out byte ) is
+ variable buffer_empty : boolean;
+ begin
+ test_empty(the_bounded_buffer, buffer_empty);
+ if buffer_empty then
+ report "read from empty bounded buffer" severity failure;
+ else
+ data := the_bounded_buffer.store(the_bounded_buffer.head_index);
+ the_bounded_buffer.head_index := (the_bounded_buffer.head_index + 1)
+ mod the_bounded_buffer.store'length;
+ the_bounded_buffer.byte_count := the_bounded_buffer.byte_count - 1;
+ end if;
+ end procedure read;
+
+end package body bounded_buffer_adt;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/index-ams.txt
new file mode 100644
index 000000000..6a27774ef
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/index-ams.txt
@@ -0,0 +1,30 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 20 - Access Types and Abstract Data Types
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+list_traversal.vhd entity list_traversal test Figure 20-5
+list_search.vhd entity list_search test Figure 20-7
+bounded_buffer_adt.vhd package bounded_buffer_adt body Figures 20-8, 20-11
+receiver.vhd entity receiver test Figure 20-9
+ordered_collection_adt.vhd package «element_type_simple_name»_ordered_collection_adt
+-- body Figures 20-12, 20-16
+stimulus_types-1.vhd package stimulus_types body Figure 20-13
+test_bench-1.vhd package stimulus_element_ordered_collection_adt
+-- body --
+-- entity test_bench initial_test Figure 20-14
+inline_01.vhd entity inline_01 test Section 20.1
+inline_02a.vhd entity inline_02a test Section 20.1
+inline_03.vhd entity inline_03 test Section 20.1
+inline_04a.vhd entity inline_04a test Section 20.1
+inline_05.vhd entity inline_05 test Section 20.1
+inline_06a.vhd entity inline_06a test Section 20.2
+inline_07a.vhd entity inline_07a test Section 20.2
+inline_08.vhd entity inline_08 test Section 20.2
+inline_09.vhd entity inline_09 test Section 20.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_bounded_buffer_adt.vhd entity tb_bounded_buffer_adt test bounded_buffer_adt.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_01.vhd
new file mode 100644
index 000000000..2d326bda1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_01.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+ process is
+
+ -- code from book:
+
+ type natural_ptr is access natural;
+
+ variable count : natural_ptr;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ count := new natural;
+
+ count.all := 10;
+
+ if count.all = 0 then
+ -- . . .
+ -- not in book
+ report "count.all = 0";
+ -- end not in book
+ end if;
+
+ -- end of code from book
+
+ if count.all /= 0 then
+ report "count.all /= 0";
+ end if;
+
+ -- code from book:
+
+ count := new natural'(10);
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_02a.vhd
new file mode 100644
index 000000000..2a0e4e686
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_02a.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02a is
+begin
+
+
+ process is
+
+ -- code from book:
+
+ type stimulus_record is record
+ stimulus_time : time;
+ stimulus_value : real_vector(0 to 3);
+ end record stimulus_record;
+
+ type stimulus_ptr is access stimulus_record;
+
+ variable bus_stimulus : stimulus_ptr;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ bus_stimulus := new stimulus_record'( 20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_03.vhd
new file mode 100644
index 000000000..e4ed82464
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_03.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+begin
+
+
+ process is
+
+ type natural_ptr is access natural;
+
+ -- code from book:
+
+ variable count1, count2 : natural_ptr;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ count1 := new natural'(5);
+ count2 := new natural'(10);
+
+ count2 := count1;
+
+ count1.all := 20;
+
+ -- end of code from book
+
+ assert
+ -- code from book:
+ count1 = count2
+ -- end of code from book
+ ;
+
+ -- code from book:
+
+ count1 := new natural'(30);
+ count2 := new natural'(30);
+
+ -- end of code from book
+
+ assert count1 = count2;
+
+ assert
+ -- code from book:
+ count1.all = count2.all
+ -- end of code from book
+ ;
+
+ -- code from book:
+
+ if count1 /= null then
+ count1.all := count1.all + 1;
+ end if;
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_04a.vhd
new file mode 100644
index 000000000..82aa9448f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_04a.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04a is
+begin
+
+
+ process is
+
+ -- code from book:
+
+ type stimulus_record is record
+ stimulus_time : time;
+ stimulus_value : real_vector(0 to 3);
+ end record stimulus_record;
+
+ type stimulus_ptr is access stimulus_record;
+
+ variable bus_stimulus : stimulus_ptr;
+
+ -- end of code from book
+
+ begin
+
+ bus_stimulus := new stimulus_record;
+
+ bus_stimulus.all := stimulus_record'(20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
+
+ report time'image(bus_stimulus.all.stimulus_time);
+
+ report time'image(bus_stimulus.stimulus_time);
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_05.vhd
new file mode 100644
index 000000000..8a03a87f4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_05.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+begin
+
+
+ process is
+
+ -- code from book:
+
+ type coordinate is array (1 to 3) of real;
+ type coordinate_ptr is access coordinate;
+
+ variable origin : coordinate_ptr := new coordinate'(0.0, 0.0, 0.0);
+
+ type time_array is array (positive range <>) of time;
+ variable activation_times : time_array(1 to 100);
+
+ -- end of code from book
+
+ begin
+
+ report real'image( origin(1) );
+ report real'image( origin(2) );
+ report real'image( origin(3) );
+ report real'image( origin.all(1) );
+
+ wait;
+ end process;
+
+
+ process is
+
+ type time_array is array (positive range <>) of time;
+
+ -- code from book:
+
+ type time_array_ptr is access time_array;
+
+ variable activation_times : time_array_ptr;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ activation_times := new time_array'(10 us, 15 us, 40 us);
+
+ activation_times := new time_array'( activation_times.all
+ & time_array'(70 us, 100 us) );
+
+ activation_times := new time_array(1 to 10);
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_06a.vhd
new file mode 100644
index 000000000..4322b31ed
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_06a.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_06a is
+
+end entity inline_06a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06a is
+begin
+
+
+ process is
+
+ -- code from book:
+
+ type value_cell is record
+ value : real_vector(0 to 3);
+ next_cell : value_ptr;
+ end record value_cell;
+
+ type value_ptr is access value_cell;
+
+ -- end of code from book
+
+ begin
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_07a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_07a.vhd
new file mode 100644
index 000000000..64b633797
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_07a.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_07a is
+
+end entity inline_07a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_07a is
+begin
+
+
+ process is
+
+ -- code from book:
+
+ type value_cell;
+
+ type value_ptr is access value_cell;
+
+ type value_cell is record
+ value : real_vector(0 to 3);
+ next_cell : value_ptr;
+ end record value_cell;
+
+ variable value_list : value_ptr;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ if value_list /= null then
+ -- . . . -- do something with the list
+ -- not in book
+ report "value_list /= null";
+ -- end not in book
+ end if;
+
+ value_list := new value_cell'( real_vector'(0.0, 5.0, 0.0, 42.0), value_list );
+
+ value_list := new value_cell'( real_vector'(3.3, 2.2, 0.27, 1.9), value_list );
+
+ value_list := new value_cell'( real_vector'(2.9, 0.1, 21.12, 8.3), value_list );
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_08.vhd
new file mode 100644
index 000000000..9533f4fd1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_08.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_08 is
+
+ type T is (t1, t2, t3);
+
+ -- code from book:
+
+ type T_ptr is access T;
+
+ procedure deallocate ( P : inout T_ptr );
+
+ -- end of code from book
+
+ procedure deallocate ( P : inout T_ptr ) is
+ begin
+ null;
+ end procedure deallocate;
+
+begin
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_09.vhd
new file mode 100644
index 000000000..d570cee51
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_09.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+
+begin
+
+ process is
+
+ type value_cell;
+
+ type value_ptr is access value_cell;
+
+ type value_cell is record
+ value : bit_vector(0 to 3);
+ next_cell : value_ptr;
+ end record value_cell;
+
+ variable value_list, cell_to_be_deleted : value_ptr;
+
+ begin
+ value_list := new value_cell'( B"1000", value_list );
+ value_list := new value_cell'( B"0010", value_list );
+ value_list := new value_cell'( B"0000", value_list );
+
+ -- code from book:
+
+ cell_to_be_deleted := value_list;
+ value_list := value_list.next_cell;
+ deallocate(cell_to_be_deleted);
+
+ while value_list /= null loop
+ cell_to_be_deleted := value_list;
+ value_list := value_list.next_cell;
+ deallocate(cell_to_be_deleted);
+ end loop;
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_search.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_search.vhd
new file mode 100644
index 000000000..57208983d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_search.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity list_search is
+
+end entity list_search;
+
+
+----------------------------------------------------------------
+
+
+architecture test of list_search is
+
+ signal s : bit_vector(0 to 3);
+
+begin
+
+ process is
+
+ type value_cell;
+
+ type value_ptr is access value_cell;
+
+ type value_cell is record
+ value : bit_vector(0 to 3);
+ next_cell : value_ptr;
+ end record value_cell;
+
+ variable value_list, current_cell : value_ptr;
+ variable search_value : bit_vector(0 to 3);
+
+ begin
+ value_list := new value_cell'( B"1000", value_list );
+ value_list := new value_cell'( B"0010", value_list );
+ value_list := new value_cell'( B"0000", value_list );
+
+ search_value := B"0010";
+
+ -- code from book:
+
+ current_cell := value_list;
+ while current_cell /= null
+ and current_cell.value /= search_value loop
+ current_cell := current_cell.next_cell;
+ end loop;
+ assert current_cell /= null
+ report "search for value failed";
+
+ -- end of code from book
+
+ search_value := B"1111";
+
+ current_cell := value_list;
+ while current_cell /= null
+ and current_cell.value /= search_value loop
+ current_cell := current_cell.next_cell;
+ end loop;
+ assert current_cell /= null
+ report "search for value failed";
+
+ wait;
+ end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_traversal.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_traversal.vhd
new file mode 100644
index 000000000..4c0dedd5f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_traversal.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity list_traversal is
+
+end entity list_traversal;
+
+
+----------------------------------------------------------------
+
+
+architecture test of list_traversal is
+
+ signal s : bit_vector(0 to 3);
+
+begin
+
+ process is
+
+ type value_cell;
+
+ type value_ptr is access value_cell;
+
+ type value_cell is record
+ value : bit_vector(0 to 3);
+ next_cell : value_ptr;
+ end record value_cell;
+
+ variable value_list, current_cell : value_ptr;
+
+ begin
+ value_list := new value_cell'( B"1000", value_list );
+ value_list := new value_cell'( B"0010", value_list );
+ value_list := new value_cell'( B"0000", value_list );
+
+ -- code from book:
+
+ current_cell := value_list;
+ while current_cell /= null loop
+ s <= current_cell.value;
+ wait for 10 ns;
+ current_cell := current_cell.next_cell;
+ end loop;
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/ordered_collection_adt.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/ordered_collection_adt.vhd
new file mode 100644
index 000000000..5a011748a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/ordered_collection_adt.vhd
@@ -0,0 +1,163 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package «element_type_simple_name»_ordered_collection_adt is
+
+ -- template: fill in the placeholders to specialize for a particular type
+
+ alias element_type is «element_type»;
+ alias key_type is «key_type»;
+ alias key_of is «key_function» [ element_type return key_type ];
+ alias "<" is «less_than_function» [ key_type, key_type return boolean ];
+
+ -- types provided by the package
+
+ type ordered_collection_object; -- private
+ type position_object; -- private
+
+ type ordered_collection is access ordered_collection_object;
+ type position is access position_object;
+
+ -- operations on ordered collections
+
+ function new_ordered_collection return ordered_collection;
+ -- returns an empty ordered collection of element_type values
+
+ procedure insert ( c : inout ordered_collection; e : in element_type );
+ -- inserts e into c in position determined by key_of(e)
+
+ procedure get_element ( variable p : in position; e : out element_type );
+ -- returns the element value at position p in its collection
+
+ procedure test_null_position ( variable p : in position; is_null : out boolean );
+ -- test whether p refers to no position in its collection
+
+ procedure search ( variable c : in ordered_collection; k : in key_type;
+ p : out position );
+ -- searches for an element with key k in c, and returns the position of
+ -- that element, or, if not found, a position for which test_null_position
+ -- returns true
+
+ procedure find_first ( variable c : in ordered_collection; p : out position );
+ -- returns the position of the first element of c
+
+ procedure advance ( p : inout position );
+ -- advances p to the next element in its collection,
+ -- or if there are no more, sets p so that test_null_position returns true
+
+ procedure delete ( p : inout position );
+ -- deletes the element at position p from its collection, and advances p
+
+ -- private types: pretend these are not visible
+
+ type ordered_collection_object is
+ record
+ element : element_type;
+ next_element, prev_element : ordered_collection;
+ end record ordered_collection_object;
+
+ type position_object is
+ record
+ the_collection : ordered_collection;
+ current_element : ordered_collection;
+ end record position_object;
+
+end package «element_type_simple_name»_ordered_collection_adt;
+
+
+package body «element_type_simple_name»_ordered_collection_adt is
+
+ function new_ordered_collection return ordered_collection is
+ variable result : ordered_collection := new ordered_collection_object;
+ begin
+ result.next_element := result;
+ result.prev_element := result;
+ return result;
+ end function new_ordered_collection;
+
+ procedure insert ( c : inout ordered_collection; e : in element_type ) is
+ variable current_element : ordered_collection := c.next_element;
+ variable new_element : ordered_collection;
+ begin
+ while current_element /= c
+ and key_of(current_element.element) < key_of(e) loop
+ current_element := current_element.next_element;
+ end loop;
+ -- insert new element before current_element
+ new_element := new ordered_collection_object'(
+ element => e,
+ next_element => current_element,
+ prev_element => current_element.prev_element );
+ new_element.next_element.prev_element := new_element;
+ new_element.prev_element.next_element := new_element;
+ end procedure insert;
+
+ procedure get_element ( variable p : in position; e : out element_type ) is
+ begin
+ e := p.current_element.element;
+ end procedure get_element;
+
+ procedure test_null_position ( variable p : in position; is_null : out boolean ) is
+ begin
+ is_null := p.current_element = p.the_collection;
+ end procedure test_null_position;
+
+ procedure search ( variable c : in ordered_collection; k : in key_type;
+ p : out position ) is
+ variable current_element : ordered_collection := c.next_element;
+ begin
+ while current_element /= c
+ and key_of(current_element.element) < k loop
+ current_element := current_element.next_element;
+ end loop;
+ if current_element = c or k < key_of(current_element.element) then
+ p := new position_object'(c, c); -- null position
+ else
+ p := new position_object'(c, current_element);
+ end if;
+ end procedure search;
+
+ procedure find_first ( variable c : in ordered_collection; p : out position ) is
+ begin
+ p := new position_object'(c, c.next_element);
+ end procedure find_first;
+
+ procedure advance ( p : inout position ) is
+ variable is_null : boolean;
+ begin
+ test_null_position(p, is_null);
+ if not is_null then
+ p.current_element := p.current_element.next_element;
+ end if;
+ end procedure advance;
+
+ procedure delete ( p : inout position ) is
+ variable is_null : boolean;
+ begin
+ test_null_position(p, is_null);
+ if not is_null then
+ p.current_element.next_element.prev_element
+ := p.current_element.prev_element;
+ p.current_element.prev_element.next_element
+ := p.current_element.next_element;
+ p.current_element := p.current_element.next_element;
+ end if;
+ end procedure delete;
+
+end package body «element_type_simple_name»_ordered_collection_adt;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/receiver.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/receiver.vhd
new file mode 100644
index 000000000..e7aad315c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/receiver.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity receiver is
+end entity receiver;
+
+
+
+architecture test of receiver is
+begin
+
+ -- code from book
+
+ receiver : process is
+
+ use work.bounded_buffer_adt.all;
+
+ variable receive_buffer : bounded_buffer := new_bounded_buffer(2048);
+ variable buffer_overrun, buffer_underrun : boolean;
+ -- . . .
+
+ -- not in book
+ variable received_byte, check_byte : byte;
+ -- end not in book
+
+ begin
+ -- . . .
+
+ test_full(receive_buffer, buffer_overrun);
+ if not buffer_overrun then
+ write(receive_buffer, received_byte);
+ end if;
+ -- . . .
+
+ test_empty(receive_buffer, buffer_underrun);
+ if not buffer_underrun then
+ read(receive_buffer, check_byte);
+ end if;
+ -- . . .
+
+ end process receiver;
+
+ -- end code from book
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/stimulus_types-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/stimulus_types-1.vhd
new file mode 100644
index 000000000..a7d924533
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/stimulus_types-1.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package stimulus_types is
+
+ constant stimulus_vector_length : positive := 4;
+
+ type stimulus_element is record
+ application_time : delay_length;
+ pattern : real_vector(0 to stimulus_vector_length - 1);
+ end record stimulus_element;
+
+ function stimulus_key ( stimulus : stimulus_element ) return delay_length;
+
+end package stimulus_types;
+
+----------------------------------------------------------------
+
+package body stimulus_types is
+
+ function stimulus_key ( stimulus : stimulus_element ) return delay_length is
+ begin
+ return stimulus.application_time;
+ end function stimulus_key;
+
+end package body stimulus_types;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/tb_bounded_buffer_adt.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/tb_bounded_buffer_adt.vhd
new file mode 100644
index 000000000..9da5aa2aa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/tb_bounded_buffer_adt.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_bounded_buffer_adt is
+end entity tb_bounded_buffer_adt;
+
+
+architecture test of tb_bounded_buffer_adt is
+begin
+
+ process is
+
+ use work.bounded_buffer_adt.all;
+
+ variable buf : bounded_buffer := new_bounded_buffer(4);
+ variable empty, full : boolean;
+ variable d : byte;
+
+ begin
+ test_empty(buf, empty);
+ assert empty;
+ test_full(buf, full);
+ assert not full;
+
+ write(buf, X"01");
+ write(buf, X"02");
+
+ test_empty(buf, empty);
+ assert not empty;
+ test_full(buf, full);
+ assert not full;
+
+ write(buf, X"03");
+ write(buf, X"04");
+
+ test_empty(buf, empty);
+ assert not empty;
+ test_full(buf, full);
+ assert full;
+
+ write(buf, X"05");
+
+ read(buf, d);
+ read(buf, d);
+
+ test_empty(buf, empty);
+ assert not empty;
+ test_full(buf, full);
+ assert not full;
+
+ read(buf, d);
+ read(buf, d);
+
+ test_empty(buf, empty);
+ assert empty;
+ test_full(buf, full);
+ assert not full;
+
+ read(buf, d);
+
+ write(buf, X"06");
+ write(buf, X"07");
+ write(buf, X"08");
+ read(buf, d);
+ read(buf, d);
+ write(buf, X"09");
+ read(buf, d);
+ write(buf, X"0A");
+ read(buf, d);
+ write(buf, X"0B");
+ read(buf, d);
+ write(buf, X"0C");
+ read(buf, d);
+ write(buf, X"0D");
+ read(buf, d);
+ write(buf, X"0E");
+ read(buf, d);
+ write(buf, X"0F");
+ read(buf, d);
+
+ wait;
+ end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/test_bench-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/test_bench-1.vhd
new file mode 100644
index 000000000..00ef8bdf5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/test_bench-1.vhd
@@ -0,0 +1,224 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+package stimulus_element_ordered_collection_adt is
+
+ -- template: fill in the placeholders to specialize for a particular type
+
+ alias element_type is work.stimulus_types.stimulus_element;
+ alias key_type is delay_length;
+ alias key_of is work.stimulus_types.stimulus_key [ element_type return key_type ];
+ alias "<" is std.standard."<" [ key_type, key_type return boolean ];
+
+ -- types provided by the package
+
+ type ordered_collection_object; -- private
+ type position_object; -- private
+
+ type ordered_collection is access ordered_collection_object;
+ type position is access position_object;
+
+ -- operations on ordered collections
+
+ function new_ordered_collection return ordered_collection;
+ -- returns an empty ordered collection of element_type values
+
+ procedure insert ( c : inout ordered_collection; e : in element_type );
+ -- inserts e into c in position determined by key_of(e)
+
+ procedure get_element ( variable p : in position; e : out element_type );
+ -- returns the element value at position p in its collection
+
+ procedure test_null_position ( variable p : in position; is_null : out boolean );
+ -- test whether p refers to no position in its collection
+
+ procedure search ( variable c : in ordered_collection; k : in key_type;
+ p : out position );
+ -- searches for an element with key k in c, and returns the position of
+ -- that element, or, if not found, a position for which test_null_position
+ -- returns true
+
+ procedure find_first ( variable c : in ordered_collection; p : out position );
+ -- returns the position of the first element of c
+
+ procedure advance ( p : inout position );
+ -- advances p to the next element in its collection,
+ -- or if there are no more, sets p so that test_null_position returns true
+
+ procedure delete ( p : inout position );
+ -- deletes the element at position p from its collection, and advances p
+
+ -- private types: pretend these are not visible
+
+ type ordered_collection_object is
+ record
+ element : element_type;
+ next_element, prev_element : ordered_collection;
+ end record ordered_collection_object;
+
+ type position_object is
+ record
+ the_collection : ordered_collection;
+ current_element : ordered_collection;
+ end record position_object;
+
+end package stimulus_element_ordered_collection_adt;
+
+
+
+package body stimulus_element_ordered_collection_adt is
+
+ function new_ordered_collection return ordered_collection is
+ variable result : ordered_collection := new ordered_collection_object;
+ begin
+ result.next_element := result;
+ result.prev_element := result;
+ return result;
+ end function new_ordered_collection;
+
+ procedure insert ( c : inout ordered_collection; e : in element_type ) is
+ variable current_element : ordered_collection := c.next_element;
+ variable new_element : ordered_collection;
+ begin
+ while current_element /= c
+ and key_of(current_element.element) < key_of(e) loop
+ current_element := current_element.next_element;
+ end loop;
+ -- insert new element before current_element
+ new_element := new ordered_collection_object'(
+ element => e,
+ next_element => current_element,
+ prev_element => current_element.prev_element );
+ new_element.next_element.prev_element := new_element;
+ new_element.prev_element.next_element := new_element;
+ end procedure insert;
+
+ procedure get_element ( variable p : in position; e : out element_type ) is
+ begin
+ e := p.current_element.element;
+ end procedure get_element;
+
+ procedure test_null_position ( variable p : in position; is_null : out boolean ) is
+ begin
+ is_null := p.current_element = p.the_collection;
+ end procedure test_null_position;
+
+ procedure search ( variable c : in ordered_collection; k : in key_type;
+ p : out position ) is
+ variable current_element : ordered_collection := c.next_element;
+ begin
+ while current_element /= c
+ and key_of(current_element.element) < k loop
+ current_element := current_element.next_element;
+ end loop;
+ if current_element = c or k < key_of(current_element.element) then
+ p := new position_object'(c, c); -- null position
+ else
+ p := new position_object'(c, current_element);
+ end if;
+ end procedure search;
+
+ procedure find_first ( variable c : in ordered_collection; p : out position ) is
+ begin
+ p := new position_object'(c, c.next_element);
+ end procedure find_first;
+
+ procedure advance ( p : inout position ) is
+ variable is_null : boolean;
+ begin
+ test_null_position(p, is_null);
+ if not is_null then
+ p.current_element := p.current_element.next_element;
+ end if;
+ end procedure advance;
+
+ procedure delete ( p : inout position ) is
+ variable is_null : boolean;
+ begin
+ test_null_position(p, is_null);
+ if not is_null then
+ p.current_element.next_element.prev_element
+ := p.current_element.prev_element;
+ p.current_element.prev_element.next_element
+ := p.current_element.next_element;
+ p.current_element := p.current_element.next_element;
+ end if;
+ end procedure delete;
+
+end package body stimulus_element_ordered_collection_adt;
+
+
+
+entity test_bench is
+end entity test_bench;
+
+-- end not in book
+
+
+architecture initial_test of test_bench is
+
+ use work.stimulus_types.all;
+
+ -- . . . -- component and signal declarations
+
+ -- not in book
+ signal dut_signals : real_vector(0 to stimulus_vector_length - 1);
+ -- end not in book
+
+begin
+
+ -- . . . -- instantiate design under test
+
+ stimulus_generation : process is
+
+ use work.stimulus_element_ordered_collection_adt.all;
+
+ variable stimulus_list : ordered_collection := new_ordered_collection;
+ variable next_stimulus_position : position;
+ variable next_stimulus : stimulus_element;
+ variable position_is_null : boolean;
+
+ begin
+ insert(stimulus_list, stimulus_element'(0 ns, real_vector'(0.0, 5.0, 0.0, 2.0)));
+ insert(stimulus_list, stimulus_element'(200 ns, real_vector'(3.3, 2.1, 0.0, 2.0)));
+ insert(stimulus_list, stimulus_element'(300 ns, real_vector'(3.3, 2.1, 1.1, 3.3)));
+ insert(stimulus_list, stimulus_element'(50 ns, real_vector'(3.3, 3.3, 2.2, 4.0)));
+ insert(stimulus_list, stimulus_element'(60 ns, real_vector'(5.0, 3.3, 4.0, 2.2)));
+ -- . . .
+ -- not in book
+ insert(stimulus_list, stimulus_element'(100 ns, real_vector'(0.0, 0.0, 0.0, 0.0)));
+ search(stimulus_list, 100 ns, next_stimulus_position);
+ delete(next_stimulus_position);
+ get_element(next_stimulus_position, next_stimulus);
+ -- end not in book
+ find_first(stimulus_list, next_stimulus_position);
+ loop
+ test_null_position(next_stimulus_position, position_is_null);
+ exit when position_is_null;
+ get_element(next_stimulus_position, next_stimulus);
+ wait for next_stimulus.application_time - now;
+ dut_signals <= next_stimulus.pattern;
+ advance(next_stimulus_position);
+ end loop;
+ wait;
+ end process stimulus_generation;
+
+end architecture initial_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller.vhd
new file mode 100644
index 000000000..532d65c5e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity DMA_controller is
+end entity DMA_controller;
+
+-- end not in book
+
+
+
+architecture behavioral of DMA_controller is
+
+ use work.DMA_controller_types_and_utilities.all;
+
+begin
+
+ behavior : process is
+
+ variable address_reg0, address_reg1 : word;
+ variable count_reg0, count_reg1 : word;
+ -- . . .
+
+ begin
+ -- . . .
+ address_reg0 := address_reg0 + X"0000_0004";
+ -- . . .
+ end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd
new file mode 100644
index 000000000..95d300ed0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package cpu_types is
+
+ constant word_size : positive := 16;
+
+ subtype word is bit_vector(word_size - 1 downto 0);
+
+ type status_value is ( halted, idle, fetch, mem_read, mem_write,
+ io_read, io_write, int_ack );
+
+end package cpu_types;
+
+
+
+package bit_vector_unsigned_arithmetic is
+
+ function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+end package bit_vector_unsigned_arithmetic;
+
+
+package body bit_vector_unsigned_arithmetic is
+
+ function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
+
+ alias norm1 : bit_vector(1 to bv1'length) is bv1;
+ alias norm2 : bit_vector(1 to bv2'length) is bv2;
+
+ variable result : bit_vector(1 to bv1'length);
+ variable carry : bit := '0';
+
+ begin
+ if bv1'length /= bv2'length then
+ report "arguments of different length" severity failure;
+ else
+ for index in norm1'reverse_range loop
+ result(index) := norm1(index) xor norm2(index) xor carry;
+ carry := ( norm1(index) and norm2(index) )
+ or ( carry and ( norm1(index) or norm2(index) ) );
+ end loop;
+ end if;
+ return result;
+ end function "+";
+
+end package body bit_vector_unsigned_arithmetic;
+
+
+
+
+-- code from book
+
+package DMA_controller_types_and_utilities is
+
+ alias word is work.cpu_types.word;
+ alias status_value is work.cpu_types.status_value;
+
+ alias "+" is work.bit_vector_unsigned_arithmetic."+"
+ [ bit_vector, bit_vector return bit_vector ];
+
+ -- . . .
+
+end package DMA_controller_types_and_utilities;
+
+-- end code from book
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/controller_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/controller_system.vhd
new file mode 100644
index 000000000..87f5d99ef
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/controller_system.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+package alu_types is
+
+ constant data_width : positive := 32;
+
+end package alu_types;
+
+
+package io_types is
+
+ constant data_width : positive := 32;
+
+end package io_types;
+
+
+entity controller_system is
+end entity controller_system;
+
+-- end not in book
+
+
+
+library ieee; use ieee.std_logic_1164.all;
+use work.alu_types.all, work.io_types.all;
+
+architecture structural of controller_system is
+
+ alias alu_data_width is work.alu_types.data_width;
+ alias io_data_width is work.io_types.data_width;
+
+ signal alu_in1, alu_in2,
+ alu_result : std_logic_vector(0 to alu_data_width - 1);
+ signal io_data : std_logic_vector(0 to io_data_width - 1);
+ -- . . .
+
+ -- not in book
+ -- following should not analyze: data_width not directly visible
+ -- constant test : positive := data_width;
+ -- end not in book
+
+begin
+
+ -- . . .
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/function_plus.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/function_plus.vhd
new file mode 100644
index 000000000..ddf330d0f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/function_plus.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package function_plus is
+
+ -- code from book (in text)
+
+ function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+ -- end code from book
+
+end package function_plus;
+
+
+
+package body function_plus is
+
+ -- code from book
+
+ function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
+
+ alias norm1 : bit_vector(1 to bv1'length) is bv1;
+ alias norm2 : bit_vector(1 to bv2'length) is bv2;
+
+ variable result : bit_vector(1 to bv1'length);
+ variable carry : bit := '0';
+
+ begin
+ if bv1'length /= bv2'length then
+ report "arguments of different length" severity failure;
+ else
+ for index in norm1'reverse_range loop
+ result(index) := norm1(index) xor norm2(index) xor carry;
+ carry := ( norm1(index) and norm2(index) )
+ or ( carry and ( norm1(index) or norm2(index) ) );
+ end loop;
+ end if;
+ return result;
+ end function "+";
+
+ -- end code from book
+
+end package body function_plus;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/index-ams.txt
new file mode 100644
index 000000000..9d6e7557b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/index-ams.txt
@@ -0,0 +1,28 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 11 - Aliases
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+controller_system.vhd package alu_types -- --
+-- package io_types -- --
+-- entity controller_system structural Figure 11-1
+safety_switch.vhd entity safety_switch basic Figure 11-2
+function_plus.vhd package function_plus body Figure 11-3
+DMA_controller_types_and_utilities.vhd package cpu_types -- --
+-- package bit_vector_unsigned_arithmetic body --
+-- package DMA_controller_types_and_utilities -- Figure 11-4
+DMA_controller.vhd entity DMA_controller behavioral Figure 11-5
+inline_01a.vhd entity inline_01a test Section 11.1
+inline_02.vhd entity inline_02 test Section 11.1
+inline_03a.vhd entity inline_03a test Section 11.1
+inline_04.vhd entity inline_04 test Section 11.2
+inline_05.vhd package system_types -- Section 11.2
+-- entity inline_05 test Section 11.2
+inline_06.vhd package arithmetic_ops body Section 11.2
+-- entity inline_06 test Section 11.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_function_plus.vhd entity tb_function_plus test tb_function_plus.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_01a.vhd
new file mode 100644
index 000000000..e2cda9e03
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_01a.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.mechanical_systems.all;
+
+entity inline_01a is
+
+end entity inline_01a;
+
+
+architecture test of inline_01a is
+
+ -- code from book
+
+ alias ground is electrical_ref;
+
+ --
+
+ alias anchor is translational_ref;
+
+ -- end code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_02.vhd
new file mode 100644
index 000000000..40c3f5441
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_02.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+begin
+
+
+ process_1_a : process is
+
+ -- code from book:
+
+ type register_array is array (0 to 15) of bit_vector(31 downto 0);
+
+ type register_set is record
+ general_purpose_registers : register_array;
+ program_counter : bit_vector(31 downto 0);
+ program_status : bit_vector(31 downto 0);
+ end record;
+
+ variable CPU_registers : register_set;
+
+ alias PSW is CPU_registers.program_status;
+ alias PC is CPU_registers.program_counter;
+ alias GPR is CPU_registers.general_purpose_registers;
+
+ alias SP is CPU_registers.general_purpose_registers(15);
+
+ alias interrupt_level is PSW(30 downto 26);
+
+ -- end of code from book
+
+ procedure procedure_1_b is
+
+ -- code from book:
+
+ alias SP is GPR(15);
+
+ alias interrupt_level : bit_vector(4 downto 0) is PSW(30 downto 26);
+
+ -- end of code from book
+
+ begin
+ end procedure procedure_1_b;
+
+ begin
+ wait;
+ end process process_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_03a.vhd
new file mode 100644
index 000000000..ce51a86a7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_03a.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_03a is
+
+end entity inline_03a;
+
+
+architecture test of inline_03a is
+
+ -- code from book
+
+ nature electrical_bus is
+ record
+ strobe : electrical;
+ databus : electrical_vector(0 to 7);
+ end record;
+ terminal ebus : electrical_bus;
+ quantity bus_voltages across ebus to ground;
+
+ --
+
+ alias e_strobe is bus_voltages.strobe;
+ alias e_data is bus_voltages.databus;
+
+ -- end code from book
+
+begin
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_04.vhd
new file mode 100644
index 000000000..a17356cc0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_04.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_04 is
+
+end entity inline_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04 is
+begin
+
+
+ process_2_a : process is
+
+ -- code from book:
+
+ alias binary_string is bit_vector;
+
+ variable s1, s2 : binary_string(0 to 7);
+ -- . . .
+
+ -- end of code from book
+
+ begin
+
+ s1 := "10101010";
+ s2 := "11110000";
+
+ -- code from book:
+
+ s1 := s1 and not s2;
+
+ -- end of code from book
+
+ wait;
+ end process process_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_05.vhd
new file mode 100644
index 000000000..8480a9555
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_05.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package system_types is
+
+ -- code from book
+
+ type system_status is (idle, active, overloaded);
+
+ -- end code from book
+
+end package system_types;
+
+
+
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+ -- code from book
+
+ alias status_type is work.system_types.system_status;
+
+ -- end code from book
+
+begin
+
+
+ process_2_b : process is
+
+ variable status : status_type := idle;
+
+ begin
+ wait for 10 ns;
+ status := active;
+ wait for 10 ns;
+ status := overloaded;
+
+ wait;
+ end process process_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_06.vhd
new file mode 100644
index 000000000..70b2c2bb2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_06.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package arithmetic_ops is
+
+ -- code from book
+
+ procedure increment ( bv : inout bit_vector; by : in integer := 1 );
+
+ procedure increment ( int : inout integer; by : in integer := 1 );
+
+ -- end code from book
+
+end package arithmetic_ops;
+
+
+
+package body arithmetic_ops is
+
+ procedure increment ( bv : inout bit_vector; by : in integer := 1 ) is
+ begin
+ end procedure increment;
+
+ procedure increment ( int : inout integer; by : in integer := 1 ) is
+ begin
+ end procedure increment;
+
+end package body arithmetic_ops;
+
+
+
+----------------------------------------------------------------
+
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+library util; use util.stimulus_generators.all;
+
+architecture test of inline_06 is
+
+ -- code from book
+
+ alias bv_increment is work.arithmetic_ops.increment [ bit_vector, integer ];
+
+ alias int_increment is work.arithmetic_ops.increment [ integer, integer ];
+
+ alias "*" is "and" [ bit, bit return bit ];
+
+ alias "+" is "or" [ bit, bit return bit ];
+
+ alias "-" is "not" [ bit return bit ];
+
+ alias high is std.standard.'1' [ return bit ];
+
+ -- end code from book
+
+ signal a, b, c, s : bit := '0';
+ signal test_vector : bit_vector(1 to 3);
+ signal test_high : bit := high;
+
+begin
+
+ -- code from book
+
+ s <= a * b + (-a) * c;
+
+ -- end code from book
+
+ stimulus : all_possible_values ( bv => test_vector,
+ delay_between_values => 10 ns );
+
+ (a, b, c) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd
new file mode 100644
index 000000000..fb3caad5b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all, ieee_proposed.mechanical_systems.all;
+
+entity safety_switch is
+ port ( terminal neutral : electrical;
+ terminal relay_actuator : translational );
+end entity safety_switch;
+
+-- code from book
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all, ieee_proposed.mechanical_systems.all;
+
+architecture basic of safety_switch is
+
+ quantity neutral_potential across neutral to ground;
+ quantity relay_position across relay_actuator to anchor;
+ -- ...
+
+begin
+ -- ...
+end architecture basic;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/tb_function_plus.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/tb_function_plus.vhd
new file mode 100644
index 000000000..4acb94814
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/tb_function_plus.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_function_plus is
+end entity tb_function_plus;
+
+
+architecture test of tb_function_plus is
+
+ use work.function_plus.all;
+
+begin
+
+ stimulus : process is
+ use std.textio.all;
+ variable L : line;
+ begin
+ write(L, X"0002" + X"0000");
+ writeline(output, L);
+ write(L, X"0002" + X"0005");
+ writeline(output, L);
+ write(L, X"0002" + X"FFFE");
+ writeline(output, L);
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd
new file mode 100644
index 000000000..7e29c44db
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity analog_switch is
+ port ( terminal n1, n2 : electrical;
+ signal control : in std_ulogic );
+end entity analog_switch;
+
+----------------------------------------------------------------
+
+architecture ideal of analog_switch is
+ quantity v across i through n1 to n2;
+begin
+
+ if control = '1' or control = 'H' use
+ v == 0.0;
+ else
+ i == 0.0;
+ end use;
+
+ break on control;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd
new file mode 100644
index 000000000..a8583af64
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.mechanical_systems.all;
+
+entity ball is
+end entity ball;
+
+----------------------------------------------------------------
+
+architecture bouncer of ball is
+ quantity v : velocity := 0.0;
+ quantity s : displacement := 10.0;
+ constant g : real := 9.81;
+ constant air_res : real := 0.1;
+begin
+
+ if v'above(0.0) use
+ v'dot == -g - v**2*air_res;
+ else
+ v'dot == -g + v**2*air_res;
+ end use;
+
+ reversal_tester : process is
+ begin
+ wait on s'above(0.0);
+ break v => -v when s < 0.0;
+ end process reversal_tester;
+
+ s'dot == v;
+
+end architecture bouncer;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd
new file mode 100644
index 000000000..27d999548
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+ENTITY ball_wa IS
+END ENTITY ball_wa;
+
+ARCHITECTURE simple OF ball_wa IS
+ QUANTITY v: real;
+ QUANTITY s: real;
+ CONSTANT G: real := 9.81;
+ CONSTANT Air_Res: real := 0.1;
+ SIGNAL damping: real := -0.7;
+ signal v_at_impact : real:= 0.0;
+ signal impact: boolean;
+BEGIN
+ if domain = quiescent_domain use
+ v == 0.0;
+ s == 30.0;
+ elsif impact use
+ v == damping*v_at_impact;
+ s == 0.0;
+ else
+ s'dot == v;
+ v'dot == -G;
+ end use;
+ process begin
+ wait until not s'above(0.0);
+ if v < -1.0e-9 then
+ v_at_impact <= v;
+ impact <= true, false after 1 us;
+ else
+ damping <= 0.0;
+ impact <= true;
+ end if;
+ end process;
+ break on impact;
+END architecture simple;
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd
new file mode 100644
index 000000000..94e7d9e90
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity bit_to_analog is
+ port ( d : in bit;
+ terminal a : electrical );
+end entity bit_to_analog;
+
+----------------------------------------------------------------
+
+architecture ideal of bit_to_analog is
+ constant v_low : real := 0.0;
+ constant v_high : real := 5.0;
+ signal v_in : real := 0.0;
+ quantity v_out across i_out through a to electrical_ref;
+begin
+
+ v_in <= v_high when d = '1' else v_low;
+ v_out == v_in'ramp(1.0e-9);
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd
new file mode 100644
index 000000000..06c375461
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity capacitor is
+ port ( terminal node1, node2 : electrical );
+end entity capacitor;
+
+architecture leakage of capacitor is
+ constant c : real := 1.0E-6;
+ constant r_leak : real := 10.0E6;
+ quantity v_cap across i_cap, i_leak through node1 to node2;
+begin
+ i_cap == c * v_cap'dot;
+ i_leak == v_cap / r_leak;
+end architecture leakage;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd
new file mode 100644
index 000000000..c2cba718e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity comparator is
+ port ( terminal plus_in, minus_in : electrical;
+ signal output : out std_ulogic );
+end entity comparator;
+
+----------------------------------------------------------------
+
+architecture hysteresis of comparator is
+
+ constant threshold_margin : real := 0.2;
+ quantity v_in across plus_in to minus_in;
+
+begin
+
+ comp_behavior : process is
+ variable threshold : real := threshold_margin;
+ begin
+ if v_in > threshold then
+ output <= '1' after 10 ns;
+ threshold := -threshold_margin;
+ else
+ output <= '0' after 10 ns;
+ threshold := threshold_margin;
+ end if;
+ wait on v_in'above(threshold);
+ end process comp_behavior;
+
+end architecture hysteresis;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd
new file mode 100644
index 000000000..3f5437f75
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity comparator is
+ port ( terminal a : electrical;
+ signal d : out std_ulogic );
+end entity comparator;
+
+----------------------------------------------------------------
+
+architecture ideal of comparator is
+ constant ref_voltage : real := 5.0;
+ quantity vin across a;
+begin
+
+ comparator_behavior : process is
+ begin
+ if vin > ref_voltage / 2.0 then
+ d <= '1' after 5 ns;
+ else
+ d <= '0' after 5 ns;
+ end if;
+ wait on vin'above(ref_voltage / 2.0);
+ end process comparator_behavior;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd
new file mode 100644
index 000000000..b4fa8b7ec
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity control_system is
+ port ( quantity feedback, target : in voltage;
+ quantity output : out voltage );
+end entity control_system;
+
+----------------------------------------------------------------
+
+architecture simple_feedback of control_system is
+ constant gain : real := 2.0;
+begin
+ output == gain * ( target - feedback );
+end architecture simple_feedback;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd
new file mode 100644
index 000000000..5d762e85e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity dac_12_bit is
+ port ( signal bus_in : in std_ulogic_vector (11 downto 0);
+ terminal analog_out : electrical );
+end entity dac_12_bit;
+
+----------------------------------------------------------------
+
+architecture behavioral of dac_12_bit is
+
+ constant v_max : real := 3.3;
+ signal s_out : real := 0.0;
+ quantity v_out across i_out through analog_out to electrical_ref;
+
+begin
+
+ convert : process ( bus_in ) is
+ variable sum : natural;
+ begin
+ sum := 0;
+ for i in bus_in'range loop
+ sum := sum * 2 + boolean'pos( bus_in(i) = '1' or bus_in(i) = 'H' );
+ end loop;
+ s_out <= v_max * real(sum) / real(2**12 - 1);
+ end process convert;
+
+ v_out == s_out'ramp(1.0E-6);
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd
new file mode 100644
index 000000000..aeb24de0b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee, ieee_proposed;
+use ieee.math_real.all;
+use ieee_proposed.energy_systems.all;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.thermal_systems.all;
+
+entity diode is
+ port ( terminal p, m : electrical;
+ terminal j : thermal );
+end entity diode;
+
+----------------------------------------------------------------
+
+architecture one of diode is
+
+ constant area : real := 1.0e-3;
+ constant Dn : real := 30.0; -- electron diffusion coefficient
+ constant Dp : real := 15.0; -- hole diffusion coefficient
+ constant np : real := 6.77e-5; -- minority charge density
+ constant pn : real := 6.77e-6; -- minority charge density
+ constant Ln : real := 5.47e-6; -- diffusion length for electrons
+ constant Lp : real := 12.25e-6; -- diffusion length for holes
+ quantity v across id through p to m;
+ quantity vt : voltage := 1.0; -- threshold voltage
+ quantity temp across power through j;
+
+begin
+
+ vt == temp * K / Q;
+
+ id == Q * area * (Dp * (pn / Lp) + Dn * (np / Ln)) * (exp(v / vt) - 1.0);
+
+ power == v * id;
+
+end architecture one;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/index-ams.txt
new file mode 100644
index 000000000..887fe94cb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/index-ams.txt
@@ -0,0 +1,84 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 6 - Analog Modeling Constructs
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+control_system.vhd entity control_system simple_feedback Figure 6-2
+comparator.vhd entity comparator ideal Figure 6-9
+variable_comparator.vhd entity variable_comparator ideal Figure 6-10
+transmission_line.vhd entity transmission_line abstract Figure 6-11
+transmission_line_wa.vhd entity transmission_line_wa abstract --
+inductor.vhd entity inductor ideal Figure 6-12
+piston.vhd entity piston simple Figure 6-13
+inductor-1.vhd entity inductor integral_form Figure 6-14
+moving_mass.vhd entity moving_mass behavioral Figure 6-15
+moving_mass_wa.vhd entity moving_mass_wa behavioral --
+opamp.vhd entity opamp slew_limited Figure 6-17
+quad_opamp.vhd entity quad_opamp slew_limited Figure 6-19
+quad_opamp_wa.vhd entity quad_opamp_wa slew_limited --
+bit_to_analog.vhd entity bit_to_analog ideal Figure 6-21
+std_logic_to_analog.vhd entity std_logic_to_analog ideal Figure 6-23
+opamp-1.vhd entity opamp saturating Figure 6-24
+opamp_wa-1.vhd entity opamp_wa saturating --
+resistor.vhd entity resistor ideal Figure 6-26
+capacitor.vhd entity capacitor leakage Figure 6-26
+inverting_integrator.vhd entity inverting_integrator structural Figure 6-27
+timer.vhd entity timer behavioral Figure 6-29
+ball.vhd entity ball bouncer Figure 6-30
+ball_wa.vhd entity ball_wa simple --
+analog_switch.vhd entity analog_switch ideal Figure 6-31
+pendulum.vhd entity pendulum constrained Figure 6-33
+pendulum_wa.vhd entity pendulum_wa constrained --
+triangle_waveform.vhd entity triangle_waveform ideal Figure 6-34
+triangle_waveform_wa.vhd entity triangle_waveform_wa ideal --
+comparator-1.vhd entity comparator hysteresis Figure 6-35
+dac_12_bit.vhd entity dac_12_bit behavioral Figure 6-36
+diode.vhd entity diode one Figure 6-38
+inline_01a.vhd entity inline_01a test Section 6.1
+inline_02a.vhd entity inline_02a test Section 6.1
+inline_03a.vhd entity temperature_dependent_resistor linear_approx Section 6.1
+inline_04a.vhd entity inline_04a test Section 6.2
+inline_05a.vhd entity inline_05a test Section 6.2
+inline_06a.vhd entity inline_06a test Section 6.2
+inline_07a.vhd entity battery -- Section 6.2
+-- entity ADC -- Section 6.2
+-- entity diode_thermal -- Section 6.2
+inline_08a.vhd entity inline_08a test Section 6.3
+inline_09a.vhd entity inline_09a test Section 6.4
+inline_10a.vhd entity inline_10a test Section 6.4
+inline_11a.vhd entity inline_11a test Section 6.4
+inline_12a.vhd entity inline_12a test Section 6.4
+inline_13a.vhd entity inline_13a test Section 6.4
+inline_14a.vhd entity inline_14a test Section 6.4
+inline_15a.vhd entity inline_15a test Section 6.5
+inline_16a.vhd package inline_16a_types -- Section 6.5
+-- entity seven_segment_led basic_optics Section 6.5
+-- entity inline_16a test Section 6.5
+inline_17a.vhd entity adc_with_ref signal_flow Section 6.5
+-- entity inline_17a test Section 6.5
+inline_18a.vhd entity inline_18a test Section 6.6
+inline_19a.vhd entity inline_19a test Section 6.6
+inline_20a.vhd entity inline_20a test Section 6.6
+inline_21a.vhd entity inline_21a test Section 6.7
+inline_22a.vhd entity inline_22a test Section 6.8
+inline_23a.vhd entity inline_23a test Section 6.8
+inline_24a.vhd entity inline_24a test Section 6.9
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_control_system.vhd entity tb_control_system TB_control_system control_system.vhd
+tb_comparator.vhd entity tb_comparator TB_comparator comparator.vhd
+tb_variable_comparator.vhd entity tb_variable_comparator TB_variable_comparator variable_comparator.vhd
+tb_transmission_line.vhd entity tb_transmission_line TB_transmission_line transmission_line_wa.vhd
+tb_piston.vhd entity tb_piston TB_piston piston.vhd
+tb_moving_mass.vhd entity tb_moving_mass TB_moving_mass moving_mass_wa.vhd
+tb_quad_opamp.vhd entity tb_quad_opamp TB_quad_opamp quad_opamp_wa.vhd
+tb_bit_to_analog.vhd entity tb_bit_to_analog TB_bit2analog bit_to_analog.vhd
+tb_std_logic_to_analog.vhd entity tb_std_logic_to_analog TB_std_logic2analog std_logic_to_analog.vhd
+tb_inv_integrator.vhd entity tb_inv_integrator TB_inv_integrator inverting_integrator.vhd
+tb_analog_switch.vhd entity tb_analog_switch TB_analog_switch analog_switch.vhd
+tb_triangle_waveform.vhd entity tb_triangle_waveform TB_triangle_waveform triangle_waveform.vhd
+tb_comparator-1.vhd entity tb_comparator TB_comparator comparator-1.vhd
+tb_diode.vhd entity tb_diode TB_diode diode.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd
new file mode 100644
index 000000000..15d12f215
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inductor is
+ port (terminal n1, n2: electrical);
+end entity inductor;
+
+----------------------------------------------------------------
+
+architecture integral_form of inductor is
+ constant L: inductance := 0.5;
+ quantity branch_voltage across branch_current through n1 to n2;
+begin
+ branch_current == branch_voltage'integ / L;
+end architecture integral_form;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd
new file mode 100644
index 000000000..9f3fbd258
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inductor is
+ port (terminal n1, n2: electrical);
+end entity inductor;
+
+----------------------------------------------------------------
+
+architecture ideal of inductor is
+ constant L: inductance := 0.5;
+ quantity branch_voltage across branch_current through n1 to n2;
+begin
+ branch_voltage == L* branch_current'dot;
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd
new file mode 100644
index 000000000..d6b0709b8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01a is
+
+end entity inline_01a;
+
+
+architecture test of inline_01a is
+
+ quantity capacitor_voltage : real;
+ constant capacitance : real := 1.0e-9;
+
+ subtype current is real;
+
+ -- code from book
+
+ subtype charge is real tolerance "default_charge";
+ quantity capacitor_charge : charge;
+
+ --
+
+ quantity engine_power : real tolerance "approximate_power";
+
+ --
+
+ quantity I_sense : current := 0.15; -- initial value is 150mA
+
+ --
+
+ quantity amplifier_gains : real_vector (3 downto 0) := (1.0, 1.0, 1.0, 0.5);
+
+ -- end code from book
+
+begin
+
+ -- code from book
+
+ capacitor_charge == capacitor_voltage * capacitance;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd
new file mode 100644
index 000000000..c46a6a0f0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+architecture test of inline_02a is
+begin
+
+ block_1 : block is
+
+ -- code from book
+
+ quantity input1, input2, output : real;
+ quantity amplified_input1, amplified_input2 : real;
+
+ constant gain1 : real := 2.0;
+ constant gain2 : real := 4.0;
+
+ -- end code from book
+
+ begin
+
+ -- code from book
+
+ amplified_input1 == input1 * gain1;
+ amplified_input2 == input2 * gain2;
+ output == amplified_input1 * amplified_input2;
+
+ -- end code from book
+
+ end block block_1;
+
+
+ block_2 : block is
+
+ quantity input1, input2, output : real;
+
+ constant gain1 : real := 2.0;
+ constant gain2 : real := 4.0;
+
+ begin
+
+ -- code from book
+
+ output == input1 * gain1 * input2 * gain2;
+
+ -- end code from book
+
+ end block block_2;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd
new file mode 100644
index 000000000..b73e207eb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.thermal_systems.all;
+
+entity temperature_dependent_resistor is
+ port ( terminal n1, n2 : electrical;
+ quantity temp : in temperature );
+end entity temperature_dependent_resistor;
+
+architecture linear_approx of temperature_dependent_resistor is
+ constant resistance_at_0 : real := 1.0E6;
+ constant resistance_drop_per_kelvin : real := 100.0;
+ quantity resistance : real;
+ quantity V across I through n1 to n2;
+begin
+ resistance == resistance_at_0 - temp * resistance_drop_per_kelvin;
+ V == I * resistance;
+end architecture linear_approx;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd
new file mode 100644
index 000000000..9050b0de6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+architecture test of inline_04a is
+begin
+
+ block_1 : block is
+
+ -- code from book
+
+ subtype voltage is real tolerance "low_voltage";
+ subtype current is real tolerance "low_current";
+ nature electrical is voltage across current through electrical_ref reference;
+ terminal anode, cathode : electrical;
+
+ --
+
+ subtype illuminance is real tolerance "default_illuminance";
+ subtype optic_flux is real tolerance "default_optic_flux";
+ nature radiant is illuminance across optic_flux through radiant_ref reference;
+ terminal light_bulb, light_emitting_diode : radiant;
+
+ --
+
+ nature electrical_vector is array (natural range <>) of electrical;
+ terminal a_bus : electrical_vector(1 to 8);
+
+ --
+
+ quantity light_illuminance across light_bulb;
+ quantity LED_flux through light_emitting_diode;
+
+ -- end code from book
+
+ terminal n1, n2 : electrical;
+
+ -- code from book
+
+ quantity voltage_drop across
+ inductive_current, capacitive_current, resistive_current through
+ n1 to n2;
+
+ -- end code from book
+
+ begin
+ end block block_1;
+
+
+
+ block_2 : block is
+
+ subtype voltage is real tolerance "low_voltage";
+ subtype current is real tolerance "low_current";
+ nature electrical is voltage across current through electrical_ref reference;
+
+ -- code from book
+
+ terminal anode, cathode : electrical;
+
+ --
+
+ quantity battery_voltage across battery_current through anode to cathode;
+ quantity leakage_voltage across leakage_current through anode;
+
+ -- end code from book
+
+ begin
+ end block block_2;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd
new file mode 100644
index 000000000..f0ed183a0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_05a is
+
+end entity inline_05a;
+
+
+architecture test of inline_05a is
+
+begin
+
+ block_1 : block is
+
+ constant cap : real := 1.0e-9;
+ constant rleak : real := 1.0E6;
+
+ -- code from book
+
+ terminal p1, p2 : electrical;
+ quantity vcap across icap, ileak through p1 to p2;
+
+ -- end code from book
+
+ begin
+
+ -- code from book
+
+ icap == cap * vcap'dot;
+
+ ileak == vcap / rleak;
+
+ -- end code from book
+
+ end block block_1;
+
+
+ block_2 : block is
+
+ -- code from book
+
+ nature electrical_vector is array (natural range <>) of electrical;
+ terminal a_bus : electrical_vector(1 to 8);
+ terminal signal_ground : electrical;
+
+ --
+
+ quantity bus_drops across bus_currents through a_bus to signal_ground;
+
+ --
+
+ terminal p1 : electrical_vector(0 to 3);
+ terminal p2 : electrical;
+
+ quantity v across i through p1 to p2;
+
+ --
+
+ constant tc1 : real := 1.0e-3; -- Linear temperature coefficient
+ constant tc2 : real := 1.0e-6; -- Second-order temperature coefficient
+ constant temp : real := 27.0; -- Ambient temperature
+ constant tnom : real := 50.0; -- Nominal temperature
+ constant res : real_vector := (1.0e3, 2.0e3, 4.0e3, 8.0e3); -- Nominal resistances
+
+ --
+
+ constant res_factor : real := (1.0 + tc1*(temp-tnom) + tc2*(temp-tnom)**2);
+
+ -- end code from book
+
+ begin
+
+ -- code from book
+
+ v(0) == i(0) * res(0) * res_factor;
+ v(1) == i(1) * res(1) * res_factor;
+ v(2) == i(2) * res(2) * res_factor;
+ v(3) == i(3) * res(3) * res_factor;
+
+ -- end code from book
+
+ end block block_2;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd
new file mode 100644
index 000000000..0c69a05ba
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_06a is
+
+end entity inline_06a;
+
+
+architecture test of inline_06a is
+
+ -- code from book
+
+ terminal a_bus : electrical_vector(1 to 8);
+ terminal b_bus : electrical_vector(8 downto 1);
+
+ --
+
+ quantity a_to_b_drops across a_to_b_currents through a_bus to b_bus;
+
+ --
+
+ nature electrical_bus is
+ record
+ strobe: electrical;
+ databus : electrical_vector(0 to 7);
+ end record;
+
+ terminal t1, t2 : electrical_bus;
+
+ --
+
+ quantity bus_voltages across t1 to t2;
+
+ --
+
+ terminal p1, p2 : electrical_vector(0 to 3);
+
+ quantity v across i through p1 to p2;
+
+ -- end code from book
+
+
+begin
+
+ block_1 : block is
+
+ terminal anode, cathode : electrical;
+
+ -- code from book
+
+ quantity battery_voltage tolerance "battery_tolerance" across
+ battery_current tolerance "battery_tolerance" through anode to cathode;
+
+ -- end code from book
+
+ begin
+ end block block_1;
+
+
+ block_2 : block is
+
+ terminal anode, cathode : electrical;
+
+ -- code from book
+
+ quantity battery_volts := 5.0 across
+ battery_amps := 0.0 through
+ anode to cathode;
+
+ -- end code from book
+
+ begin
+ end block block_2;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd
new file mode 100644
index 000000000..e126536d3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity battery is
+ port ( terminal anode, cathode : electrical );
+end entity battery;
+
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity ADC is
+ port ( terminal a : electrical;
+ signal d : out bit );
+end entity ADC;
+
+
+
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all, ieee_proposed.thermal_systems.all;
+
+entity diode_thermal is
+ port ( terminal p, m : electrical;
+ terminal j : thermal );
+end entity diode_thermal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd
new file mode 100644
index 000000000..9915d4fc6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_08a is
+
+end entity inline_08a;
+
+
+architecture test of inline_08a is
+
+ -- code from book
+
+ terminal bias_node : electrical;
+
+ --
+
+ subnature accurate_electrical is electrical
+ tolerance "accurate_voltage" across "accurate_current" through;
+
+ --
+
+ terminal n1, n2 : accurate_electrical;
+
+ --
+
+ quantity n1_n2_voltage across n1_n2_current through n1 to n2;
+
+ --
+
+ quantity internal_voltage : voltage tolerance n1_n2_voltage'tolerance;
+ quantity internal_current : current tolerance n1_n2_current'tolerance;
+
+ --
+
+ terminal bus_a_end, bus_b_end : electrical_vector(15 downto 0);
+ quantity bus_currents through bus_a_end to bus_b_end;
+
+ -- end code from book
+
+begin
+
+ -- code from book
+
+ bias_node'reference == 0.5;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd
new file mode 100644
index 000000000..fc3e334b6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.mechanical_systems.all;
+
+entity inline_09a is
+
+end entity inline_09a;
+
+
+architecture test of inline_09a is
+
+
+ constant R : real := 1.0e3;
+ constant k : real := 10.0;
+
+ -- code from book
+
+ terminal p, m : electrical;
+ quantity v across i through p to m;
+
+ --
+
+ terminal node1, node2 : translational;
+ quantity d across f through node1 to node2;
+
+ -- end code from book
+
+begin
+
+ -- code from book
+
+ v == i * R;
+
+ --
+
+ f == d * k;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd
new file mode 100644
index 000000000..a6c3191c0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd
@@ -0,0 +1,217 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_10a is
+
+end entity inline_10a;
+
+
+architecture test of inline_10a is
+
+ constant R : real := 10_000.0;
+ constant R1 : real := 10_000.0;
+ constant R2 : real := 10_000.0;
+
+ -- code from book
+
+ nature electrical_bus is
+ record
+ strobe: electrical;
+ databus : electrical_vector(0 to 7);
+ end record;
+
+ -- end code from book
+
+begin
+
+ block_1 : block is
+
+ -- code from book
+
+ terminal bus_end1, bus_end2 : electrical_bus;
+ quantity bus_v across bus_i through bus_end1 to bus_end2;
+
+ -- end code from book
+
+ begin
+
+ -- code from book
+
+ bus_v == bus_i * R;
+
+ -- end code from book
+
+ end block block_1;
+
+
+ block_2 : block is
+
+ terminal bus_end1, bus_end2 : electrical_bus;
+ quantity bus_v across bus_i through bus_end1 to bus_end2;
+
+ begin
+
+ -- code from book
+
+ bus_v.strobe == bus_i.strobe * R;
+ bus_v.databus(0) == bus_i.databus(0) * R;
+ bus_v.databus(1) == bus_i.databus(1) * R;
+ -- ...
+ -- not in book
+ bus_v.databus(2) == bus_i.databus(2) * R;
+ bus_v.databus(3) == bus_i.databus(3) * R;
+ bus_v.databus(4) == bus_i.databus(4) * R;
+ bus_v.databus(5) == bus_i.databus(5) * R;
+ bus_v.databus(6) == bus_i.databus(6) * R;
+ -- end not in book
+ bus_v.databus(7) == bus_i.databus(7) * R;
+
+ -- end code from book
+
+ end block block_2;
+
+
+ block_3 : block is
+
+ terminal p, m : electrical;
+ quantity v across i through p to m;
+
+ begin
+
+ -- code from book
+
+ v == i * R;
+
+ -- end code from book
+
+ end block block_3;
+
+
+ block_4 : block is
+
+ terminal p, m : electrical;
+ quantity v across i through p to m;
+
+ begin
+
+ -- code from book
+
+ v / R == i;
+
+ -- end code from book
+
+ end block block_4;
+
+
+ block_5 : block is
+
+ terminal bus_end1, bus_end2 : electrical_bus;
+ quantity bus_v across bus_i through bus_end1 to bus_end2;
+
+ begin
+
+ -- code from book
+
+ bus_v.strobe == bus_i.strobe * R;
+ bus_v.databus(0) == bus_i.databus(0) * R;
+
+ -- end code from book
+
+ bus_v.databus(1) == bus_i.databus(1) * R;
+ bus_v.databus(2) == bus_i.databus(2) * R;
+ bus_v.databus(3) == bus_i.databus(3) * R;
+ bus_v.databus(4) == bus_i.databus(4) * R;
+ bus_v.databus(5) == bus_i.databus(5) * R;
+ bus_v.databus(6) == bus_i.databus(6) * R;
+ bus_v.databus(7) == bus_i.databus(7) * R;
+
+ end block block_5;
+
+
+ block_6 : block is
+
+ terminal p1, m1, p2, m2 : electrical;
+ quantity v1 across i1 through p1 to m1;
+ quantity v2 across i2 through p2 to m2;
+
+ begin
+
+ -- code from book
+
+ i1 * R1 == i2 * R2; -- illegal
+
+ -- end code from book
+
+ end block block_6;
+
+
+ block_7 : block is
+
+ terminal p1, m1, p2, m2 : electrical;
+ quantity v1 across i1 through p1 to m1;
+ quantity v2 across i2 through p2 to m2;
+
+ begin
+
+ -- code from book
+
+ i1 * R1 == i2 * R2 tolerance "current_tolerance";
+
+ -- end code from book
+
+ end block block_7;
+
+
+ block_8 : block is
+
+ terminal p1, m1, p2, m2 : electrical;
+ quantity v1 across i1 through p1 to m1;
+ quantity v2 across i2 through p2 to m2;
+
+ begin
+
+ -- code from book
+
+ i1 * R1 == i2 * R2 tolerance i2'tolerance;
+
+ -- end code from book
+
+ end block block_8;
+
+
+ block_9 : block is
+
+ terminal p, m : electrical;
+ quantity v across i through p to m;
+
+ begin
+
+ -- code from book
+
+ v == i * R tolerance i'tolerance;
+
+ -- end code from book
+
+ end block block_9;
+
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd
new file mode 100644
index 000000000..67589bce6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_11a is
+
+end entity inline_11a;
+
+
+architecture test of inline_11a is
+
+ constant v_pos : voltage := 15.0;
+ constant v_neg : voltage := -15.0;
+ terminal input : electrical;
+ quantity v_in across input;
+ quantity v_amplified : voltage;
+ constant gain : real := 1.0;
+
+ constant threshold_voltage : voltage := 0.6;
+ constant k : real := 0.0125;
+ terminal gate, source, drain : electrical;
+ quantity vds across ids through drain to source;
+ quantity vsd across source to drain;
+ quantity vgs across gate to source;
+ quantity vgd across gate to drain;
+
+ constant r_charge : resistance := 10_000.0;
+ constant r_discharge : resistance := 10_000.0;
+ constant charging : boolean := true;
+ terminal cap, plus, minus : electrical;
+ quantity v_plus := 10.0 across plus;
+ quantity v_minus := 0.0 across minus;
+ quantity v_cap across cap;
+ quantity i_charge through plus to cap;
+ quantity i_discharge through cap to minus;
+
+begin
+
+ -- code from book
+
+ if v_in * gain > v_pos use -- incorrect
+ v_amplified == v_pos;
+ elsif v_in * gain < v_neg use -- incorrect
+ v_amplified == v_neg;
+ else
+ v_amplified == gain * v_in;
+ end use;
+
+ --
+
+ if vds'above(0.0) use -- transistor is forward biased
+ if not vgs'above(threshold_voltage) use -- cutoff region
+ ids == 0.0;
+ elsif vds'above(vgs - threshold_voltage) use -- saturation region
+ ids == 0.5 * k * (vgs - threshold_voltage)**2;
+ else -- linear/triode region
+ ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
+ end use;
+ else -- transistor is reverse biased
+ if not vgd 'above(threshold_voltage) use -- cutoff region
+ ids == 0.0;
+ elsif vsd'above(vgd - threshold_voltage) use -- saturation region
+ ids == -0.5 * k * (vgd - threshold_voltage)**2;
+ else -- linear/triode region
+ ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
+ end use;
+ end use;
+
+ --
+
+ if charging use
+ i_charge == ( v_plus - v_cap ) / r_charge;
+ i_discharge == 0.0;
+ else
+ i_charge == 0.0;
+ i_discharge == ( v_cap - v_minus ) / r_discharge;
+ end use;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd
new file mode 100644
index 000000000..a9c08e45d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_12a is
+
+end entity inline_12a;
+
+
+architecture test of inline_12a is
+
+ -- code from book
+
+ type biases is (forward, reverse);
+ type regions is (cutoff, saturation, linear);
+
+ signal bias : biases;
+ signal region : regions;
+
+ -- end code from book
+
+ constant threshold_voltage : voltage := 0.6;
+ constant k : real := 0.0125;
+ terminal gate, source, drain : electrical;
+ quantity vds across ids through drain to source;
+ quantity vsd across source to drain;
+ quantity vgs across gate to source;
+ quantity vgd across gate to drain;
+
+begin
+
+ -- code from book
+
+ case bias use
+ when forward =>
+ case region use
+ when cutoff =>
+ ids == 0.0;
+ when saturation =>
+ ids == 0.5 * k * (vgs - threshold_voltage)**2;
+ when linear =>
+ ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
+ end case;
+ when reverse =>
+ case region use
+ when cutoff =>
+ ids == 0.0;
+ when saturation =>
+ ids == -0.5 * k * (vgd - threshold_voltage)**2;
+ when linear =>
+ ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
+ end case;
+ end case;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd
new file mode 100644
index 000000000..d2a9c792f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_13a is
+
+end entity inline_13a;
+
+
+architecture test of inline_13a is
+
+ -- code from book
+
+ quantity v : voltage;
+ -- ...
+
+ -- end code from book
+
+begin
+
+ -- code from book
+
+ if v'above(0.0) and not v'above(0.6) use
+ -- ...
+ elsif v'above(0.6) and not v'above(2.7) use
+ -- ...
+ else
+ -- ...
+ end use;
+
+ --
+
+ case v use -- illegal
+ when 0.0 to 0.6 =>
+ -- ...;
+ when 0.6 to 2.7 =>
+ --...;
+ when others =>
+ --...;
+ end case;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd
new file mode 100644
index 000000000..db70d94e4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_14a is
+
+end entity inline_14a;
+
+
+architecture test of inline_14a is
+
+ terminal p : electrical;
+ quantity v across i through p;
+ constant R : resistance := 10_000.0;
+
+ type modeling_mode_type is (ideal, non_ideal);
+ constant modeling_mode : modeling_mode_type := ideal;
+
+begin
+
+ -- code from book
+
+ if modeling_mode = ideal use
+ v == i * R;
+ else
+ null; -- still need to include resistor with thermal effects!
+ end use;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd
new file mode 100644
index 000000000..639e7a4db
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.thermal_systems.all;
+
+entity inline_15a is
+
+end entity inline_15a;
+
+
+architecture test of inline_15a is
+
+ -- code from book
+
+ terminal bridge1, bridge2 : electrical;
+ quantity ambient : temperature;
+
+ -- end code from book
+
+begin
+
+ ambient == 300.0;
+
+ -- code from book
+
+ resistor1 : entity work.temperature_dependent_resistor(linear_approx)
+ port map ( n1 => bridge1, n2 => bridge2, temp => ambient );
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd
new file mode 100644
index 000000000..7cb180104
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package inline_16a_types is
+
+ subtype ILLUMINANCE is REAL tolerance "DEFAULT_ILLUMINANCE";
+ subtype OPTIC_FLUX is REAL tolerance "DEFAULT_OPTIC_FLUX";
+
+ nature RADIANT is
+ ILLUMINANCE across
+ OPTIC_FLUX through
+ RADIANT_REF reference;
+
+ subtype VOLTAGE is REAL tolerance "DEFAULT_VOLTAGE";
+ subtype CURRENT is REAL tolerance "DEFAULT_CURRENT";
+
+ nature ELECTRICAL is
+ VOLTAGE across
+ CURRENT through
+ ELECTRICAL_REF reference;
+
+ -- code from book
+
+ type illuminance_vector is array ( natural range <> ) of illuminance;
+ nature electrical_vector is array ( natural range <> ) of electrical;
+
+ -- end code from book
+
+end package inline_16a_types;
+
+
+
+use work.inline_16a_types.all;
+
+-- code from book
+
+entity seven_segment_led is
+ port ( terminal segment_anodes : electrical_vector ( 1 to 7 );
+ terminal common_cathode : electrical;
+ quantity segment_illuminances : out illuminance_vector ( 1 to 7 ) );
+end entity seven_segment_led;
+
+-- end code from book
+
+
+
+architecture basic_optics of seven_segment_led is
+begin
+end architecture basic_optics;
+
+
+
+use work.inline_16a_types.all;
+
+entity inline_16a is
+
+end entity inline_16a;
+
+
+architecture test of inline_16a is
+
+ -- code from book
+
+ terminal hour_anode_2, hour_anode_3 : electrical;
+ terminal anodes_unused : electrical_vector(1 to 5);
+ terminal hour_display_source_2, hour_display_source_3 : radiant;
+ quantity hour_illuminance_2 across hour_display_source_2;
+ quantity hour_illuminance_3 across hour_display_source_3;
+ quantity illuminances_unused : illuminance_vector(1 to 5);
+
+ -- end code from book
+
+begin
+
+ -- code from book
+
+ hour_digit : entity work.seven_segment_led(basic_optics)
+ port map ( segment_anodes(2) => hour_anode_2,
+ segment_anodes(3) => hour_anode_3,
+ segment_anodes(1) => anodes_unused(1),
+ segment_anodes(4 to 7) => anodes_unused(2 to 5),
+ common_cathode => electrical_ref,
+ segment_illuminances(2) => hour_illuminance_2,
+ segment_illuminances(3) => hour_illuminance_3,
+ segment_illuminances(1) => illuminances_unused(1),
+ segment_illuminances(4 to 7) => illuminances_unused(2 to 5) );
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd
new file mode 100644
index 000000000..08dbf5dfa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity adc_with_ref is
+ port ( quantity v_in : in voltage;
+ signal d_out : out bit;
+ quantity v_ref : in voltage := 1.0 );
+end entity adc_with_ref;
+
+-- end code from book
+
+
+architecture signal_flow of adc_with_ref is
+begin
+end architecture signal_flow;
+
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_17a is
+
+end entity inline_17a;
+
+
+architecture test of inline_17a is
+
+begin
+
+ block_1 : block is
+
+ quantity sensor_in : voltage;
+ signal sensor_data_out : bit;
+
+ begin
+
+ sensor_in == 5.0;
+
+ -- code from book
+
+ default_adc : entity work.adc_with_ref(signal_flow)
+ port map ( sensor_in, sensor_data_out );
+
+ -- end code from book
+
+ end block block_1;
+
+
+ block_2 : block is
+
+ quantity sensor_in : voltage;
+ signal sensor_data_out : bit;
+ constant v_supply : voltage := 10.0;
+
+ begin
+
+ sensor_in == 5.0;
+
+ -- code from book
+
+ fixed_adc : entity work.adc_with_ref(signal_flow)
+ port map ( sensor_in, sensor_data_out, v_ref => v_supply / 2.0 );
+
+ -- end code from book
+
+ end block block_2;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd
new file mode 100644
index 000000000..00d73909b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_18a is
+
+end entity inline_18a;
+
+
+architecture test of inline_18a is
+
+begin
+
+ process is
+ begin
+
+ -- code from book
+
+ break;
+
+ -- end code from book
+
+ wait;
+ end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd
new file mode 100644
index 000000000..2e959007e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_19a is
+
+end entity inline_19a;
+
+
+architecture test of inline_19a is
+
+ signal reset, trigger_n : std_ulogic;
+ terminal rc_ext : electrical;
+ quantity v_rc_ext across rc_ext;
+ constant half_vdd : voltage := 2.5;
+
+begin
+
+ block_1 : block is
+
+ signal q, q_n : std_ulogic;
+
+ begin
+
+ process is
+ begin
+
+ -- code from book
+
+ -- ...
+ if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
+ q <= '0'; q_n <= '1';
+ break;
+ elsif trigger_n = '0' or trigger_n = 'L' then
+ q <= '1'; q_n <= '0';
+ break;
+ end if;
+ -- ...
+
+ -- end code from book
+
+ wait;
+ end process;
+
+ end block block_1;
+
+
+ block_2 : block is
+
+ signal q, q_n : std_ulogic;
+
+ begin
+
+ process is
+ begin
+
+ -- code from book
+
+ q_n <= '1' after 20 ns;
+ break;
+
+ -- end code from book
+
+ wait;
+ end process;
+
+ end block block_2;
+
+
+ block_3 : block is
+
+ signal q, q_n : std_ulogic;
+
+ begin
+
+ process is
+ begin
+
+ -- code from book
+
+ q_n <= '1';
+ break;
+
+ -- end code from book
+
+ wait;
+ end process;
+
+ end block block_3;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd
new file mode 100644
index 000000000..8b6b66cbf
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd
@@ -0,0 +1,315 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.mechanical_systems.all;
+
+entity inline_20a is
+
+end entity inline_20a;
+
+
+architecture test of inline_20a is
+
+ signal trigger, discharge, clk : bit;
+ constant capacitance : real := 1.0e-9;
+
+begin
+
+
+ block_1 : block is
+
+ terminal cap : electrical;
+ quantity v_cap across i_cap through cap;
+
+ begin
+
+ -- code from book
+
+ i_cap == capacitance * v_cap'dot;
+
+ --
+
+ trigger_reset : process (trigger) is
+ begin
+ if trigger = '1' then
+ break v_cap => 0.0;
+ end if;
+ end process trigger_reset;
+
+ -- end code from book
+
+ end block block_1;
+
+
+ block_2 : block is
+
+ constant mass : real := 1.0;
+ terminal n : translational_v;
+ quantity v across n;
+ quantity applied_force : real;
+ quantity acceleration : real;
+
+ quantity vx, vy : real;
+
+ begin
+
+ acceleration == v'dot;
+
+ -- code from book
+
+ applied_force == mass * acceleration;
+
+ -- end code from book
+
+ process is
+ begin
+
+ -- code from book
+
+ break acceleration'integ => - acceleration'integ;
+
+ --
+
+ break vx => 0.0, vy => 0.0;
+
+ -- end code from book
+
+ wait;
+ end process;
+
+ end block block_2;
+
+
+ block_3 : block is
+
+ terminal cap : electrical;
+ quantity v_cap across i_cap through cap;
+
+ begin
+
+ i_cap == capacitance * v_cap'dot;
+
+ -- code from book
+
+ trigger_reset : process (trigger) is
+ begin
+ break v_cap => 0.0 when trigger = '1';
+ end process trigger_reset;
+
+ -- end code from book
+
+ end block block_3;
+
+
+ block_4 : block is
+
+ terminal cap : electrical;
+ quantity v_cap across i_cap through cap;
+ quantity charge : real;
+
+ begin
+
+ -- code from book
+
+ charge == capacitance * v_cap;
+
+ i_cap == charge'dot;
+
+ --
+
+ trigger_reset : process (trigger) is
+ begin
+ if trigger = '1' then
+ break for charge use v_cap => 0.0;
+ end if;
+ end process trigger_reset;
+
+ -- end code from book
+
+ end block block_4;
+
+
+ block_5 : block is
+
+ terminal cap : electrical;
+ quantity v_cap across i_cap through cap;
+ quantity charge : real;
+
+ begin
+
+ charge == capacitance * v_cap;
+ i_cap == charge'dot;
+
+ -- code from book
+
+ trigger_reset : process (trigger) is
+ begin
+ break for charge use v_cap => 0.0 when trigger = '1';
+ end process trigger_reset;
+
+ -- end code from book
+
+ end block block_5;
+
+
+ block_6 : block is
+
+ terminal cap : electrical;
+ quantity v_cap across i_cap through cap;
+ quantity cap_charge : real;
+
+ begin
+
+ cap_charge == capacitance * v_cap;
+ i_cap == cap_charge'dot;
+
+ -- code from book
+
+ discharge_cap : break cap_charge => 0.0
+ on clk when discharge = '1' and clk = '1';
+
+ -- end code from book
+
+ end block block_6;
+
+
+ block_7 : block is
+
+ terminal cap : electrical;
+ quantity v_cap across i_cap through cap;
+ quantity cap_charge : real;
+
+ begin
+
+ cap_charge == capacitance * v_cap;
+ i_cap == cap_charge'dot;
+
+ -- code from book
+
+ discharge_cap : process is
+ begin
+ break cap_charge => 0.0 when discharge = '1' and clk = '1';
+ wait on clk;
+ end process discharge_cap;
+
+ -- end code from book
+
+ end block block_7;
+
+
+ block_8 : block is
+
+ terminal cap : electrical;
+ quantity v_cap across i_cap through cap;
+ quantity charge : real;
+
+ begin
+
+ charge == capacitance * v_cap;
+ i_cap == charge'dot;
+
+ -- code from book
+
+ trigger_reset : break for charge use v_cap => 0.0 when trigger = '1';
+
+ -- end code from book
+
+ end block block_8;
+
+
+ block_9 : block is
+
+ terminal cap : electrical;
+ quantity v_cap across i_cap through cap;
+ quantity charge : real;
+
+ begin
+
+ charge == capacitance * v_cap;
+ i_cap == charge'dot;
+
+ -- code from book
+
+ trigger_reset : process is
+ begin
+ break for charge use v_cap => 0.0 when trigger = '1';
+ wait on trigger;
+ end process trigger_reset;
+
+ -- end code from book
+
+ end block block_9;
+
+
+ block_10 : block is
+
+ quantity q : real;
+ constant new_q : real := 0.0;
+
+ begin
+
+ -- code from book
+
+ useless_break : break q => new_q when q < 0.0 or q > 3.0;
+
+ -- end code from book
+
+ end block block_10;
+
+
+ block_11 : block is
+
+ quantity q : real;
+ constant new_q : real := 0.0;
+
+ begin
+
+ -- code from book
+
+ useless_break : process is
+ begin
+ break q => new_q when q < 0.0 or q > 3.0;
+ wait;
+ end process useless_break;
+
+ -- end code from book
+
+ end block block_11;
+
+
+ block_12 : block is
+
+ quantity q : real;
+ constant new_q : real := 0.0;
+
+ begin
+
+ -- code from book
+
+ correct_break : break q => new_q on q'above(0.0), q'above(3.0)
+ when q < 0.0 or q > 3.0;
+
+ -- end code from book
+
+ end block block_12;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd
new file mode 100644
index 000000000..81f5e4fe3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.mechanical_systems.all;
+
+entity inline_21a is
+
+end entity inline_21a;
+
+
+architecture test of inline_21a is
+
+ -- code from book
+
+ quantity d : displacement;
+
+ limit d : displacement with 0.001;
+
+ --
+
+ quantity drive_shaft_av, axle_av, wheel_av : angular_velocity;
+
+ --
+
+ limit drive_shaft_av, axle_av, wheel_av : angular_velocity with 0.01;
+
+ --
+
+ limit all : angular_velocity with 0.01;
+
+ --
+
+ quantity input, preamp_out, mixer_out, agc_out : voltage;
+
+ limit input, preamp_out : voltage with 1.0E-9;
+ limit others : voltage with 1.0E-7;
+
+ --
+
+ terminal bus1 : electrical_vector(1 to 8);
+ terminal bus2 : electrical_vector(1 to 8);
+ quantity v_bus across bus1 to bus2;
+ limit v_bus : voltage_vector with 1.0E-3;
+
+ -- end code from book
+
+begin
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd
new file mode 100644
index 000000000..e53a30cc5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_22a is
+
+end entity inline_22a;
+
+
+architecture test of inline_22a is
+
+ signal clock : bit;
+ quantity q : real;
+ signal sample : integer;
+ signal average : real;
+
+ quantity v_in : real;
+ constant v_il : real := 0.8;
+ constant v_ih : real := 2.0;
+ signal data : std_ulogic;
+
+begin
+
+ -- code from book
+
+ sampler : process ( clock ) is
+ constant num_levels : real := 64.0;
+ constant max_val : real := 5.0;
+ begin
+ if clock = '1' then
+ sample <= integer(q * num_levels / max_val) after 5 ns;
+ end if;
+ end process sampler;
+
+ --
+
+ compute_running_average : process (clock) is
+ variable num_samples : integer := 0;
+ variable total : real := 0.0;
+ variable running_average : real := 0.0;
+ begin
+ if clock = '1' then
+ total := total + q;
+ num_samples := num_samples + 1;
+ running_average := total / real(num_samples);
+ average <= running_average after 5 ns;
+ end if;
+ end process compute_running_average;
+
+ --
+
+ analog_to_std_logic : process (v_in'above(v_il), v_in'above(v_ih)) is
+ begin
+ if not v_in'above(v_il) then
+ data <= '0';
+ elsif v_in'above(v_ih) then
+ data <= '1';
+ else
+ data <= 'X';
+ end if;
+ end process analog_to_std_logic;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd
new file mode 100644
index 000000000..88a8025c6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_23a is
+
+end entity inline_23a;
+
+
+architecture test of inline_23a is
+
+ signal digital_level : integer;
+ constant num_levels : integer := 63;
+ constant max_voltage : real := 10.0;
+
+begin
+
+ block_1 : block is
+
+ quantity analog_voltage : real;
+
+ begin
+
+ -- code from book
+
+ analog_voltage == real(digital_level) / real(num_levels) * max_voltage;
+
+ -- end code from book
+
+ end block block_1;
+
+
+ block_2 : block is
+
+ signal real_digital_level : real;
+ quantity analog_voltage : real;
+
+ begin
+
+ -- code from book
+
+ real_digital_level <= real(digital_level);
+ analog_voltage == real_digital_level'ramp(1.0E-6) / real(num_levels) * max_voltage;
+
+ -- end code from book
+
+ end block block_2;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd
new file mode 100644
index 000000000..66f0030fa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.mechanical_systems.all;
+
+entity inline_24a is
+
+end entity inline_24a;
+
+
+architecture test of inline_24a is
+
+ -- code from book
+
+ terminal plus, minus : electrical;
+ quantity v across i through plus to minus;
+
+ terminal shaft : rotational_v;
+ quantity applied_torque through shaft;
+
+ -- end code from book
+
+begin
+
+ -- code from book
+
+ applied_torque == v * i;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd
new file mode 100644
index 000000000..3edb97525
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inverting_integrator is
+ port ( terminal input, output : electrical );
+end entity inverting_integrator;
+
+----------------------------------------------------------------
+
+architecture structural of inverting_integrator is
+ terminal internal : electrical;
+begin
+
+ r1 : entity work.resistor(ideal)
+ port map ( node1 => input, node2 => internal ) ;
+
+ c1 : entity work.capacitor(leakage)
+ port map ( node1 => internal, node2 => output );
+
+ amp : entity work.opamp(slew_limited)
+ port map ( plus_in => electrical_ref, minus_in => internal,
+ output => output );
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd
new file mode 100644
index 000000000..586eaef48
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.mechanical_systems.all;
+
+entity moving_mass is
+ port ( terminal external_attachment : translational );
+end entity moving_mass;
+
+----------------------------------------------------------------
+
+architecture behavioral of moving_mass is
+ constant mass : real := 10.0;
+ constant stiffness : real := 2.0;
+ constant damping : real := 5.0;
+ quantity position across driving_force through external_attachment;
+ quantity velocity : real;
+begin
+ position == velocity'integ;
+ mass * velocity'dot == driving_force - stiffness * velocity'integ - damping * velocity
+ tolerance velocity'tolerance;
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd
new file mode 100644
index 000000000..fc897f5be
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.mechanical_systems.all;
+
+entity moving_mass_wa is
+ port ( terminal external_attachment : translational );
+end entity moving_mass_wa;
+
+----------------------------------------------------------------
+
+architecture behavioral of moving_mass_wa is
+ constant mass : real := 10.0;
+ constant stiffness : real := 2.0;
+ constant damping : real := 5.0;
+ quantity position across driving_force through external_attachment;
+ quantity velocity : real;
+begin
+ velocity == position'dot;
+ driving_force == mass*velocity'dot + damping*velocity + stiffness*position;
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd
new file mode 100644
index 000000000..a2a26fe2c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity opamp is
+ port ( terminal positive_supply, negative_supply : electrical;
+ terminal plus_in, minus_in, output : electrical );
+end entity opamp;
+
+----------------------------------------------------------------
+
+architecture saturating of opamp is
+
+ constant gain : real := 50.0;
+ quantity v_pos across positive_supply;
+ quantity v_neg across negative_supply;
+ quantity v_in across plus_in to minus_in;
+ quantity v_out across i_out through output;
+ quantity v_amplified : voltage;
+
+begin
+
+ if v_in'above(v_pos / gain) use
+ v_amplified == v_pos;
+ elsif not v_in'above(v_neg / gain) use
+ v_amplified == v_neg;
+ else
+ v_amplified == gain * v_in;
+ end use;
+
+ break on v_in'above(v_pos/gain), v_in'above(v_neg/gain);
+
+ v_out == v_amplified'slew(1.0e6,-1.0e6);
+
+end architecture saturating;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd
new file mode 100644
index 000000000..009e061ba
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity opamp is
+ port ( terminal plus_in, minus_in, output : electrical );
+end entity opamp;
+
+----------------------------------------------------------------
+
+architecture slew_limited of opamp is
+
+ constant gain : real := 50.0;
+ quantity v_in across plus_in to minus_in;
+ quantity v_out across i_out through output;
+ quantity v_amplified : voltage;
+
+begin
+
+ v_amplified == gain * v_in;
+
+ v_out == v_amplified'slew(1.0e6,-1.0e6);
+
+end architecture slew_limited;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd
new file mode 100644
index 000000000..b5e7aa759
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity opamp_wa is
+ port ( terminal positive_supply, negative_supply : electrical;
+ terminal plus_in, minus_in, output : electrical );
+end entity opamp_wa;
+
+----------------------------------------------------------------
+
+architecture saturating of opamp_wa is
+
+ constant gain : real := 50.0;
+ quantity v_pos := 15.0 across positive_supply;
+ quantity v_neg := -15.0 across negative_supply;
+ quantity v_in across plus_in to minus_in;
+ quantity v_out across i_out through output;
+ quantity v_amplified : voltage;
+
+begin
+
+ if v_in'above(v_pos / gain) use
+ v_amplified == v_pos;
+ elsif not v_in'above(v_neg / gain) use
+ v_amplified == v_neg;
+ else
+ v_amplified == gain * v_in;
+ end use;
+
+ break on v_in'above(v_pos/gain), v_in'above(v_neg/gain);
+
+ v_out == v_amplified; -- 'slew(1.0e6,-1.0e6);
+
+end architecture saturating;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd
new file mode 100644
index 000000000..e78288068
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+
+entity pendulum is
+end entity pendulum;
+
+----------------------------------------------------------------
+
+architecture constrained of pendulum is
+
+ constant mass : real := 10.0;
+ constant arm_length : real := 5.0;
+ constant pin_angle : real := 0.25 * math_pi;
+ constant pin_distance : real := 2.5;
+ constant damping : real := 1.0;
+ constant gravity : real := 9.81;
+ constant short_length : real := arm_length - pin_distance;
+ quantity phi : real := -0.5*math_pi;
+ quantity current_length : real := arm_length;
+
+begin
+
+ if phi'above(pin_angle) use
+ current_length == short_length;
+ else
+ current_length == arm_length;
+ end use;
+
+ break phi'dot => phi'dot * arm_length/short_length
+ when phi'above(pin_angle);
+
+ break phi'dot => phi'dot * short_length/arm_length
+ when not phi'above(pin_angle);
+
+ mass * current_length * phi'dot'dot
+ == - mass * gravity * sin(phi) - damping * current_length * phi'dot;
+
+end architecture constrained;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd
new file mode 100644
index 000000000..bf3381127
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- Pendulum example. Look at velocity quantity, phi_dot, to see effects of
+-- discontinuity. Run simulation for about 20 sec.
+
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+library ieee; use ieee.math_real.all;
+
+entity pendulum_wa is
+end entity pendulum_wa;
+
+-- ======================================================================================
+-- constrained architecture
+-- ======================================================================================
+architecture constrained of pendulum_wa is
+ constant mass : real := 10.0;
+ constant arm_length : real := 5.0;
+ constant pin_angle : real := 0.25*math_pi;
+ constant pin_distance : real := 2.5;
+ constant damping : real := 1.0;
+ constant gravity : real := 9.81;
+ constant short_length : real := arm_length-pin_distance;
+ quantity phi : real := -0.5*math_pi;
+ signal current_length : real := arm_length;
+ quantity acceleration, velocity : real;
+ quantity phi_dot : real;
+ signal pin_thresh : boolean;
+ signal phi_dot_at_pin_thresh : real := 0.0;
+ signal transition : boolean := false;
+
+begin
+ if domain = quiescent_domain use
+ phi == -0.5*math_pi;
+ phi'dot == 0.0;
+ elsif transition and pin_thresh use
+ phi == pin_angle;
+ phi'dot == phi_dot_at_pin_thresh*arm_length/short_length;
+ elsif transition and not pin_thresh use
+ phi == pin_angle;
+ phi'dot == phi_dot_at_pin_thresh*short_length/arm_length;
+ else
+ mass*acceleration == -mass*gravity*sin(phi)-damping*velocity;
+ velocity == current_length*phi'dot;
+ end use;
+
+ acceleration == velocity'dot;
+ phi_dot == phi'dot;
+
+ pin_thresh <= phi'above(pin_angle);
+
+ process
+ begin
+ wait on pin_thresh;
+ phi_dot_at_pin_thresh <= phi_dot;
+ if pin_thresh = true then
+ current_length <= short_length;
+ transition <= true;
+ else
+ current_length <= arm_length;
+ transition <= true;
+ end if;
+ wait for 1 us;
+ transition <= false;
+ end process;
+ break on pin_thresh;
+ break on transition;
+
+end architecture constrained;
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd
new file mode 100644
index 000000000..50f9db8c4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.mechanical_systems.all;
+
+entity piston is
+ port ( terminal motion : translational );
+end entity piston;
+
+--------------------------------------------------------------
+
+architecture simple of piston is
+ constant mass : real := 10.0;
+ quantity resultant_displacement across applied_force through motion;
+begin
+ applied_force == mass * resultant_displacement'dot'dot;
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd
new file mode 100644
index 000000000..0bf267f9c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity quad_opamp is
+ port ( terminal plus_in, minus_in, output : electrical_vector(1 to 4) );
+end entity quad_opamp;
+
+----------------------------------------------------------------
+
+architecture slew_limited of quad_opamp is
+
+ constant gain : real := 50.0;
+ quantity v_in across plus_in to minus_in;
+ quantity v_out across i_out through output;
+ quantity v_amplified : real_vector(1 to 4);
+
+begin
+
+ v_amplified(1) == gain * v_in(1);
+ v_amplified(2) == gain * v_in(2);
+ v_amplified(3) == gain * v_in(3);
+ v_amplified(4) == gain * v_in(4);
+
+ real_vector(v_out) == v_amplified'slew(1.0e6,-1.0e6);
+
+end architecture slew_limited;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd
new file mode 100644
index 000000000..221b3e97f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity quad_opamp_wa is
+ port (terminal n1, n2, output : electrical_vector(1 to 4));
+end entity quad_opamp_wa ;
+
+----------------------------------------------------------------
+
+architecture slew_limited of quad_opamp_wa is
+
+ quantity vin across n1 to n2;
+ quantity vout across iout through output;
+ quantity vamp1 : real;
+ quantity vamp2 : real;
+ quantity vamp3 : real;
+ quantity vamp4 : real;
+ constant gain : real := 50.0;
+
+begin
+
+ vamp1 == gain*vin(1);
+ vamp2 == gain*vin(2);
+ vamp3 == gain*vin(3);
+ vamp4 == gain*vin(4);
+
+ vout(1) == vamp1'slew(1.0e6,-1.0e6);
+ vout(2) == vamp2'slew(1.0e6,-1.0e6);
+ vout(3) == vamp3'slew(1.0e6,-1.0e6);
+ vout(4) == vamp4'slew(1.0e6,-1.0e6);
+
+end architecture slew_limited ;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd
new file mode 100644
index 000000000..2339f3344
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+ port ( terminal node1, node2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+ constant R : real := 1000.0;
+ quantity v across i through node1 to node2;
+begin
+ v == i * R;
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd
new file mode 100644
index 000000000..a469e16a2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity std_logic_to_analog is
+ port ( d : in std_logic;
+ terminal a : electrical );
+end entity std_logic_to_analog;
+
+----------------------------------------------------------------
+
+architecture ideal of std_logic_to_analog is
+ constant v_low : real := 0.0;
+ constant v_high : real := 5.0;
+ constant v_unknown : real := 2.0;
+ signal v_in : real := 0.0;
+ quantity v_out across i_out through a to electrical_ref;
+begin
+
+ v_in <= v_high when d = '1' or d = 'H' else
+ v_low when d = '0' or d = 'L' else
+ v_unknown;
+
+ v_out == v_in'slew(2.0e+9, -1.0e+9);
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd
new file mode 100644
index 000000000..08cc1b7d6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity tb_analog_switch is
+end tb_analog_switch;
+
+architecture TB_analog_switch of tb_analog_switch is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_ana_src : electrical;
+ terminal in_switch : electrical;
+ signal clock_out : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ vdc1 : entity work.v_constant(ideal)
+ generic map(
+ level => 1.0
+ )
+ port map(
+ pos => in_ana_src,
+ neg => ELECTRICAL_REF
+ );
+ Clk1 : entity work.clock(ideal)
+ generic map(
+ period => 10.0ms
+ )
+ port map(
+ clk_out => clock_out
+ );
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 100.0
+ )
+ port map(
+ p1 => in_ana_src,
+ p2 => in_switch
+ );
+ swtch : entity work.analog_switch(ideal)
+ port map(
+ n1 => in_switch,
+ n2 => ELECTRICAL_REF,
+ control => clock_out
+ );
+end TB_analog_switch;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd
new file mode 100644
index 000000000..2c3cb18ef
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_bit_to_analog is
+end tb_bit_to_analog;
+
+architecture TB_bit2analog of tb_bit_to_analog is
+ -- Component declarations
+ -- Signal declarations
+ terminal ana_out : electrical;
+ signal ina : bit;
+ signal ina_tmp : std_logic;
+
+begin
+ -- Signal assignments
+ ina <= To_bit(ina_tmp); -- convert std_logic to bit
+ -- Component instances
+ d2a1 : entity work.bit_to_analog(ideal)
+ port map(
+ d => ina, -- bit type pin
+ a => ana_out
+ );
+ clk1 : entity work.clock_duty(ideal)
+ generic map(
+ off_time => 2 ms,
+ on_time => 1 ms
+ )
+ port map(
+ CLOCK_OUT => ina_tmp -- std_logic type pin
+ );
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => ana_out,
+ p2 => electrical_ref
+ );
+end TB_bit2analog;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd
new file mode 100644
index 000000000..b3e3ef248
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_comparator is
+end tb_comparator;
+
+architecture TB_comparator of tb_comparator is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src : electrical;
+ signal cmp_out : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_sine(ideal)
+ generic map(
+ freq => 100.0,
+ amplitude => 5.0
+ )
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+ C1 : entity work.comparator(hysteresis)
+ port map(
+ plus_in => in_src,
+ minus_in => electrical_ref,
+ output => cmp_out
+ );
+end TB_comparator;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd
new file mode 100644
index 000000000..33d8194df
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity tb_comparator is
+end tb_comparator;
+
+architecture TB_comparator of tb_comparator is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src : electrical;
+ signal cmp_out : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_sine(ideal)
+ generic map(
+ freq => 100.0,
+ amplitude => 5.0
+ )
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+ C1 : entity work.comparator(ideal)
+ port map(
+ a => in_src,
+ d => cmp_out
+ );
+end TB_comparator;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd
new file mode 100644
index 000000000..a4da70d2e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed;
+
+entity tb_control_system is
+end tb_control_system;
+
+architecture TB_control_system of tb_control_system is
+ -- Component declarations
+ -- Signal declarations
+ quantity in_src, fb : real;
+ quantity output : real;
+begin
+ -- Signal assignments
+ -- Component instances
+ src3 : entity work.src_sine(ideal)
+ generic map(
+ freq => 100.0,
+ amplitude => 1.0
+ )
+ port map(
+ output => in_src
+ );
+ XCMP12 : entity work.control_system(simple_feedback)
+ port map(
+ target => in_src,
+ output => output,
+ feedback => fb
+ );
+ gain1 : entity work.gain(simple)
+ generic map(
+ k => 1.0
+ )
+ port map (
+ input => output,
+ output => fb
+ );
+end TB_control_system;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd
new file mode 100644
index 000000000..05c20a95b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.thermal_systems.all;
+entity tb_diode is
+end tb_diode;
+
+architecture TB_diode of tb_diode is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src : electrical;
+ terminal r1_d1 : electrical;
+ terminal temp_in : thermal;
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_sine(ideal)
+ generic map(
+ freq => 100.0,
+ amplitude => 5.0
+ )
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+ tmp : entity work.TempConstant(ideal)
+ generic map(
+ level => 100.0
+ )
+ port map(
+ th1 => temp_in,
+ th2 => thermal_REF
+ );
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 100.0
+ )
+ port map(
+ p1 => in_src,
+ p2 => r1_d1
+ );
+ D1 : entity work.diode(one)
+ port map(
+ p => r1_d1,
+ m => electrical_ref,
+ j => temp_in
+ );
+end TB_diode;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd
new file mode 100644
index 000000000..bcc236dc7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_inv_integrator is
+end tb_inv_integrator;
+
+architecture TB_inv_integrator of tb_inv_integrator is
+ -- Component declarations
+ -- Signal declarations
+ terminal vin : electrical;
+ terminal vout : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ v1 : entity work.v_sine(ideal)
+ generic map(
+ amplitude => 0.2,
+ freq => 1.0e3
+ )
+ port map(
+ pos => vin,
+ neg => ELECTRICAL_REF
+ );
+ inverting_integ1 : entity work.inverting_integrator(structural)
+ port map(
+ output => vout,
+ input => vin
+ );
+ RLoad : entity work.load_res(ideal)
+ generic map(
+ R => 100.0
+ )
+ port map(
+ node1 => vout,
+ node2 => ELECTRICAL_REF
+ );
+end TB_inv_integrator;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd
new file mode 100644
index 000000000..8a44b78bb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_moving_mass is
+end tb_moving_mass;
+
+architecture TB_moving_mass of tb_moving_mass is
+ -- Component declarations
+ -- Signal declarations
+ terminal msd_discrete, msd_mdl : translational;
+begin
+ -- Signal assignments
+ -- Component instances
+ mass1 : entity work.mass_t(ideal)
+ generic map(
+ m => 10.0
+ )
+ port map(
+ trans1 => msd_discrete
+ );
+ spring2 : entity work.spring_t(linear)
+ generic map(
+ k => 2.0
+ )
+ port map(
+ trans1 => msd_discrete,
+ trans2 => TRANSLATIONAL_REF
+ );
+ damper1 : entity work.damper_t(ideal)
+ generic map(
+ d => 5.0
+ )
+ port map(
+ trans1 => msd_discrete,
+ trans2 => TRANSLATIONAL_REF
+ );
+ Force1 : entity work.ForcePulse_t(ideal)
+ generic map(
+ initial => 0.0,
+ pulse => 20.0e-3,
+ ti2p => 1 ms,
+ tp2i => 1 ms,
+ delay => 1 ms,
+ width => 1 sec,
+ period => 3 sec
+ )
+ port map(
+ trans_pos => msd_discrete,
+ trans_neg => TRANSLATIONAL_REF
+ );
+ Force2 : entity work.ForcePulse_t(ideal)
+ generic map(
+ initial => 0.0,
+ pulse => 20.0e-3,
+ ti2p => 1 ms,
+ tp2i => 1 ms,
+ delay => 1 ms,
+ width => 1 sec,
+ period => 3 sec
+ )
+ port map(
+ trans_pos => msd_mdl,
+ trans_neg => TRANSLATIONAL_REF
+ );
+ moving_mass4 : entity work.moving_mass_wa(behavioral)
+ port map(
+ external_attachment => msd_mdl
+ );
+end TB_moving_mass;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd
new file mode 100644
index 000000000..5f238e443
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_piston is
+end tb_piston;
+
+architecture TB_piston of tb_piston is
+ -- Component declarations
+ -- Signal declarations
+ terminal n1, n2 : translational;
+begin
+ -- Signal assignments
+ -- Component instances
+ Force1 : entity work.ForcePulse_t(ideal)
+ generic map(
+ initial => 0.0,
+ pulse => 20.0e-3,
+ ti2p => 1 ms,
+ tp2i => 1 ms,
+ delay => 1 ms,
+ width => 1 sec,
+ period => 3 sec
+ )
+ port map(
+ trans_pos => n1,
+ trans_neg => TRANSLATIONAL_REF
+ );
+ mass1 : entity work.piston(simple)
+ port map(
+ motion => n1
+ );
+ Force2 : entity work.ForcePulse_t(ideal)
+ generic map(
+ initial => 0.0,
+ pulse => 20.0e-3,
+ ti2p => 1 ms,
+ tp2i => 1 ms,
+ delay => 1 ms,
+ width => 1 sec,
+ period => 3 sec
+ )
+ port map(
+ trans_pos => n2,
+ trans_neg => TRANSLATIONAL_REF
+ );
+ mass2 : entity work.mass_t(ideal)
+ generic map(
+ m => 10.0
+ )
+ port map(
+ trans1 => n2
+ );
+end TB_piston;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd
new file mode 100644
index 000000000..dc55ca3d7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd
@@ -0,0 +1,162 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_quad_opamp is
+end tb_quad_opamp ;
+
+architecture TB_quad_opamp of tb_quad_opamp is
+ -- Component declarations
+ -- Signal declarations
+ terminal amp_out : electrical_vector(1 to 4);
+ terminal inm : electrical_vector(1 to 4);
+ terminal inp : electrical_vector(1 to 4);
+begin
+ -- Signal assignments
+ -- Component instances
+ opamp_quad_slew1 : entity work.quad_opamp_wa(slew_limited)
+ port map(
+ n1 => inp,
+ n2 => inm,
+ output => amp_out
+ );
+ R4 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => ELECTRICAL_REF,
+ p2 => amp_out(4)
+ );
+ v4 : entity work.v_pulse(ideal)
+ generic map(
+ period => 200 us,
+ width => 100 us,
+ delay => 10 us,
+ tp2i => 0.9 us,
+ ti2p => 0.70 us,
+ pulse => 5.0
+ )
+ port map(
+ pos => inm(1),
+ neg => ELECTRICAL_REF
+ );
+ R5 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => ELECTRICAL_REF,
+ p2 => amp_out(3)
+ );
+ R6 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => ELECTRICAL_REF,
+ p2 => amp_out(2)
+ );
+ R7 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => ELECTRICAL_REF,
+ p2 => amp_out(1)
+ );
+ v5 : entity work.v_pulse(ideal)
+ generic map(
+ pulse => 5.0,
+ ti2p => 0.70 us,
+ tp2i => 0.9 us,
+ delay => 10 us,
+ width => 100 us,
+ period => 200 us
+ )
+ port map(
+ pos => inm(2),
+ neg => ELECTRICAL_REF
+ );
+ v6 : entity work.v_pulse(ideal)
+ generic map(
+ pulse => 5.0,
+ ti2p => 0.70 us,
+ tp2i => 0.9 us,
+ delay => 10 us,
+ width => 100 us,
+ period => 200 us
+ )
+ port map(
+ pos => inm(3),
+ neg => ELECTRICAL_REF
+ );
+ v7 : entity work.v_pulse(ideal)
+ generic map(
+ pulse => 5.0,
+ ti2p => 0.70 us,
+ tp2i => 0.9 us,
+ delay => 10 us,
+ width => 100 us,
+ period => 200 us
+ )
+ port map(
+ pos => inm(4),
+ neg => ELECTRICAL_REF
+ );
+ R8 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e-3
+ )
+ port map(
+ p1 => ELECTRICAL_REF,
+ p2 => inp(1)
+ );
+ R9 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e-3
+ )
+ port map(
+ p1 => ELECTRICAL_REF,
+ p2 => inp(2)
+ );
+ R10 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e-3
+ )
+ port map(
+ p1 => ELECTRICAL_REF,
+ p2 => inp(3)
+ );
+ R11 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e-3
+ )
+ port map(
+ p1 => ELECTRICAL_REF,
+ p2 => inp(4)
+ );
+end TB_quad_opamp ;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd
new file mode 100644
index 000000000..1059d6c15
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_std_logic_to_analog is
+end tb_std_logic_to_analog;
+
+architecture TB_std_logic2analog of tb_std_logic_to_analog is
+ -- Component declarations
+ -- Signal declarations
+ terminal ana_out : electrical ;
+ signal ina : std_logic ;
+
+begin
+ -- Signal assignments
+ -- Component instances
+ d2a1 : entity work.std_logic_to_analog(ideal)
+ port map(
+ d => ina, -- bit type pin
+ a => ana_out
+ );
+ clk1 : entity work.clock_duty(ideal)
+ generic map(
+ off_time => 2 ms,
+ on_time => 1 ms
+ )
+ port map(
+ CLOCK_OUT => ina -- std_logic type pin
+ );
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => ana_out,
+ p2 => electrical_ref
+ );
+end TB_std_logic2analog;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd
new file mode 100644
index 000000000..c535fd771
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_transmission_line is
+
+end tb_transmission_line;
+
+architecture TB_transmission_line of tb_transmission_line is
+ quantity in_src, line_out : voltage;
+ -- Component declarations
+ -- Signal declarations
+begin
+ -- Signal assignments
+ -- Component instances
+ q1 : entity work.src_pulse(ideal)
+ generic map(
+ initial => 0.0,
+ pulse => 1.0e1,
+ ti2p => 1.0e-12,
+ tp2i => 1.0e-12,
+ delay => 1 ps,
+ width => 20 ns,
+ period => 50 ns
+ )
+ port map(
+ output => in_src
+ );
+
+ T1 : entity work.transmission_line_wa(abstract)
+ port map(
+ vin => in_src,
+ vout => line_out
+ );
+
+end TB_transmission_line;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd
new file mode 100644
index 000000000..ce33af878
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity tb_triangle_waveform is
+end tb_triangle_waveform;
+
+architecture TB_triangle_waveform of tb_triangle_waveform is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.triangle_waveform_wa(ideal)
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e9
+ )
+ port map(
+ p1 => in_src,
+ p2 => ELECTRICAL_REF
+ );
+end TB_triangle_waveform;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd
new file mode 100644
index 000000000..9dc43671a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity tb_variable_comparator is
+end tb_variable_comparator;
+
+architecture TB_variable_comparator of tb_variable_comparator is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src, v_ref : electrical;
+ signal cmp_out : std_logic;
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_sine(ideal)
+ generic map(
+ freq => 100.0,
+ amplitude => 5.0
+ )
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+ C1 : entity work.variable_comparator(ideal)
+ port map(
+ a => in_src,
+ ref => electrical_ref,
+ d => cmp_out
+ );
+end TB_variable_comparator;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd
new file mode 100644
index 000000000..8b151da24
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity timer is
+ port ( signal trigger_n, reset : in std_ulogic; signal q : out std_ulogic;
+ terminal rc_ext : electrical );
+end entity timer;
+
+----------------------------------------------------------------
+
+architecture behavioral of timer is
+
+ constant half_vdd : real := 2.5;
+ constant clamp_on_resistance : real := 0.01;
+ constant clamp_off_resistance : real := 10.0E6;
+ quantity v_rc_ext across i_clamp through rc_ext to electrical_ref;
+ signal q_n : std_ulogic := '1';
+
+begin
+
+ if q_n = '1' use
+ i_clamp == v_rc_ext / clamp_on_resistance;
+ else
+ i_clamp == v_rc_ext / clamp_off_resistance;
+ end use;
+
+ timer_state : process ( trigger_n, reset, v_rc_ext'above(half_vdd) ) is
+ begin
+ if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
+ q <= '0'; q_n <= '1';
+ elsif trigger_n = '0' or trigger_n = 'L' then
+ q <= '1'; q_n <= '0';
+ end if;
+ end process timer_state;
+
+ clamp_change : process ( q_n ) is
+ begin
+ break;
+ end process clamp_change;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd
new file mode 100644
index 000000000..0206b7738
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity transmission_line is
+ port ( quantity vin : in voltage;
+ quantity vout : out voltage);
+end entity transmission_line;
+
+----------------------------------------------------------------
+
+architecture abstract of transmission_line is
+ constant propagation_time : real := 2.5E-9;
+ constant attenuation : real := 0.8;
+begin
+ vout == attenuation * vin'delayed(propagation_time);
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd
new file mode 100644
index 000000000..accb3937b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity transmission_line_wa is
+ port ( quantity vin : in voltage;
+ quantity vout : out voltage);
+end entity transmission_line_wa;
+
+----------------------------------------------------------------
+
+architecture abstract of transmission_line_wa is
+ constant propagation_time : real := 2.5E-9;
+ constant attenuation : real := 0.8;
+ quantity vin_temp : real;
+begin
+ vin_temp == vin;
+ vout == attenuation * vin_temp'delayed(propagation_time);
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd
new file mode 100644
index 000000000..6a7b82d2a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity triangle_waveform is
+ port ( terminal pos, neg : electrical );
+end entity triangle_waveform;
+
+----------------------------------------------------------------
+
+architecture ideal of triangle_waveform is
+
+ constant freq : real := 10_000.0; -- in Hz
+ constant period : real := 1.0 / freq;
+ constant amplitude : voltage := 5.0;
+ constant offset : voltage := 0.0;
+ signal square_wave : real := 0.0;
+ quantity v across i through pos to neg;
+ limit v : voltage with period / 10.0;
+
+begin
+
+ process is
+ variable state : bit := '0';
+ begin
+ if state = '1' then
+ square_wave <= 1.0;
+ else
+ square_wave <= 0.0;
+ end if;
+ state := not state;
+ wait for period / 2.0;
+ end process;
+
+ v == offset + amplitude * square_wave'ramp(period / 2.0);
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd
new file mode 100644
index 000000000..bebc5ae38
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity triangle_waveform_wa is
+ port ( terminal pos, neg : electrical );
+end entity triangle_waveform_wa;
+
+----------------------------------------------------------------
+
+architecture ideal of triangle_waveform_wa is
+
+ constant freq : real := 10_000.0; -- in Hz
+ constant period : real := 1.0 / freq;
+ constant amplitude : voltage := 5.0;
+ constant offset : voltage := 0.0;
+ signal square_wave : real := 0.0;
+ quantity v across i through pos to neg;
+-- limit v : voltage with period / 10.0;
+
+begin
+
+ process is
+ variable state : bit := '0';
+ begin
+ if state = '1' then
+ square_wave <= 1.0;
+ else
+ square_wave <= 0.0;
+ end if;
+ state := not state;
+ wait for period / 2.0;
+ end process;
+
+ v == offset + amplitude * square_wave'ramp(period / 2.0);
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd
new file mode 100644
index 000000000..fb26e8711
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity variable_comparator is
+ port ( terminal a : electrical;
+ terminal ref : electrical;
+ signal d : out std_ulogic );
+end entity variable_comparator;
+
+----------------------------------------------------------------
+
+architecture ideal of variable_comparator is
+ quantity v_ref across ref;
+ quantity vin across a;
+begin
+
+ comparator_behavior : process is
+ begin
+ if vin > v_ref then
+ d <= '1' after 5 ns;
+ else
+ d <= '0' after 5 ns;
+ end if;
+ wait on vin'above(v_ref / 2.0);
+ end process comparator_behavior;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/74x138.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/74x138.vhd
new file mode 100644
index 000000000..dd3f90210
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/74x138.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package physical_attributes is
+
+ -- code from book (in text)
+
+ attribute layout_ignore : boolean;
+ attribute pin_number : positive;
+
+ -- end code from book
+
+end package physical_attributes;
+
+
+-- code from book
+
+library ieee; use ieee.std_logic_1164.all;
+use work.physical_attributes.all;
+
+entity \74x138\ is
+ generic ( Tpd : time );
+ port ( en1, en2a_n, en2b_n : in std_logic;
+ s0, s1, s2 : in std_logic;
+ y0, y1, y2, y3, y4, y5, y6, y7 : out std_logic );
+
+ attribute layout_ignore of Tpd : constant is true;
+
+ attribute pin_number of s0 : signal is 1;
+ attribute pin_number of s1 : signal is 2;
+ attribute pin_number of s2 : signal is 3;
+ attribute pin_number of en2a_n : signal is 4;
+ -- . . .
+
+end entity \74x138\;
+
+-- code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd
new file mode 100644
index 000000000..a475d11c9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package cell_attributes is
+
+ type length is range 0 to integer'high
+ units nm;
+ um = 1000 nm;
+ mm = 1000 um;
+ mil = 25400 nm;
+ end units length;
+
+ type coordinate is record
+ x, y : length;
+ end record coordinate;
+
+ attribute cell_position : coordinate;
+
+end package cell_attributes;
+
+
+
+entity CPU is
+end entity CPU;
+
+
+-- code from book
+
+architecture cell_based of CPU is
+
+ component fpu is
+ port ( -- . . . );
+ -- not in book
+ port_name : bit := '0' );
+ -- end not in book
+ end component;
+
+ use work.cell_attributes.all;
+
+ attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+
+ -- . . .
+
+begin
+
+ the_fpu : component fpu
+ port map ( -- . . . );
+ -- not in book
+ port_name => open );
+ -- end not in book
+
+ -- . . .
+
+end architecture cell_based;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/add_with_overflow.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/add_with_overflow.vhd
new file mode 100644
index 000000000..dd06f91a6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/add_with_overflow.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity add_with_overflow is
+end entity add_with_overflow;
+
+
+architecture test of add_with_overflow is
+begin
+
+-- code from book
+
+process is
+
+ procedure add_with_overflow ( a, b : in integer;
+ sum : out integer;
+ overflow : out boolean ) is -- . . .
+
+ -- not in book
+ begin
+ end;
+ -- end not in book
+
+ procedure add_with_overflow ( a, b : in bit_vector;
+ sum : out bit_vector;
+ overflow : out boolean ) is -- . . .
+
+ -- not in book
+ begin
+ end;
+ -- end not in book
+
+ attribute built_in : string;
+
+ attribute built_in of
+ add_with_overflow [ integer, integer,
+ integer, boolean ] : procedure is "int_add_overflow";
+
+ attribute built_in of
+ add_with_overflow [ bit_vector, bit_vector,
+ bit_vector, boolean ] : procedure is "bit_vector_add_overflow";
+
+begin
+ -- . . .
+ -- not in book
+ wait;
+ -- end not in book
+end process;
+
+-- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/bottom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/bottom.vhd
new file mode 100644
index 000000000..0ddddd90c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/bottom.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity bottom is
+ port ( -- . . . );
+ --
+ port_name : in bit := '0' );
+ --
+end entity bottom;
+
+--------------------------------------------------
+
+architecture bottom_arch of bottom is
+
+ signal bot_sig : -- . . .; -- 5
+ --
+ bit;
+ --
+
+ procedure proc ( -- . . . ) is
+ --
+ param_name : in bit := '0' ) is
+ --
+ variable v : -- . . .; -- 6
+ --
+ bit;
+ --
+ begin
+ -- . . .
+ --
+ report "--6: " & v'path_name;
+ report "--6: " & v'instance_name;
+ --
+ end procedure proc;
+
+begin
+
+ delays : block is
+ constant d : integer := 1; -- 7
+ begin
+ -- . . .
+ --
+ assert false report "--7: " & d'path_name;
+ assert false report "--7: " & d'instance_name;
+ --
+ end block delays;
+
+ func : block is
+ begin
+
+ process is
+ variable v : -- . . .; -- 8
+ --
+ bit;
+ --
+ begin
+ -- . . .
+ --
+ report "--5: " & bot_sig'path_name;
+ report "--5: " & bot_sig'instance_name;
+ report "--8: " & v'path_name;
+ report "--8: " & v'instance_name;
+ proc(param_name => open);
+ wait;
+ --
+ --
+ end process;
+
+ end block func;
+
+end architecture bottom_arch;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/clock_buffer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/clock_buffer.vhd
new file mode 100644
index 000000000..31683f7e7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/clock_buffer.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package constraints is
+
+ -- code from book (in text)
+
+ group port_pair is ( signal, signal );
+
+ attribute max_prop_delay : time;
+
+ -- end code from book
+
+end package constraints;
+
+
+
+-- code from book
+
+library ieee; use ieee.std_logic_1164.all;
+use work.constraints.port_pair, work.constraints.max_prop_delay;
+
+entity clock_buffer is
+ port ( clock_in : in std_logic;
+ clock_out1, clock_out2, clock_out3 : out std_logic );
+
+ group clock_to_out1 : port_pair ( clock_in, clock_out1 );
+ group clock_to_out2 : port_pair ( clock_in, clock_out2 );
+ group clock_to_out3 : port_pair ( clock_in, clock_out3 );
+
+ attribute max_prop_delay of clock_to_out1 : group is 2 ns;
+ attribute max_prop_delay of clock_to_out2 : group is 2 ns;
+ attribute max_prop_delay of clock_to_out3 : group is 2 ns;
+
+end entity clock_buffer;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/controller.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/controller.vhd
new file mode 100644
index 000000000..c1953b5c3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/controller.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity controller is
+end entity controller;
+
+
+architecture test of controller is
+
+ signal clk : bit;
+
+ attribute synthesis_hint : string;
+
+begin
+
+ -- code from book
+
+ controller : process is
+
+ attribute synthesis_hint of control_loop : label is
+ "implementation:FSM(clk)";
+ -- . . .
+
+ begin
+ -- . . . -- initialization
+ control_loop : loop
+ wait until clk = '1';
+ -- . . .
+ end loop;
+ end process controller;
+
+ -- end code fom book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/display_interface.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/display_interface.vhd
new file mode 100644
index 000000000..a2795917e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/display_interface.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package display_interface is
+
+ -- . . .
+
+ -- not in book
+ type status_type is (t1, t2, t3);
+ -- end not in book
+
+ procedure create_window ( size_x, size_y : natural;
+ status : out status_type );
+
+ attribute foreign of create_window : procedure is
+ "language Ada; with window_operations;" &
+ "bind to window_operations.create_window;" &
+ "parameter size_x maps to size_x : in natural;" &
+ "parameter size_y maps to size_y : in natural;" &
+ "parameter status maps to status : out window_operations.status_type;" &
+ "others map to default";
+
+ -- . . .
+
+end package display_interface;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/flipflop.vhd
new file mode 100644
index 000000000..53d6c3bc2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/flipflop.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity flipflop is
+ generic ( Tsetup : delay_length );
+ port ( clk, d : in bit; q : out bit );
+end entity flipflop;
+
+
+-- code from book
+
+architecture behavior of flipflop is
+begin
+
+ timing_check : process (clk) is
+ begin
+ if clk = '1' then
+ assert d'last_event >= Tsetup
+ report "set up violation detected in " & timing_check'path_name
+ severity error;
+ end if;
+ end process timing_check;
+
+ -- . . . -- functionality
+
+end architecture behavior;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd
new file mode 100644
index 000000000..271dbbd9d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- analyze into resource library graphics
+
+package graphics_pkg is
+
+ attribute graphic_symbol : string;
+ attribute graphic_style : string;
+
+end package graphics_pkg;
+
+
+
+-- code from book
+
+library ieee; use ieee.std_logic_1164.all;
+library graphics;
+
+package gate_components is
+
+ use graphics.graphics_pkg.graphic_symbol,
+ graphics.graphics_pkg.graphic_style;
+
+ component and2 is
+ generic ( prop_delay : delay_length );
+ port ( a, b : in std_logic; y : out std_logic );
+ end component and2;
+
+ attribute graphic_symbol of and2 : component is "and2";
+ attribute graphic_style of and2 : component is "color:default, weight:bold";
+
+ -- . . .
+
+end package gate_components;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/index-ams.txt
new file mode 100644
index 000000000..90d6c36ec
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/index-ams.txt
@@ -0,0 +1,48 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 22 - Attributes and Groups
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+flipflop.vhd entity flipflop behavior Figure 22-8
+mem_pkg.vhd package mem_pkg body Figure 22-9
+top.vhd entity top top_arch Figure 22-10
+bottom.vhd entity bottom bottom_arch Figure 22-12
+add_with_overflow.vhd entity add_with_overflow test Figure 22-14
+74x138.vhd package physical_attributes -- Section 22.2
+-- entity \74x138\ -- Figure 22-15
+mem_read.vhd entity mem_read test Figure 22-16
+gate_components.vhd package graphics_pkg -- --
+-- package gate_components -- Figure 22-17
+CPU.vhd package cell_attributes -- --
+-- entity CPU cell_based Figure 22-18
+controller.vhd entity controller test Figure 22-19
+voltage_defs.vhd package voltage_defs -- Figure 22-20
+sequencer.vhd package timing_attributes -- --
+-- entity sequencer structural Figure 22-21
+display_interface.vhd package display_interface -- Figure 22-22
+clock_buffer.vhd package constraints -- Section 20.3
+-- entity clock_buffer -- Figure 20-23
+inline_01.vhd package utility_definitions -- --
+-- entity inline_01 test Section 22.1
+inline_02.vhd entity inline_02 test Section 22.1
+inline_03.vhd package inline_03_defs -- Section 22.2
+-- entity inline_03 test Section 22.2
+inline_04.vhd package inline_04 -- --
+-- entity flipflop std_cell Section 22.2
+-- package model_utilities -- Section 22.2
+inline_05.vhd entity inline_05 test Section 22.2
+inline_06.vhd entity inline_06 test Section 22.2
+inline_07.vhd entity inline_07 test Section 22.2
+inline_08.vhd entity inline_08 test Section 22.2
+inline_09.vhd package inline_09_defs -- --
+-- entity e arch --
+-- entity inline_09 test Section 22.2
+inline_10.vhd package inline_10 -- Section 22.2
+-- entity and2 accelerated Section 22.2
+inline_11.vhd entity inline_11 test Section 22.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_flipflop.vhd entity tb_flipflop test flipflop.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_01.vhd
new file mode 100644
index 000000000..7516d539c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_01.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- analyze into resource library utilities
+
+package utility_definitions is
+
+ constant word_size : natural := 16;
+
+end package utility_definitions;
+
+
+
+library utilities;
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+ process is
+ begin
+
+ report
+
+ -- code from book:
+
+ utilities.utility_definitions.word_size'simple_name
+
+ -- end of code from book
+
+ ;
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_02.vhd
new file mode 100644
index 000000000..36f102d64
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_02.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library project;
+
+entity inline_02 is
+end entity inline_02;
+
+
+architecture test of inline_02 is
+begin
+
+ process is
+
+ use project.mem_pkg;
+ use project.mem_pkg.all;
+ variable words : word_array(0 to 3);
+
+ begin
+ assert
+ -- code from book (in text)
+ mem_pkg'path_name = ":project:mem_pkg:"
+ -- end code from book
+ ;
+ report mem_pkg'path_name;
+
+ assert
+ -- code from book (in text)
+ word'path_name = ":project:mem_pkg:word"
+ -- end code from book
+ ;
+ report word'path_name;
+
+ assert
+ -- code from book (in text)
+ word_array'path_name = ":project:mem_pkg:word_array"
+ -- end code from book
+ ;
+
+ report word_array'path_name;
+
+ assert
+ -- code from book (in text)
+ load_array'path_name = ":project:mem_pkg:load_array"
+ -- end code from book
+ ;
+ report load_array'path_name;
+
+ load_array(words, "/dev/null");
+ wait;
+ end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_03.vhd
new file mode 100644
index 000000000..749cbee36
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_03.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package inline_03_defs is
+
+ -- code from book:
+
+ attribute cell_name : string;
+ attribute pin_number : positive;
+ attribute max_wire_delay : delay_length;
+ attribute encoding : bit_vector;
+
+
+ type length is range 0 to integer'high
+ units nm;
+ um = 1000 nm;
+ mm = 1000 um;
+ mil = 25400 nm;
+ end units length;
+
+ type coordinate is record
+ x, y : length;
+ end record coordinate;
+
+ attribute cell_position : coordinate;
+
+ -- end of code from book
+
+end package inline_03_defs;
+
+
+
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture std_cell of inline_03 is
+
+ use work.inline_03_defs.all;
+
+ signal enable, clk : bit;
+
+ type state_type is (idle_state, other_state);
+
+ -- code from book:
+
+ attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+ attribute pin_number of enable : signal is 14;
+ attribute max_wire_delay of clk : signal is 50 ps;
+ attribute encoding of idle_state : literal is b"0000";
+ attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+
+ -- end of code from book
+
+begin
+
+ the_fpu : block is
+ begin
+ end block the_fpu;
+
+ process is
+ use std.textio.all;
+ variable L : line;
+ begin
+ write(L, std_cell'cell_name);
+ writeline(output, L);
+ write(L, enable'pin_number);
+ writeline(output, L);
+ write(L, clk'max_wire_delay);
+ writeline(output, L);
+ write(L, idle_state[return state_type]'encoding);
+ writeline(output, L);
+ write(L, length'image(the_fpu'cell_position.x));
+ write(L, ' ');
+ write(L, length'image(the_fpu'cell_position.y));
+ writeline(output, L);
+
+ wait;
+ end process;
+
+end architecture std_cell;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_04.vhd
new file mode 100644
index 000000000..5cd9ec28b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_04.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package inline_04 is
+
+ attribute cell_name : string;
+
+end package inline_04;
+
+
+
+entity flipflop is
+
+end entity flipflop;
+
+
+
+use work.inline_04.all;
+
+-- code from book:
+
+architecture std_cell of flipflop is
+
+ attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+
+ -- . . . -- other declarations
+
+begin
+ -- . . .
+end architecture std_cell;
+
+-- end of code from book
+
+
+
+-- code from book:
+
+package model_utilities is
+
+ attribute optimize : string;
+ attribute optimize of model_utilities : package is "level_4";
+
+ -- . . .
+
+end package model_utilities;
+
+-- end of code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_05.vhd
new file mode 100644
index 000000000..340664b08
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_05.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+ type stimulus_list is array (natural range <>) of integer;
+
+
+ -- code from book:
+
+ function "&" ( a, b : stimulus_list ) return stimulus_list;
+
+ attribute debug : string;
+ attribute debug of
+ "&" [ stimulus_list, stimulus_list return stimulus_list ] : function is
+ "source_statement_step";
+
+
+ type mvl is ('X', '0', '1', 'Z');
+ type mvl_vector is array ( integer range <>) of mvl;
+ function resolve_mvl ( drivers : mvl_vector ) return mvl;
+
+ subtype resolved_mvl is resolve_mvl mvl;
+
+
+ type builtin_types is (builtin_bit, builtin_mvl, builtin_integer);
+ attribute builtin : builtin_types;
+
+ attribute builtin of resolved_mvl : subtype is builtin_mvl;
+
+ -- end of code from book
+
+ function "&" ( a, b : stimulus_list ) return stimulus_list is
+ begin
+ return stimulus_list'(1 to 0 => 0);
+ end function "&";
+
+ function resolve_mvl ( drivers : mvl_vector ) return mvl is
+ begin
+ return drivers(drivers'left);
+ end function resolve_mvl;
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd
new file mode 100644
index 000000000..2d0b8758e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+use std.textio.all;
+
+architecture test of inline_06 is
+
+ subtype encoding_type is bit_vector(1 downto 0);
+ attribute encoding : encoding_type;
+
+begin
+
+
+ process1 : process is
+
+ -- code from book:
+
+ type controller_state is (idle, active, fail_safe);
+ type load_level is (idle, busy, overloaded);
+
+ attribute encoding of idle [ return controller_state ] : literal is b"00";
+ attribute encoding of active [ return controller_state ] : literal is b"01";
+ attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
+
+ -- end of code from book
+
+ variable L : line;
+
+ begin
+ write(L, string'("process1"));
+ writeline(output, L);
+ write(L, idle [ return controller_state ] ' encoding);
+ writeline(output, L);
+ write(L, active [ return controller_state ] ' encoding);
+ writeline(output, L);
+ write(L, fail_safe [ return controller_state ] ' encoding);
+ writeline(output, L);
+ wait;
+ end process process1;
+
+
+ process2 : process is
+
+ type controller_state is (idle, active, fail_safe);
+ type load_level is (idle, busy, overloaded);
+
+ attribute encoding of idle : literal is b"11";
+
+ variable L : line;
+
+ begin
+ write(L, string'("process2"));
+ writeline(output, L);
+ write(L, idle [ return controller_state ] ' encoding);
+ writeline(output, L);
+ write(L, idle [ return load_level ] ' encoding);
+ writeline(output, L);
+ wait;
+ end process process2;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_07.vhd
new file mode 100644
index 000000000..6ed29d90a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_07.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_07 is
+
+ component multiplier is
+ end component multiplier;
+
+ type length is range 0 to integer'high
+ units nm;
+ um = 1000 nm;
+ mm = 1000 um;
+ mil = 25400 nm;
+ end units length;
+
+ type coordinate is record
+ x, y : length;
+ end record coordinate;
+
+ type orientation_type is (up, down, left, right);
+
+ attribute cell_allocation : string;
+ attribute cell_position : coordinate;
+ attribute cell_orientation : orientation_type;
+
+ -- code from book:
+
+ attribute cell_allocation of mult : label is "wallace_tree_multiplier";
+ attribute cell_position of mult : label is ( 1200 um, 4500 um );
+ attribute cell_orientation of mult : label is down;
+
+ -- end of code from book
+
+begin
+
+ mult : component multiplier;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd
new file mode 100644
index 000000000..20050940e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd
@@ -0,0 +1,117 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+architecture std_cell of inline_08 is
+
+ attribute cell_name : string;
+ attribute pin_number : positive;
+ attribute max_wire_delay : delay_length;
+ attribute encoding : bit_vector;
+
+ type length is range 0 to integer'high
+ units nm;
+ um = 1000 nm;
+ mm = 1000 um;
+ mil = 25400 nm;
+ end units length;
+
+ type coordinate is record
+ x, y : length;
+ end record coordinate;
+
+ attribute cell_position : coordinate;
+
+ type built_in_type is (bv_incr, std_incr);
+ attribute built_in : built_in_type;
+
+ signal enable, clk : bit;
+
+ type state_type is (idle_state, other_state);
+
+ type speed_range is (high, other_speed);
+ type coolant_level is (high, other_level);
+
+ attribute representation : string;
+
+ function increment ( vector : in bit_vector ) return bit_vector is
+ begin
+ end;
+
+ function increment ( vector : in std_logic_vector ) return std_logic_vector is
+ begin
+ end;
+
+ attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+ attribute pin_number of enable : signal is 14;
+ attribute max_wire_delay of clk : signal is 50 ps;
+ attribute encoding of idle_state : literal is b"0000";
+ attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+ attribute built_in of
+ increment [ bit_vector return bit_vector ] : function is bv_incr;
+ attribute built_in of
+ increment [ std_logic_vector return std_logic_vector ] : function is std_incr;
+ attribute representation of high [ return speed_range ] : literal is "byte";
+ attribute representation of high [ return coolant_level ] : literal is "word";
+
+begin
+
+ the_fpu : block is
+ begin
+ end block the_fpu;
+
+ process is
+ variable v1 : string(1 to 11);
+ variable v2 : positive;
+ variable v3 : time;
+ variable v4 : bit_vector(0 to 3);
+ variable v5 : coordinate;
+ variable v6, v7 : built_in_type;
+ variable v8, v9 : string(1 to 4);
+ begin
+
+ -- code from book included...
+
+ v1 := std_cell'cell_name ;
+ v2 := enable'pin_number ;
+ v3 := clk'max_wire_delay ;
+ v4 := idle_state'encoding ;
+ v5 := the_fpu'cell_position ;
+
+ v6 := increment [ bit_vector return bit_vector ] 'built_in ;
+ v7 := increment [ std_logic_vector return std_logic_vector ] 'built_in ;
+
+ v8 := high [ return speed_range ] 'representation ;
+ v9 := high [ return coolant_level ] 'representation ;
+
+ -- end code from book
+
+ wait;
+ end process;
+
+end architecture std_cell;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_09.vhd
new file mode 100644
index 000000000..7ecccaaca
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_09.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package inline_09_defs is
+
+ attribute attr : integer;
+
+end package inline_09_defs;
+
+
+
+use work.inline_09_defs.all;
+
+entity e is
+ port ( p : in bit );
+ attribute attr of p : signal is 1;
+end entity e;
+
+
+architecture arch of e is
+begin
+
+ assert false report integer'image(p'attr);
+
+end architecture arch;
+
+
+
+use work.inline_09_defs.all;
+
+entity inline_09 is
+end entity inline_09;
+
+
+
+architecture test of inline_09 is
+
+ signal s : bit;
+
+ attribute attr of s : signal is 2;
+
+begin
+
+ -- code from book
+
+ c1 : entity work.e(arch)
+ port map ( p => s );
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_10.vhd
new file mode 100644
index 000000000..267f4aeef
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_10.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package inline_10 is
+
+ -- code from book
+
+ attribute foreign : string;
+
+ -- end code from book
+
+end package inline_10;
+
+
+
+entity and2 is
+end entity and2;
+
+
+-- code from book
+
+architecture accelerated of and2 is
+ attribute foreign of accelerated : architecture is
+ "accelerate/function:and_2in/nocheck";
+begin
+end architecture accelerated;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_11.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_11.vhd
new file mode 100644
index 000000000..11d66caf9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_11.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_11 is
+
+end entity inline_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_11 is
+
+ component comp is
+ end component comp;
+
+ signal clk_phase1, clk_phase2 : bit;
+
+ -- code from book:
+
+ group signal_pair is (signal, signal);
+
+ group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
+
+ attribute max_skew : time;
+
+ attribute max_skew of clock_pair : group is 200 ps;
+
+ group component_instances is ( label <> );
+
+ group U1 : component_instances ( nand1, nand2, nand3 );
+ group U2 : component_instances ( inv1, inv2 );
+
+ attribute IC_allocation : string;
+
+ attribute IC_allocation of U1 : group is "74LS00";
+ attribute IC_allocation of U2 : group is "74LS04";
+
+ -- end of code from book
+
+begin
+
+
+ nand1 : component comp;
+ nand2 : component comp;
+ nand3 : component comp;
+ inv1 : component comp;
+ inv2 : component comp;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_pkg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_pkg.vhd
new file mode 100644
index 000000000..39655036a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_pkg.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package mem_pkg is
+
+ subtype word is bit_vector(0 to 31);
+ type word_array is array (natural range <>) of word;
+
+ procedure load_array ( words : out word_array; file_name : string );
+
+end package mem_pkg;
+
+--------------------------------------------------
+
+package body mem_pkg is
+
+ procedure load_array ( words : out word_array; file_name : string ) is
+ -- words'path_name = ":project:mem_pkg:load_array:words"
+
+ use std.textio.all;
+ file load_file : text open read_mode is file_name;
+ -- load_file'path_name = ":project:mem_pkg:load_array:load_file"
+
+ procedure read_line is
+ -- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
+ variable current_line : line;
+ -- current_line'path_name =
+ -- ":project:mem_pkg:load_array:read_line:current_line"
+ begin
+ -- . . .
+ -- not in book
+ report current_line'path_name;
+ -- end not in book
+ end procedure read_line;
+
+ begin -- load_array
+ -- . . .
+ -- not in book
+ report mem_pkg'path_name;
+ report words'path_name;
+ report load_file'path_name;
+ report read_line'path_name;
+ read_line;
+ -- end not in book
+ end procedure load_array;
+
+end package body mem_pkg;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_read.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_read.vhd
new file mode 100644
index 000000000..a320a42a0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_read.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity mem_read is
+end entity mem_read;
+
+
+architecture test of mem_read is
+
+ attribute trace : string;
+
+ subtype byte is bit_vector(7 downto 0);
+ type byte_vector is array (natural range <>) of byte;
+
+ type ram_bus is record
+ d : byte;
+ cmd, status, clk : bit;
+ end record ram_bus;
+
+ -- code from book
+
+ procedure mem_read ( address : in natural;
+ result : out byte_vector;
+ signal memory_bus : inout ram_bus ) is
+
+ attribute trace of address : constant is "integer/hex";
+ attribute trace of result : variable is "byte/multiple/hex";
+ attribute trace of memory_bus : signal is
+ "custom/command=rambus.cmd";
+ -- . . .
+
+ begin
+ -- . . .
+ -- not in book
+ report address'trace;
+ report result'trace;
+ report memory_bus'trace;
+ -- end not in book
+ end procedure mem_read;
+
+ -- end code from book
+
+ signal memory_bus : ram_bus;
+
+begin
+
+ process is
+ variable address : natural;
+ variable result : byte_vector(0 to 3);
+ begin
+ mem_read ( address, result, memory_bus );
+ wait;
+ end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/sequencer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/sequencer.vhd
new file mode 100644
index 000000000..f35a75a02
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/sequencer.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package timing_attributes is
+
+ attribute max_wire_delay : delay_length;
+
+end package timing_attributes;
+
+
+entity sequencer is
+end entity sequencer;
+
+
+-- code from book
+
+library ieee; use ieee.std_logic_1164.all;
+use work.timing_attributes.all;
+
+architecture structural of sequencer is
+
+ signal recovered_clk1, recovered_clk2 : std_logic;
+ signal test_enable : std_logic;
+ signal test_data : std_logic_vector(0 to 15);
+
+ attribute max_wire_delay of
+ recovered_clk1, recovered_clk2 : signal is 100 ps;
+
+ attribute max_wire_delay of others : signal is 200 ps;
+
+ -- . . .
+
+begin
+ -- . . .
+ -- not in book
+ assert false report time'image(recovered_clk1'max_wire_delay) severity note;
+ assert false report time'image(recovered_clk2'max_wire_delay) severity note;
+ assert false report time'image(test_enable'max_wire_delay) severity note;
+ assert false report time'image(test_data'max_wire_delay) severity note;
+ -- end not in book
+end architecture structural;
+
+-- code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/tb_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/tb_flipflop.vhd
new file mode 100644
index 000000000..f1aacab62
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/tb_flipflop.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+
+entity tb_flipflop is
+end entity tb_flipflop;
+
+
+architecture test of tb_flipflop is
+
+ signal clk, d, q : bit;
+
+begin
+
+ dut : entity work.flipflop(behavior)
+ generic map ( Tsetup => 3 ns )
+ port map ( clk => clk, d => d, q => q );
+
+ clk <= '1' after 10 ns, '0' after 20 ns;
+
+ d <= '1' after 8 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/top.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/top.vhd
new file mode 100644
index 000000000..46c69c6bd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/top.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity top is
+end entity top;
+
+--------------------------------------------------
+
+architecture top_arch of top is
+
+ signal top_sig : -- . . .; -- 1
+ --
+ bit;
+ --
+
+begin
+
+ stimulus : process is
+ variable var : -- . . .; -- 2
+ --
+ bit;
+ --
+ begin
+ -- . . .
+ --
+ report "--1: " & top'path_name;
+ report "--1: " & top'instance_name;
+ report "--1: " & top_sig'path_name;
+ report "--1: " & top_sig'instance_name;
+ report "--2: " & stimulus'path_name;
+ report "--2: " & stimulus'instance_name;
+ report "--2: " & var'path_name;
+ report "--2: " & var'instance_name;
+ wait;
+ --
+ end process stimulus;
+
+ rep_gen : for index in 0 to 7 generate
+ begin
+
+ end_gen : if index = 7 generate
+ signal end_sig : -- . . .; -- 3
+ --
+ bit;
+ --
+ begin
+ -- . . .
+ assert false report "--3: " & end_sig'path_name;
+ assert false report "--3: " & end_sig'instance_name;
+ --
+ end generate end_gen;
+
+ other_gen : if index /= 7 generate
+ signal other_sig : -- . . .; -- 4
+ --
+ bit;
+ --
+ begin
+ other_comp : entity work.bottom(bottom_arch)
+ port map ( -- . . . );
+ --
+ port_name => open );
+ assert false report "--4: " & other_sig'path_name;
+ assert false report "--4: " & other_sig'instance_name;
+ --
+ end generate other_gen;
+
+ end generate rep_gen;
+
+end architecture top_arch;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/voltage_defs.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/voltage_defs.vhd
new file mode 100644
index 000000000..e0774e68a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/voltage_defs.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package voltage_defs is
+
+ type voltage is range -2e9 to +2e9
+ units
+ nV;
+ uV = 1000 nV;
+ mV = 1000 uV;
+ V = 1000 mV;
+ end units voltage;
+
+ attribute resolution : real;
+
+ attribute resolution of nV : units is 1.0;
+ attribute resolution of uV : units is 0.01;
+ attribute resolution of mV : units is 0.01;
+ attribute resolution of V : units is 0.001;
+
+end package voltage_defs;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/compliant.exp b/testsuite/vests/vhdl-ams/ashenden/compliant/compliant.exp
new file mode 100644
index 000000000..f4d0f0836
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/compliant.exp
@@ -0,0 +1,586 @@
+
+# Copyright (C) 2003-2004 University of Cincinnati
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+# Please email any bugs, comments, and/or additions to this file to:
+# vests@cliftonlabs.com
+
+# Authors: Philip A. Wilsey philip.wilsey@ieee.org
+# Dale E. Martin dmartin@cliftonlabs.com
+
+setup_test_group "Ashenden:VHDL-AMS Compliant Cases" "vhdl-ams"
+
+build_compliant_test util/clock_duty.vhd
+build_compliant_test util/gain.vhd
+build_compliant_test util/resistor.vhd
+build_compliant_test util/src_constant.vhd
+build_compliant_test util/src_pulse.vhd
+build_compliant_test util/src_sine.vhd
+build_compliant_test util/sum2.vhd
+build_compliant_test util/stimulus_generators.vhd
+
+build_compliant_test AMS_CS1_Mixed_Sig/switch_dig_2in.vhd
+build_compliant_test AMS_CS1_Mixed_Sig/a2d_nbit.vhd
+build_compliant_test AMS_CS1_Mixed_Sig/dac_10_bit.vhd
+build_compliant_test AMS_CS1_Mixed_Sig/tb_2in_switch.vhd
+build_compliant_test AMS_CS1_Mixed_Sig/tb_a2d_d2a.vhd
+build_compliant_test AMS_CS1_Mixed_Sig/tb_CS1.vhd
+
+build_compliant_test AMS_CS2_Mixed_Tech/gain.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/gain_e.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/sum2.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/limiter.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/lpf_1.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/lead_lag.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/DC_Motor.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/gear_rv_r.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/stop_r.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/lead_lag_diff.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd
+
+build_compliant_test AMS_CS3_Power_Systems/tb_BuckConverter.vhd
+build_compliant_test AMS_CS3_Power_Systems/capacitor.vhd
+build_compliant_test AMS_CS3_Power_Systems/switch_dig.vhd
+build_compliant_test AMS_CS3_Power_Systems/buck_sw.vhd
+build_compliant_test AMS_CS3_Power_Systems/sw_LoopCtrl.vhd
+build_compliant_test AMS_CS3_Power_Systems/sw_LoopCtrl_wa.vhd
+build_compliant_test AMS_CS3_Power_Systems/comp_2p2z.vhd
+build_compliant_test AMS_CS3_Power_Systems/pwl_load.vhd
+build_compliant_test AMS_CS3_Power_Systems/pwl_load_wa.vhd
+build_compliant_test AMS_CS3_Power_Systems/CalcBuckParams.vhd
+build_compliant_test AMS_CS3_Power_Systems/CalcBuckParams_wa.vhd
+build_compliant_test AMS_CS3_Power_Systems/tb_CalcBuckParams.vhd
+build_compliant_test AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd
+
+build_compliant_test AMS_CS4_RF_IC/bfsk.vhd
+build_compliant_test AMS_CS4_RF_IC/bfsk_wa.vhd
+build_compliant_test AMS_CS4_RF_IC/MeasFreq.vhd
+build_compliant_test AMS_CS4_RF_IC/v_BPF.vhd
+build_compliant_test AMS_CS4_RF_IC/v_Sum.vhd
+build_compliant_test AMS_CS4_RF_IC/PLL.vhd
+build_compliant_test AMS_CS4_RF_IC/tb_pll.vhd
+build_compliant_test AMS_CS4_RF_IC/tb_CS4_CommSys_PLL.vhd
+build_compliant_test AMS_CS4_RF_IC/tb_CS4_CommSys_det.vhd
+
+build_compliant_test AMS_CS5_RC_Airplane/amp_lim.vhd
+build_compliant_test AMS_CS5_RC_Airplane/pwl_functions.vhd
+build_compliant_test AMS_CS5_RC_Airplane/prop_pwl.vhd
+build_compliant_test AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
+build_compliant_test AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd
+build_compliant_test AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
+build_compliant_test AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd
+build_compliant_test AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd
+
+build_compliant_test access-types/list_traversal.vhd
+build_compliant_test access-types/list_search.vhd
+build_compliant_test access-types/bounded_buffer_adt.vhd
+build_compliant_test access-types/receiver.vhd
+build_compliant_test access-types/ordered_collection_adt.vhd
+build_compliant_test access-types/stimulus_types-1.vhd
+build_compliant_test access-types/test_bench-1.vhd
+build_compliant_test access-types/inline_01.vhd
+build_compliant_test access-types/inline_02a.vhd
+build_compliant_test access-types/inline_03.vhd
+build_compliant_test access-types/inline_04a.vhd
+build_compliant_test access-types/inline_05.vhd
+build_compliant_test access-types/inline_06a.vhd
+build_compliant_test access-types/inline_07a.vhd
+build_compliant_test access-types/inline_08.vhd
+build_compliant_test access-types/inline_09.vhd
+build_compliant_test access-types/tb_bounded_buffer_adt.vhd
+
+build_compliant_test aliases/controller_system.vhd
+build_compliant_test aliases/safety_switch.vhd
+build_compliant_test aliases/function_plus.vhd
+build_compliant_test aliases/DMA_controller_types_and_utilities.vhd
+build_compliant_test aliases/DMA_controller.vhd
+build_compliant_test aliases/inline_01a.vhd
+build_compliant_test aliases/inline_02.vhd
+build_compliant_test aliases/inline_03a.vhd
+build_compliant_test aliases/inline_04.vhd
+build_compliant_test aliases/inline_05.vhd
+build_compliant_test aliases/inline_06.vhd
+build_compliant_test aliases/tb_function_plus.vhd
+
+build_compliant_test analog-modeling/control_system.vhd
+build_compliant_test analog-modeling/comparator.vhd
+build_compliant_test analog-modeling/variable_comparator.vhd
+build_compliant_test analog-modeling/transmission_line.vhd
+build_compliant_test analog-modeling/transmission_line_wa.vhd
+build_compliant_test analog-modeling/inductor.vhd
+build_compliant_test analog-modeling/piston.vhd
+build_compliant_test analog-modeling/inductor-1.vhd
+build_compliant_test analog-modeling/moving_mass.vhd
+build_compliant_test analog-modeling/moving_mass_wa.vhd
+build_compliant_test analog-modeling/opamp.vhd
+build_compliant_test analog-modeling/quad_opamp.vhd
+build_compliant_test analog-modeling/quad_opamp_wa.vhd
+build_compliant_test analog-modeling/bit_to_analog.vhd
+build_compliant_test analog-modeling/std_logic_to_analog.vhd
+build_compliant_test analog-modeling/opamp-1.vhd
+build_compliant_test analog-modeling/opamp_wa-1.vhd
+build_compliant_test analog-modeling/resistor.vhd
+build_compliant_test analog-modeling/capacitor.vhd
+build_compliant_test analog-modeling/inverting_integrator.vhd
+build_compliant_test analog-modeling/timer.vhd
+build_compliant_test analog-modeling/ball.vhd
+build_compliant_test analog-modeling/ball_wa.vhd
+build_compliant_test analog-modeling/analog_switch.vhd
+build_compliant_test analog-modeling/pendulum.vhd
+build_compliant_test analog-modeling/pendulum_wa.vhd
+build_compliant_test analog-modeling/triangle_waveform.vhd
+build_compliant_test analog-modeling/triangle_waveform_wa.vhd
+build_compliant_test analog-modeling/comparator-1.vhd
+build_compliant_test analog-modeling/dac_12_bit.vhd
+build_compliant_test analog-modeling/diode.vhd
+build_compliant_test analog-modeling/inline_01a.vhd
+build_compliant_test analog-modeling/inline_02a.vhd
+build_compliant_test analog-modeling/inline_03a.vhd
+build_compliant_test analog-modeling/inline_04a.vhd
+build_compliant_test analog-modeling/inline_05a.vhd
+build_compliant_test analog-modeling/inline_06a.vhd
+build_compliant_test analog-modeling/inline_07a.vhd
+build_compliant_test analog-modeling/inline_08a.vhd
+build_compliant_test analog-modeling/inline_09a.vhd
+build_compliant_test analog-modeling/inline_10a.vhd
+build_compliant_test analog-modeling/inline_11a.vhd
+build_compliant_test analog-modeling/inline_12a.vhd
+build_compliant_test analog-modeling/inline_13a.vhd
+build_compliant_test analog-modeling/inline_14a.vhd
+build_compliant_test analog-modeling/inline_15a.vhd
+build_compliant_test analog-modeling/inline_16a.vhd
+build_compliant_test analog-modeling/inline_17a.vhd
+build_compliant_test analog-modeling/inline_18a.vhd
+build_compliant_test analog-modeling/inline_19a.vhd
+build_compliant_test analog-modeling/inline_20a.vhd
+build_compliant_test analog-modeling/inline_21a.vhd
+build_compliant_test analog-modeling/inline_22a.vhd
+build_compliant_test analog-modeling/inline_23a.vhd
+build_compliant_test analog-modeling/inline_24a.vhd
+build_compliant_test analog-modeling/tb_control_system.vhd
+build_compliant_test analog-modeling/tb_comparator.vhd
+build_compliant_test analog-modeling/tb_variable_comparator.vhd
+build_compliant_test analog-modeling/tb_transmission_line.vhd
+build_compliant_test analog-modeling/tb_piston.vhd
+build_compliant_test analog-modeling/tb_moving_mass.vhd
+build_compliant_test analog-modeling/tb_quad_opamp.vhd
+build_compliant_test analog-modeling/tb_bit_to_analog.vhd
+build_compliant_test analog-modeling/tb_std_logic_to_analog.vhd
+build_compliant_test analog-modeling/tb_inv_integrator.vhd
+build_compliant_test analog-modeling/tb_analog_switch.vhd
+build_compliant_test analog-modeling/tb_triangle_waveform.vhd
+build_compliant_test analog-modeling/tb_comparator-1.vhd
+build_compliant_test analog-modeling/tb_diode.vhd
+
+build_compliant_test attributes-and-groups/flipflop.vhd
+build_compliant_test attributes-and-groups/mem_pkg.vhd
+build_compliant_test attributes-and-groups/top.vhd
+build_compliant_test attributes-and-groups/bottom.vhd
+build_compliant_test attributes-and-groups/add_with_overflow.vhd
+build_compliant_test attributes-and-groups/74x138.vhd
+build_compliant_test attributes-and-groups/mem_read.vhd
+build_compliant_test attributes-and-groups/gate_components.vhd
+build_compliant_test attributes-and-groups/CPU.vhd
+build_compliant_test attributes-and-groups/controller.vhd
+build_compliant_test attributes-and-groups/voltage_defs.vhd
+build_compliant_test attributes-and-groups/sequencer.vhd
+build_compliant_test attributes-and-groups/display_interface.vhd
+build_compliant_test attributes-and-groups/clock_buffer.vhd
+build_compliant_test attributes-and-groups/inline_01.vhd
+build_compliant_test attributes-and-groups/inline_02.vhd
+build_compliant_test attributes-and-groups/inline_03.vhd
+build_compliant_test attributes-and-groups/inline_04.vhd
+build_compliant_test attributes-and-groups/inline_05.vhd
+build_compliant_test attributes-and-groups/inline_06.vhd
+build_compliant_test attributes-and-groups/inline_07.vhd
+build_compliant_test attributes-and-groups/inline_08.vhd
+build_compliant_test attributes-and-groups/inline_09.vhd
+build_compliant_test attributes-and-groups/inline_10.vhd
+build_compliant_test attributes-and-groups/inline_11.vhd
+build_compliant_test attributes-and-groups/tb_flipflop.vhd
+
+build_compliant_test components-and-configs/opamp.vhd
+build_compliant_test components-and-configs/automotive_valve_defs.vhd
+build_compliant_test components-and-configs/automotive_valve.vhd
+build_compliant_test components-and-configs/brake_system.vhd
+build_compliant_test components-and-configs/opamp_mosfets.vhd
+build_compliant_test components-and-configs/notch_filter.vhd
+build_compliant_test components-and-configs/notch_filter_down_to_device_level.vhd
+build_compliant_test components-and-configs/notch_filter_full.vhd
+build_compliant_test components-and-configs/fm_radio.vhd
+build_compliant_test components-and-configs/successive_approx_adc.vhd
+build_compliant_test components-and-configs/sensor_interface.vhd
+build_compliant_test components-and-configs/sensor_interface_with_timing.vhd
+build_compliant_test components-and-configs/computer_system.vhd
+build_compliant_test components-and-configs/decoder_3_to_8.vhd
+build_compliant_test components-and-configs/reg-1.vhd
+build_compliant_test components-and-configs/computer_structure.vhd
+build_compliant_test components-and-configs/single_board_computer.vhd
+build_compliant_test components-and-configs/intermediate.vhd
+build_compliant_test components-and-configs/logic_block.vhd
+build_compliant_test components-and-configs/control_section.vhd
+build_compliant_test components-and-configs/controller_with_timing-1.vhd
+build_compliant_test components-and-configs/interlock_control.vhd
+build_compliant_test components-and-configs/interlock_control_with_estimates.vhd
+build_compliant_test components-and-configs/misc_logic.vhd
+build_compliant_test components-and-configs/misc_logic_reconfigured.vhd
+build_compliant_test components-and-configs/inline_02a.vhd
+build_compliant_test components-and-configs/inline_04a.vhd
+build_compliant_test components-and-configs/inline_05.vhd
+
+build_compliant_test composite-data/coeff_ram.vhd
+build_compliant_test composite-data/transmission_lines.vhd
+build_compliant_test composite-data/modem_controller.vhd
+build_compliant_test composite-data/and_multiple.vhd
+build_compliant_test composite-data/tb_and_multiple.vhd
+build_compliant_test composite-data/byte_swap.vhd
+build_compliant_test composite-data/computer.vhd
+build_compliant_test composite-data/inline_01.vhd
+build_compliant_test composite-data/inline_02a.vhd
+build_compliant_test composite-data/inline_03.vhd
+build_compliant_test composite-data/inline_04a.vhd
+build_compliant_test composite-data/inline_05.vhd
+build_compliant_test composite-data/inline_06a.vhd
+build_compliant_test composite-data/inline_07a.vhd
+build_compliant_test composite-data/inline_08.vhd
+build_compliant_test composite-data/inline_09a.vhd
+build_compliant_test composite-data/inline_10.vhd
+build_compliant_test composite-data/inline_11a.vhd
+build_compliant_test composite-data/inline_12.vhd
+build_compliant_test composite-data/inline_13.vhd
+build_compliant_test composite-data/inline_14a.vhd
+build_compliant_test composite-data/inline_15.vhd
+build_compliant_test composite-data/inline_16.vhd
+build_compliant_test composite-data/inline_17a.vhd
+build_compliant_test composite-data/tb_coeff_ram.vhd
+build_compliant_test composite-data/tb_byte_swap.vhd
+
+build_compliant_test design-processing/inverting_integrator.vhd
+build_compliant_test design-processing/dff.vhd
+build_compliant_test design-processing/volume_sensor.vhd
+build_compliant_test design-processing/active_filter.vhd
+build_compliant_test design-processing/inline_01a.vhd
+build_compliant_test design-processing/inline_02a.vhd
+build_compliant_test design-processing/inline_03a.vhd
+build_compliant_test design-processing/inline_04a.vhd
+build_compliant_test design-processing/inline_05a.vhd
+build_compliant_test design-processing/tb_volume_sensor.vhd
+
+build_compliant_test digital-modeling/program_rom.vhd
+build_compliant_test digital-modeling/and_or_inv.vhd
+build_compliant_test digital-modeling/clock_gen.vhd
+build_compliant_test digital-modeling/mux.vhd
+build_compliant_test digital-modeling/edge_triggered_Dff.vhd
+build_compliant_test digital-modeling/mux2.vhd
+build_compliant_test digital-modeling/clock_gen-1.vhd
+build_compliant_test digital-modeling/clock_gen-2.vhd
+build_compliant_test digital-modeling/computer_system.vhd
+build_compliant_test digital-modeling/asym_delay.vhd
+build_compliant_test digital-modeling/and2.vhd
+build_compliant_test digital-modeling/zmux.vhd
+build_compliant_test digital-modeling/zmux-1.vhd
+build_compliant_test digital-modeling/scheduler.vhd
+build_compliant_test digital-modeling/alu.vhd
+build_compliant_test digital-modeling/full_adder.vhd
+build_compliant_test digital-modeling/S_R_flipflop.vhd
+build_compliant_test digital-modeling/S_R_flipflop-1.vhd
+build_compliant_test digital-modeling/rom.vhd
+build_compliant_test digital-modeling/reg4.vhd
+build_compliant_test digital-modeling/counter.vhd
+build_compliant_test digital-modeling/microprocessor.vhd
+build_compliant_test digital-modeling/inline_01.vhd
+build_compliant_test digital-modeling/inline_02.vhd
+build_compliant_test digital-modeling/inline_03.vhd
+build_compliant_test digital-modeling/inline_04.vhd
+build_compliant_test digital-modeling/inline_05.vhd
+build_compliant_test digital-modeling/inline_06.vhd
+build_compliant_test digital-modeling/inline_07.vhd
+build_compliant_test digital-modeling/inline_08.vhd
+build_compliant_test digital-modeling/inline_09.vhd
+build_compliant_test digital-modeling/inline_10.vhd
+build_compliant_test digital-modeling/inline_11.vhd
+build_compliant_test digital-modeling/inline_12.vhd
+build_compliant_test digital-modeling/inline_13.vhd
+build_compliant_test digital-modeling/inline_14.vhd
+build_compliant_test digital-modeling/inline_15.vhd
+build_compliant_test digital-modeling/inline_16.vhd
+build_compliant_test digital-modeling/inline_17.vhd
+build_compliant_test digital-modeling/inline_18.vhd
+build_compliant_test digital-modeling/inline_19.vhd
+build_compliant_test digital-modeling/inline_20.vhd
+build_compliant_test digital-modeling/inline_21.vhd
+build_compliant_test digital-modeling/inline_22.vhd
+build_compliant_test digital-modeling/inline_23.vhd
+build_compliant_test digital-modeling/inline_24.vhd
+build_compliant_test digital-modeling/inline_28a.vhd
+build_compliant_test digital-modeling/tb_and_or_inv.vhd
+build_compliant_test digital-modeling/tb_edge_triggered_Dff.vhd
+build_compliant_test digital-modeling/tb_mux2.vhd
+build_compliant_test digital-modeling/tb_and2.vhd
+build_compliant_test digital-modeling/tb_full_adder.vhd
+build_compliant_test digital-modeling/tb_S_R_flipflop.vhd
+build_compliant_test digital-modeling/tb_S_R_flipflop-1.vhd
+build_compliant_test digital-modeling/tb_rom.vhd
+build_compliant_test digital-modeling/tb_reg4.vhd
+build_compliant_test digital-modeling/tb_counter.vhd
+
+build_compliant_test files-and-IO/ROM.vhd
+build_compliant_test files-and-IO/stimulate_network.vhd
+build_compliant_test files-and-IO/CPU.vhd
+build_compliant_test files-and-IO/cache.vhd
+build_compliant_test files-and-IO/read_array.vhd
+build_compliant_test files-and-IO/stimulus_generator.vhd
+build_compliant_test files-and-IO/read_transform.vhd
+build_compliant_test files-and-IO/textio.vhd
+build_compliant_test files-and-IO/stimulus_interpreter-1.vhd
+build_compliant_test files-and-IO/bus_monitor.vhd
+build_compliant_test files-and-IO/inline_01.vhd
+build_compliant_test files-and-IO/inline_02.vhd
+build_compliant_test files-and-IO/inline_03.vhd
+build_compliant_test files-and-IO/inline_04.vhd
+build_compliant_test files-and-IO/inline_05.vhd
+build_compliant_test files-and-IO/inline_06.vhd
+build_compliant_test files-and-IO/inline_08.vhd
+build_compliant_test files-and-IO/inline_09.vhd
+build_compliant_test files-and-IO/inline_10.vhd
+build_compliant_test files-and-IO/tb_ROM.vhd
+build_compliant_test files-and-IO/tb_cache.vhd
+
+build_compliant_test frequency-modeling/v_source.vhd
+build_compliant_test frequency-modeling/v_source-1.vhd
+build_compliant_test frequency-modeling/nmos_transistor.vhd
+build_compliant_test frequency-modeling/nmos_transistor_wa.vhd
+build_compliant_test frequency-modeling/lowpass-1.vhd
+build_compliant_test frequency-modeling/lowpass-2.vhd
+build_compliant_test frequency-modeling/lowpass-3.vhd
+build_compliant_test frequency-modeling/opamp.vhd
+build_compliant_test frequency-modeling/opamp_2pole.vhd
+build_compliant_test frequency-modeling/opamp_2pole_res.vhd
+build_compliant_test frequency-modeling/lowpass-4.vhd
+build_compliant_test frequency-modeling/lowpass-5.vhd
+build_compliant_test frequency-modeling/lowpass.vhd
+build_compliant_test frequency-modeling/inline_01a.vhd
+build_compliant_test frequency-modeling/inline_02a.vhd
+build_compliant_test frequency-modeling/inline_03a.vhd
+build_compliant_test frequency-modeling/tb_v_source.vhd
+build_compliant_test frequency-modeling/tb_mosfet_noisy.vhd
+build_compliant_test frequency-modeling/tb_opamp.vhd
+build_compliant_test frequency-modeling/tb_opamp_2pole.vhd
+build_compliant_test frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd
+build_compliant_test frequency-modeling/tb_lpf_dot_ltf_ztf.vhd
+
+build_compliant_test fundamental/adc.vhd
+build_compliant_test fundamental/resistor.vhd
+build_compliant_test fundamental/vc_amp.vhd
+build_compliant_test fundamental/comparator.vhd
+build_compliant_test fundamental/d_ff.vhd
+build_compliant_test fundamental/propulsion.vhd
+build_compliant_test fundamental/test_bench-1.vhd
+build_compliant_test fundamental/tb_adc.vhd
+
+build_compliant_test generators/led_bar_display.vhd
+build_compliant_test generators/resistor_pack.vhd
+build_compliant_test generators/graphics_engine.vhd
+build_compliant_test generators/memory_board.vhd
+build_compliant_test generators/carry_chain.vhd
+build_compliant_test generators/computer_system.vhd
+build_compliant_test generators/fanout_tree.vhd
+build_compliant_test generators/computer_system-1.vhd
+build_compliant_test generators/architectural.vhd
+build_compliant_test generators/identical_devices.vhd
+build_compliant_test generators/down_to_chips.vhd
+build_compliant_test generators/last_pass_spice.vhd
+build_compliant_test generators/inline_01.vhd
+build_compliant_test generators/inline_02.vhd
+
+build_compliant_test generics/control_unit.vhd
+build_compliant_test generics/timer.vhd
+build_compliant_test generics/reg.vhd
+build_compliant_test generics/multiple_opamp.vhd
+build_compliant_test generics/inline_01.vhd
+build_compliant_test generics/inline_02a.vhd
+build_compliant_test generics/inline_03.vhd
+build_compliant_test generics/inline_05a.vhd
+build_compliant_test generics/inline_06.vhd
+build_compliant_test generics/inline_07.vhd
+build_compliant_test generics/inline_08.vhd
+build_compliant_test generics/inline_09a.vhd
+build_compliant_test generics/tb_timer_w_stim.vhd
+
+build_compliant_test guards-and-blocks/computer_system.vhd
+build_compliant_test guards-and-blocks/processor.vhd
+build_compliant_test guards-and-blocks/resolve.vhd
+build_compliant_test guards-and-blocks/tri_state_reg.vhd
+build_compliant_test guards-and-blocks/data_logger.vhd
+build_compliant_test guards-and-blocks/reg_read_selector.vhd
+build_compliant_test guards-and-blocks/processor_node.vhd
+build_compliant_test guards-and-blocks/latch.vhd
+build_compliant_test guards-and-blocks/computer_system-1.vhd
+build_compliant_test guards-and-blocks/sensor.vhd
+build_compliant_test guards-and-blocks/example_entity.vhd
+build_compliant_test guards-and-blocks/circuit.vhd
+build_compliant_test guards-and-blocks/full.vhd
+build_compliant_test guards-and-blocks/inline_01.vhd
+build_compliant_test guards-and-blocks/inline_02.vhd
+build_compliant_test guards-and-blocks/inline_03.vhd
+build_compliant_test guards-and-blocks/inline_04.vhd
+build_compliant_test guards-and-blocks/inline_05.vhd
+build_compliant_test guards-and-blocks/tb_full.vhd
+build_compliant_test guards-and-blocks/inline_06.vhd
+build_compliant_test guards-and-blocks/tb_tri_state_reg.vhd
+build_compliant_test guards-and-blocks/tb_latch.vhd
+build_compliant_test guards-and-blocks/tb_sensor.vhd
+
+build_compliant_test misc-topics/count2-1.vhd
+build_compliant_test misc-topics/limit_checker.vhd
+build_compliant_test misc-topics/test_bench.vhd
+build_compliant_test misc-topics/processor.vhd
+build_compliant_test misc-topics/SR_flipflop.vhd
+build_compliant_test misc-topics/inline_01.vhd
+build_compliant_test misc-topics/inline_02.vhd
+build_compliant_test misc-topics/inline_04a.vhd
+build_compliant_test misc-topics/tb_count2.vhd
+build_compliant_test misc-topics/tb_limit_checker.vhd
+build_compliant_test misc-topics/tb_SR_flipflop.vhd
+
+build_compliant_test packages/cpu_types.vhd
+build_compliant_test packages/address_decoder.vhd
+build_compliant_test packages/clock_power_pkg.vhd
+build_compliant_test packages/io_controller-1.vhd
+build_compliant_test packages/bus_sequencer-1.vhd
+build_compliant_test packages/analog_output_interface.vhd
+build_compliant_test packages/cpu_types-1.vhd
+build_compliant_test packages/cpu.vhd
+build_compliant_test packages/bit_vector_signed_arithmetic.vhd
+build_compliant_test packages/cpu-1.vhd
+build_compliant_test packages/lessthan.vhd
+build_compliant_test packages/test_alu.vhd
+build_compliant_test packages/inline_01.vhd
+build_compliant_test packages/inline_02.vhd
+build_compliant_test packages/inline_03.vhd
+build_compliant_test packages/inline_04a.vhd
+build_compliant_test packages/inline_05.vhd
+build_compliant_test packages/inline_06.vhd
+build_compliant_test packages/inline_08.vhd
+build_compliant_test packages/inline_09.vhd
+build_compliant_test packages/tb_address_decoder.vhd
+build_compliant_test packages/tb_bit_vector_signed_arithmetic.vhd
+
+build_compliant_test resolution/resolve_tri_state_logic.vhd
+build_compliant_test resolution/MVL4.vhd
+build_compliant_test resolution/tri_state_buffer.vhd
+build_compliant_test resolution/misc_logic.vhd
+build_compliant_test resolution/words.vhd
+build_compliant_test resolution/computer_system.vhd
+build_compliant_test resolution/memory_system.vhd
+build_compliant_test resolution/resolved.vhd
+build_compliant_test resolution/bus_based_system.vhd
+build_compliant_test resolution/synchronize.vhd
+build_compliant_test resolution/synchronized_module.vhd
+build_compliant_test resolution/inline_01.vhd
+build_compliant_test resolution/inline_02.vhd
+build_compliant_test resolution/inline_03.vhd
+
+build_compliant_test scalar-data/ent.vhd
+build_compliant_test scalar-data/int_types.vhd
+build_compliant_test scalar-data/small_adder.vhd
+build_compliant_test scalar-data/inline_01a.vhd
+
+build_compliant_test sequential-statements/thermostat-1.vhd
+build_compliant_test sequential-statements/mux4.vhd
+build_compliant_test sequential-statements/counter.vhd
+build_compliant_test sequential-statements/counter-1.vhd
+build_compliant_test sequential-statements/cos.vhd
+build_compliant_test sequential-statements/SR_flipflop.vhd
+build_compliant_test sequential-statements/max3.vhd
+build_compliant_test sequential-statements/edge_triggered_register.vhd
+build_compliant_test sequential-statements/inline_01.vhd
+build_compliant_test sequential-statements/inline_02.vhd
+build_compliant_test sequential-statements/inline_03.vhd
+build_compliant_test sequential-statements/inline_04a.vhd
+build_compliant_test sequential-statements/inline_05.vhd
+build_compliant_test sequential-statements/inline_06.vhd
+build_compliant_test sequential-statements/inline_07.vhd
+build_compliant_test sequential-statements/inline_08.vhd
+build_compliant_test sequential-statements/inline_09.vhd
+build_compliant_test sequential-statements/inline_10a.vhd
+build_compliant_test sequential-statements/inline_11.vhd
+build_compliant_test sequential-statements/inline_12.vhd
+build_compliant_test sequential-statements/inline_13.vhd
+build_compliant_test sequential-statements/inline_14.vhd
+build_compliant_test sequential-statements/inline_15.vhd
+build_compliant_test sequential-statements/inline_16.vhd
+build_compliant_test sequential-statements/inline_17.vhd
+build_compliant_test sequential-statements/inline_18.vhd
+build_compliant_test sequential-statements/inline_19.vhd
+build_compliant_test sequential-statements/tb_mux4.vhd
+build_compliant_test sequential-statements/tb_counter.vhd
+build_compliant_test sequential-statements/tb_counter-1.vhd
+build_compliant_test sequential-statements/tb_cos.vhd
+build_compliant_test sequential-statements/tb_cos-1.vhd
+build_compliant_test sequential-statements/tb_SR_flipflop.vhd
+build_compliant_test sequential-statements/tb_max3.vhd
+build_compliant_test sequential-statements/tb_edge_triggered_register.vhd
+
+build_compliant_test subprograms/average_samples.vhd
+build_compliant_test subprograms/control_processor.vhd
+build_compliant_test subprograms/instruction_interpreter.vhd
+build_compliant_test subprograms/control_sequencer.vhd
+build_compliant_test subprograms/instruction_interpreter-1.vhd
+build_compliant_test subprograms/do_arith_op.vhd
+build_compliant_test subprograms/addu.vhd
+build_compliant_test subprograms/negate.vhd
+build_compliant_test subprograms/receiver.vhd
+build_compliant_test subprograms/signal_generator.vhd
+build_compliant_test subprograms/increment.vhd
+build_compliant_test subprograms/find_first_set.vhd
+build_compliant_test subprograms/bv_lt.vhd
+build_compliant_test subprograms/check_setup.vhd
+build_compliant_test subprograms/generate_clock.vhd
+build_compliant_test subprograms/limited.vhd
+build_compliant_test subprograms/bv_to_natural.vhd
+build_compliant_test subprograms/network_driver.vhd
+build_compliant_test subprograms/hold_time_checker.vhd
+build_compliant_test subprograms/v_source.vhd
+build_compliant_test subprograms/freq_detect.vhd
+build_compliant_test subprograms/mixer.vhd
+build_compliant_test subprograms/mixer_wa.vhd
+build_compliant_test subprograms/motor_system.vhd
+build_compliant_test subprograms/motor_system_wa.vhd
+build_compliant_test subprograms/reg_ctrl.vhd
+build_compliant_test subprograms/ent.vhd
+build_compliant_test subprograms/cache.vhd
+build_compliant_test subprograms/p1.vhd
+build_compliant_test subprograms/inline_01.vhd
+build_compliant_test subprograms/inline_02.vhd
+build_compliant_test subprograms/inline_03.vhd
+build_compliant_test subprograms/inline_04a.vhd
+build_compliant_test subprograms/inline_05a.vhd
+build_compliant_test subprograms/inline_06a.vhd
+build_compliant_test subprograms/inline_07.vhd
+build_compliant_test subprograms/inline_08.vhd
+build_compliant_test subprograms/tb_v_source.vhd
+build_compliant_test subprograms/tb_freq_detect.vhd
+build_compliant_test subprograms/tb_mixer.vhd
+build_compliant_test subprograms/tb_motor_system.vhd
+build_compliant_test subprograms/tb_reg_ctrl.vhd
+
+end_test_group
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd
new file mode 100644
index 000000000..71b19f557
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+use work.automotive_valve_defs.all;
+
+entity automotive_valve is
+ port ( terminal p1, p2 : valve_fluidic;
+ terminal control : valve_translational );
+end entity automotive_valve;
+
+
+-- not in book
+
+architecture test of automotive_valve is
+begin
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd
new file mode 100644
index 000000000..bf41f4883
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.fluidic_systems.all, ieee_proposed.mechanical_systems.all;
+
+package automotive_valve_defs is
+
+ subnature valve_fluidic is fluidic
+ tolerance "valve_pressure" across "valve_vflow_rate" through;
+
+ subnature valve_translational is translational
+ tolerance "valve_displacement" across "valve_force" through;
+
+ -- ... -- other useful declarations
+
+ component automotive_valve is
+ port ( terminal p1, p2 : valve_fluidic;
+ terminal control : valve_translational );
+ end component automotive_valve;
+
+end package automotive_valve_defs;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd
new file mode 100644
index 000000000..0d7a4ad23
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+use work.automotive_valve_defs.all;
+
+entity brake_system is
+end entity brake_system;
+
+-- end not in book
+
+
+
+architecture structure of brake_system is
+
+ use work.automotive_valve_defs.all;
+
+ -- ... -- declarations of other components, terminals, etc
+
+ -- not in book
+ terminal master_reservoir, brake_line : valve_fluidic;
+ terminal brake_pedal : valve_translational;
+ -- end not in book
+
+begin
+
+ pedal_valve : component automotive_valve
+ port map ( p1 => master_reservoir,
+ p2 => brake_line,
+ control => brake_pedal );
+
+ -- ... -- other component instances
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd
new file mode 100644
index 000000000..d0ee652ce
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+configuration computer_structure of computer_system is
+
+ for structure
+
+ for interface_decoder : decoder_2_to_4
+ use entity work.decoder_3_to_8(basic)
+ generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
+ port map ( s0 => in0, s1 => in1, s2 => '0',
+ enable => '1',
+ y0 => out0, y1 => out1, y2 => out2, y3 => out3,
+ y4 => open, y5 => open, y6 => open, y7 => open );
+ end for;
+
+ -- . . .
+
+ end for;
+
+end configuration computer_structure;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd
new file mode 100644
index 000000000..df8a7b60b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+
+library util; use util.stimulus_generators.all;
+
+-- end not in book
+
+
+architecture structure of computer_system is
+
+ component decoder_2_to_4 is
+ generic ( prop_delay : delay_length );
+ port ( in0, in1 : in bit;
+ out0, out1, out2, out3 : out bit );
+ end component decoder_2_to_4;
+
+ -- . . .
+
+ -- not in book
+
+ signal addr : bit_vector(5 downto 4);
+ signal interface_a_select, interface_b_select,
+ interface_c_select, interface_d_select : bit;
+ -- end not in book
+
+begin
+
+ interface_decoder : component decoder_2_to_4
+ generic map ( prop_delay => 4 ns )
+ port map ( in0 => addr(4), in1 => addr(5),
+ out0 => interface_a_select, out1 => interface_b_select,
+ out2 => interface_c_select, out3 => interface_d_select );
+
+ -- . . .
+
+ -- not in book
+
+ all_possible_values(addr, 10 ns);
+
+ -- end not in book
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd
new file mode 100644
index 000000000..3729acba9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity control_section is
+end entity control_section;
+
+-- end not in book
+
+
+architecture structural of control_section is
+
+ component reg is
+ generic ( width : positive );
+ port ( clk : in std_logic;
+ d : in std_logic_vector(0 to width - 1);
+ q : out std_logic_vector(0 to width - 1) );
+ end component reg;
+
+ for flag_reg : reg
+ use entity work.reg(gate_level)
+ port map ( clock => clk, data_in => d, data_out => q );
+
+ -- . . .
+
+ -- not in book
+ signal clock_phase1, zero_result, neg_result, overflow_result,
+ zero_flag, neg_flag, overflow_flag : std_logic;
+ -- end not in book
+
+begin
+
+ flag_reg : component reg
+ generic map ( width => 3 )
+ port map ( clk => clock_phase1,
+ d(0) => zero_result, d(1) => neg_result,
+ d(2) => overflow_result,
+ q(0) => zero_flag, q(1) => neg_flag,
+ q(2) => overflow_flag );
+
+ -- . . .
+
+ -- not in book
+
+ stimulus : process is
+ begin
+ clock_phase1 <= '0';
+ zero_result <= '0'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
+ clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
+ zero_result <= '0'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
+ clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
+ zero_result <= '0'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
+ clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
+ zero_result <= '0'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
+ clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
+ zero_result <= '1'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
+ clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
+ zero_result <= '1'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
+ clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
+ zero_result <= '1'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
+ clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
+ zero_result <= '1'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
+ clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+ -- end not in book
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd
new file mode 100644
index 000000000..d7b8ac4cf
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+configuration controller_with_timing of control_section is
+
+ for structural
+
+ for flag_reg : reg
+ generic map ( t_setup => 200 ps, t_hold => 150 ps,
+ t_pd => 150 ps, width => width )
+ port map ( reset_n => '1' );
+ end for;
+
+ -- . . .
+
+ end for;
+
+end configuration controller_with_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd
new file mode 100644
index 000000000..eba7230ea
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity decoder_3_to_8 is
+ generic ( Tpd_01, Tpd_10 : delay_length );
+ port ( s0, s1, s2 : in bit;
+ enable : in bit;
+ y0, y1, y2, y3, y4, y5, y6, y7 : out bit );
+end entity decoder_3_to_8;
+
+
+-- not in book
+
+architecture basic of decoder_3_to_8 is
+begin
+
+ process (enable, s2, s1, s0) is
+ begin
+ if enable = '0' then
+ (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000000");
+ else
+ case bit_vector'(s2, s1, s0) is
+ when "000" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000001");
+ when "001" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000010");
+ when "010" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000100");
+ when "011" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00001000");
+ when "100" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00010000");
+ when "101" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00100000");
+ when "110" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("01000000");
+ when "111" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("10000000");
+ end case;
+ end if;
+ end process;
+
+end architecture basic;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd
new file mode 100644
index 000000000..2c4163ba3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity fm_radio is
+end entity fm_radio;
+
+-- end not in book
+
+
+
+architecture top_level of fm_radio is
+
+ terminal left_decoded, left_filtered : electrical;
+ terminal right_decoded, right_filtered : electrical;
+ -- ...
+
+begin
+
+ left_pilot_filter : configuration work.notch_filter_down_to_device_level
+ port map ( input => left_decoded, output => left_filtered,
+ vdd => vdd, vss => vss, gnd => gnd );
+
+ -- ...
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/index-ams.txt
new file mode 100644
index 000000000..58e31b1be
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/index-ams.txt
@@ -0,0 +1,47 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 16 - Components and Configurations
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+opamp.vhd entity bulk_cmos_nfet basic, detailed --
+-- entity opamp struct Figure 16-1
+automotive_valve_defs.vhd package automotive_valve_defs -- Figure 16-2
+automotive_valve.vhd entity automotive_valve test Figure 16-3
+brake_system.vhd entity brake_system structure Figure 16-4
+opamp_mosfets.vhd configuration opamp_mosfets -- Figure 16-5
+notch_filter.vhd entity notch_filter opamp_based Figure 16-6
+notch_filter_down_to_device_level.vhd configuration notch_filter_down_to_device_level -- Figure 16-7
+notch_filter_full.vhd configuration full -- Figure 16-8
+fm_radio.vhd entity fm_radio top_level Figure 16-9
+successive_approx_adc.vhd entity successive_approx_adc struct Figure 16-10
+sensor_interface.vhd entity sensor_interface structural Figure 16-11
+sensor_interface_with_timing.vhd configuration sensor_interface_with_timing -- Figure 16-12
+computer_system.vhd entity computer_system structure Figure 16-13
+decoder_3_to_8.vhd entity decoder_3_to_8 basic Figure 16-14
+computer_structure.vhd configuration computer_structure -- Figure 16-15
+single_board_computer.vhd entity single_board_computer structural Figure 16-17
+intermediate.vhd entity XYZ3000_cpu full_function --
+-- entity memory_array behavioral --
+-- configuration intermediate -- Figure 16-18
+logic_block.vhd entity nand3 behavioral --
+-- entity logic_block ideal Figure 16-19
+reg-1.vhd entity reg gate_level Figure 16-21
+control_section.vhd entity control_section structural Figure 16-20
+controller_with_timing-1.vhd configuration controller_with_timing -- Figure 16-22
+interlock_control.vhd entity not_gate primitive --
+-- entity interlock_control detailed_timing Figure 16-23
+interlock_control_with_estimates.vhd configuration interlock_control_with_estimates -- Figure 16-24
+-- configuration interlock_control_with_actual -- Figure 16-24
+misc_logic.vhd entity misc_logic gate_level Figure 16-25
+misc_logic_reconfigured.vhd configuration misc_logic_reconfigured -- Figure 16-26
+inline_02a.vhd configuration inline_02a -- Section 16.2
+inline_04a.vhd entity inline_04a test --
+-- configuration inline_04a_test -- Section 16.2
+inline_05.vhd entity inline_05 test Section 16.2
+-- entity nand2 -- Section 16.2
+-- configuration inline_05_test -- Section 16.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd
new file mode 100644
index 000000000..41f40cbbe
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+configuration inline_02a of opamp is
+
+ for struct
+
+ -- code from book (in text)
+
+ for m1, m2 : nfet
+ use entity work.bulk_cmos_nfet(basic);
+ end for;
+
+ -- end code from book
+
+ end for;
+
+end configuration inline_02a;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd
new file mode 100644
index 000000000..9447cb34a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_04a is
+end entity inline_04a;
+
+
+architecture test of inline_04a is
+
+ component opamp is
+ port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
+ end component opamp;
+
+ terminal plus_in, minus_in, output, vdd, vss, gnd : electrical;
+
+begin
+
+ voltage_amp : component opamp
+ port map ( plus_in => plus_in, minus_in => minus_in, output => output,
+ vdd => vdd, vss => vss, gnd => gnd );
+
+end architecture test;
+
+
+configuration inline_04a_test of inline_04a is
+
+ for test
+
+ -- code from book (in text)
+
+ for voltage_amp : opamp
+ use configuration work.opamp_mosfets;
+ end for;
+
+ -- end code from book
+
+ end for;
+
+end configuration inline_04a_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd
new file mode 100644
index 000000000..ec39f8d0c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_05 is
+end entity inline_05;
+
+
+architecture test of inline_05 is
+
+ -- code from book
+
+ component nand3 is
+ port ( a, b, c : in bit := '1'; y : out bit );
+ end component nand3;
+
+ -- end code from book
+
+ signal s1, s2, s3 : bit;
+
+begin
+
+ -- code from book
+
+ gate1 : component nand3
+ port map ( a => s1, b => s2, c => open, y => s3 );
+
+ -- end code from book
+
+end architecture test;
+
+
+
+-- code from book
+
+entity nand2 is
+ port ( a, b : in bit := '1'; y : out bit );
+end entity nand2;
+
+-- end code from book
+
+
+
+
+configuration inline_05_test of inline_05 is
+
+ for test
+
+ -- code from book
+
+ for gate1 : nand3
+ use entity work.nand2(basic);
+ end for;
+
+ -- end code from book
+
+ end for;
+
+end configuration inline_05_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd
new file mode 100644
index 000000000..fe566b0e2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity nor_gate is
+ generic ( width : positive;
+ Tpd01, Tpd10 : delay_length );
+ port ( input : in std_logic_vector(0 to width - 1);
+ output : out std_logic );
+end entity nor_gate;
+
+
+architecture primitive of nor_gate is
+
+ function max ( a, b : delay_length ) return delay_length is
+ begin
+ if a > b then
+ return a;
+ else
+ return b;
+ end if;
+ end function max;
+
+begin
+
+ reducer : process (input) is
+ variable result : std_logic;
+ begin
+ result := '0';
+ for index in input'range loop
+ result := result or input(index);
+ end loop;
+ if not result = '1' then
+ output <= not result after Tpd01;
+ elsif not result = '0' then
+ output <= not result after Tpd10;
+ else
+ output <= not result after max(Tpd01, Tpd10);
+ end if;
+ end process reducer;
+
+end architecture primitive;
+
+
+library ieee; use ieee.std_logic_1164.all;
+library cell_lib;
+
+entity interlock_control is
+end entity interlock_control;
+
+
+-- code from book
+
+architecture detailed_timing of interlock_control is
+
+ component nor_gate is
+ generic ( input_width : positive );
+ port ( input : in std_logic_vector(0 to input_width - 1);
+ output : out std_logic );
+ end component nor_gate;
+
+ for ex_interlock_gate : nor_gate
+ use entity cell_lib.nor_gate(primitive)
+ generic map ( width => input_width,
+ Tpd01 => 250 ps, Tpd10 => 200 ps ); -- estimates
+
+ -- . . .
+
+ -- not in book
+ signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
+ -- end not in book
+
+begin
+
+ ex_interlock_gate : component nor_gate
+ generic map ( input_width => 2 )
+ port map ( input(0) => reg_access_hazard,
+ input(1) => load_hazard,
+ output => stall_ex_n);
+
+ -- . . .
+
+ -- not in book
+
+ reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;
+
+ load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
+ '0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
+ '0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
+ '0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;
+
+ -- end not in book
+
+end architecture detailed_timing;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd
new file mode 100644
index 000000000..f6d4a51e6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+configuration interlock_control_with_estimates of interlock_control is
+
+ for detailed_timing
+
+ end for;
+
+ -- . . .
+
+end configuration interlock_control_with_estimates;
+
+--------------------------------------------------
+
+configuration interlock_control_with_actual of interlock_control is
+
+ for detailed_timing
+
+ for ex_interlock_gate : nor_gate
+ generic map ( Tpd01 => 320 ps, Tpd10 => 230 ps );
+ end for;
+
+ -- . . .
+
+ end for;
+
+end configuration interlock_control_with_actual;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd
new file mode 100644
index 000000000..53342b411
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- analyze into resource library chips
+
+entity XYZ3000_cpu is
+ port ( clock : in bit; addr_data : inout bit_vector(31 downto 0);
+ other_port : in bit := '0' );
+end entity XYZ3000_cpu;
+
+
+architecture full_function of XYZ3000_cpu is
+begin
+end architecture full_function;
+
+
+-- analyze into work library
+
+entity memory_array is
+ port ( addr : in bit_vector(25 downto 0); other_port : in bit := '0' );
+end entity memory_array;
+
+
+architecture behavioral of memory_array is
+begin
+end architecture behavioral;
+
+
+
+-- code from book
+
+library chips;
+
+configuration intermediate of single_board_computer is
+
+ for structural
+
+ for cpu : processor
+ use entity chips.XYZ3000_cpu(full_function)
+ port map ( clock => clk, addr_data => a_d, -- . . . );
+ -- not in book
+ other_port => open );
+ -- end not in book
+ end for;
+
+ for main_memory : memory
+ use entity work.memory_array(behavioral);
+ end for;
+
+ for all : serial_interface
+ use open;
+ end for;
+
+ -- . . .
+
+ end for;
+
+end configuration intermediate;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd
new file mode 100644
index 000000000..a1d95b85c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book (in text)
+
+entity nand3 is
+ port ( a, b, c : in bit; y : out bit );
+end entity nand3;
+
+-- end code from book
+
+architecture behavioral of nand3 is
+begin
+ y <= not (a and b and c);
+end architecture behavioral;
+
+
+
+entity logic_block is
+end entity logic_block;
+
+
+-- code from book
+
+library gate_lib;
+
+architecture ideal of logic_block is
+
+ component nand2 is
+ port ( in1, in2 : in bit; result : out bit );
+ end component nand2;
+
+ for all : nand2
+ use entity gate_lib.nand3(behavioral)
+ port map ( a => in1, b => in2, c => '1', y => result );
+
+ -- . . . -- other declarations
+
+ -- not in book
+ signal s1, s2, s3 : bit := '0';
+
+begin
+
+ gate1 : component nand2
+ port map ( in1 => s1, in2 => s2, result => s3 );
+
+ -- . . . -- other concurrent statements
+
+ -- not in book
+
+ s1 <= '1' after 20 ns;
+
+ s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
+
+ -- end not in book
+
+end architecture ideal;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd
new file mode 100644
index 000000000..da51c5802
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library project_lib;
+library util; use util.stimulus_generators.all;
+
+entity misc_logic is
+end entity misc_logic;
+
+
+-- code from book
+
+architecture gate_level of misc_logic is
+
+ component nand3 is
+ generic ( Tpd : delay_length );
+ port ( a, b, c : in bit; y : out bit );
+ end component nand3;
+
+ for all : nand3
+ use entity project_lib.nand3(basic);
+
+ -- . . .
+
+ -- not in book
+ signal sig1, sig2, sig3, out_sig : bit;
+ signal test_vector : bit_vector(1 to 3);
+ -- end not in book
+
+begin
+
+ gate1 : component nand3
+ generic map ( Tpd => 2 ns )
+ port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
+
+ -- . . .
+
+ -- not in book
+
+ all_possible_values(test_vector, 10 ns);
+
+ (sig1, sig2, sig3) <= test_vector;
+
+ -- end not in book
+
+end architecture gate_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd
new file mode 100644
index 000000000..7a4a73519
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+configuration misc_logic_reconfigured of misc_logic is
+
+ for gate_level
+
+ for gate1 : nand3
+ generic map ( Tpd => 1.6 ns )
+ port map ( a => c, c => a, b => b, y => y );
+ end for;
+
+ end for;
+
+end configuration misc_logic_reconfigured;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd
new file mode 100644
index 000000000..00842f4c4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity notch_filter is
+ port ( terminal input, output, vdd, vss, gnd : electrical );
+end entity notch_filter;
+
+----------------------------------------------------------------
+
+architecture opamp_based of notch_filter is
+
+ component simple_opamp is
+ port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
+ end component simple_opamp;
+ -- ...
+
+ terminal opamp1_in, opamp1_out, opamp2_in, -- ...
+ -- not in book
+ other_terminal
+ -- end not in book
+ : electrical;
+
+begin
+
+ opamp1 : component simple_opamp
+ port map ( plus_in => gnd, minus_in => opamp1_in, output => opamp1_out,
+ vdd => vdd, vss => vss, gnd => gnd );
+
+ opamp2 : component simple_opamp
+ port map ( plus_in => gnd, minus_in => opamp2_in, output => output,
+ vdd => vdd, vss => vss, gnd => gnd );
+
+ -- other component instances
+ -- ...
+
+end architecture opamp_based;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd
new file mode 100644
index 000000000..0d3098039
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+configuration notch_filter_down_to_device_level of notch_filter is
+
+ for opamp_based
+
+ for all : simple_opamp
+ use configuration work.opamp_mosfets;
+ end for;
+
+ -- ... -- bindings for other component instances
+
+ end for; -- end of architecture opamp_based
+
+end configuration notch_filter_down_to_device_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd
new file mode 100644
index 000000000..93eee766a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library cmos_lib; use cmos_lib.bulk_cmos_nfet;
+
+configuration full of notch_filter is
+
+ for opamp_based -- architecture of notch_filter
+
+ for all : simple_opamp
+ use entity work.opamp(struct);
+
+ for struct -- architecture of opamp
+
+ for m1, m2 : nfet
+ use entity bulk_cmos_nfet(detailed);
+ end for;
+
+ for others : nfet
+ use entity bulk_cmos_nfet(basic);
+ end for;
+
+ -- ...
+
+ end for; -- end of architecture struct
+
+ end for;
+
+ -- ... -- bindings for other component instances
+
+ end for; -- end of architecture opamp_based
+
+end configuration full;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd
new file mode 100644
index 000000000..f6805923e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity bulk_cmos_nfet is
+ generic ( Vt : real;
+ transconductance : real );
+ port ( terminal gate, drain, source : electrical );
+end entity bulk_cmos_nfet;
+
+
+architecture basic of bulk_cmos_nfet is
+begin
+end architecture basic;
+
+
+architecture detailed of bulk_cmos_nfet is
+begin
+end architecture detailed;
+
+
+-- code from book
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity opamp is
+ port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
+end entity opamp;
+
+----------------------------------------------------------------
+
+architecture struct of opamp is
+
+ component nfet is
+ generic ( Vt : real;
+ transconductance : real );
+ port ( terminal gate, drain, source : electrical );
+ end component nfet;
+
+ terminal int_1, int_2, int_3, -- ...
+ -- not in book
+ other_terminal
+ -- end not in book
+ : electrical;
+
+begin
+
+ m1 : component nfet
+ generic map ( Vt => 0.026, transconductance => 1.0 )
+ port map ( gate => plus_in, drain => int_1, source => int_2 );
+
+ m2 : component nfet
+ generic map ( Vt => 0.026, transconductance => 1.0 )
+ port map ( gate => minus_in, drain => int_1, source => int_3 );
+
+ -- other component instances
+ -- ...
+
+end architecture struct;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd
new file mode 100644
index 000000000..42f238294
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library cmos_lib;
+use cmos_lib.bulk_cmos_nfet;
+
+configuration opamp_mosfets of opamp is
+
+ for struct -- architecture of opamp
+
+ for m1, m2 : nfet
+ use entity bulk_cmos_nfet(detailed);
+ end for;
+
+ for others : nfet
+ use entity bulk_cmos_nfet(basic);
+ end for;
+
+ -- ...
+
+ end for; -- end of architecture struct
+
+end configuration opamp_mosfets;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd
new file mode 100644
index 000000000..445b8888a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity reg is
+ generic ( t_setup, t_hold, t_pd : delay_length;
+ width : positive );
+ port ( clock : in std_logic;
+ reset_n : in std_logic := 'H';
+ data_in : in std_logic_vector(0 to width - 1);
+ data_out : out std_logic_vector(0 to width - 1) );
+end entity reg;
+
+
+
+-- not in book
+
+architecture gate_level of reg is
+
+begin
+
+ store : process (clock, reset_n) is
+ begin
+ if reset_n = '0' or reset_n = 'L' then
+ data_out <= (others => '0') after t_pd;
+ elsif rising_edge(clock) then
+ data_out <= data_in after t_pd;
+ end if;
+ end process store;
+
+end architecture gate_level;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd
new file mode 100644
index 000000000..d676652b3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity sensor_interface is
+
+end entity sensor_interface;
+
+-- end not in book
+
+
+
+architecture structural of sensor_interface is
+
+ component adc is
+ generic ( width : positive );
+ port ( terminal analog_in : electrical;
+ signal clock : in std_logic;
+ signal start : in std_logic;
+ signal eoc : out std_logic;
+ signal data_out : out std_logic_vector(0 to width - 1) );
+ end component adc;
+
+ -- ...
+
+ -- not in book
+ terminal sensor_input : electrical;
+ signal clk, start_conversion, end_conversion : std_logic;
+ signal sensor_data : std_logic_vector(0 to 7);
+ -- end not in book
+
+begin
+
+ sensor_adc : component adc
+ generic map ( width => sensor_data'length )
+ port map ( analog_in => sensor_input,
+ clock => clk,
+ start => start_conversion,
+ eoc => end_conversion,
+ data_out => sensor_data );
+
+ -- ...
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd
new file mode 100644
index 000000000..c7a03a394
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+configuration sensor_interface_with_timing of sensor_interface is
+
+ for structural
+
+ for sensor_adc : adc
+ use entity work.successive_approx_adc(struct)
+ generic map ( t_setup => 200 ps, t_hold => 150 ps, t_pd => 150 ps,
+ width => width );
+ end for;
+
+ -- ...
+
+ end for;
+
+end configuration sensor_interface_with_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd
new file mode 100644
index 000000000..10be48856
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+entity single_board_computer is
+end entity single_board_computer;
+-- end not in book
+
+
+architecture structural of single_board_computer is
+
+ -- . . . -- type and signal declarations
+
+ -- not in book
+
+ subtype word is bit_vector(31 downto 0);
+ signal sys_clk : bit;
+ signal cpu_a_d, latched_addr : word;
+
+ -- end not in book
+
+ component processor is
+ port ( clk : in bit; a_d : inout word; -- . . . );
+ -- not in book
+ other_port : in bit := '0' );
+ -- end not in book
+ end component processor;
+
+ component memory is
+ port ( addr : in bit_vector(25 downto 0); -- . . . );
+ -- not in book
+ other_port : in bit := '0' );
+ -- end not in book
+ end component memory;
+
+ component serial_interface is
+ port ( clk : in bit; address : in bit_vector(3 downto 0); -- . . . );
+ -- not in book
+ other_port : in bit := '0' );
+ -- end not in book
+ end component serial_interface;
+
+begin
+
+ cpu : component processor
+ port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . );
+ -- not in book
+ other_port => open );
+ -- end not in book
+
+ main_memory : component memory
+ port map ( addr => latched_addr(25 downto 0), -- . . . );
+ -- not in book
+ other_port => open );
+ -- end not in book
+
+ serial_interface_a : component serial_interface
+ port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . );
+ -- not in book
+ other_port => open );
+ -- end not in book
+
+ -- . . .
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd
new file mode 100644
index 000000000..18de7922e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity successive_approx_adc is
+ generic ( t_setup, t_hold, t_pd : delay_length;
+ width : positive );
+ port ( terminal analog_in : electrical;
+ signal clock : in std_logic;
+ signal start : in std_logic;
+ signal eoc : out std_logic;
+ signal data_out : out std_logic_vector(0 to width - 1) );
+end entity successive_approx_adc;
+
+
+-- not in book
+
+architecture struct of successive_approx_adc is
+
+begin
+
+end architecture struct;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd
new file mode 100644
index 000000000..598232905
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity and_multiple is
+ port ( i : in bit_vector; y : out bit );
+end entity and_multiple;
+
+--------------------------------------------------
+
+architecture behavioral of and_multiple is
+begin
+
+ and_reducer : process ( i ) is
+ variable result : bit;
+ begin
+ result := '1';
+ for index in i'range loop
+ result := result and i(index);
+ end loop;
+ y <= result;
+ end process and_reducer;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd
new file mode 100644
index 000000000..105f11fc7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book:
+
+package byte_swap_types is
+
+ subtype halfword is bit_vector(0 to 15);
+
+end package byte_swap_types;
+
+
+use work.byte_swap_types.all;
+
+-- end not in book:
+
+
+entity byte_swap is
+ port (input : in halfword; output : out halfword);
+end entity byte_swap;
+
+--------------------------------------------------
+
+architecture behavior of byte_swap is
+
+begin
+
+ swap : process (input)
+ begin
+ output(8 to 15) <= input(0 to 7);
+ output(0 to 7) <= input(8 to 15);
+ end process swap;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd
new file mode 100644
index 000000000..8650058e1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book:
+
+package coeff_ram_types is
+
+ subtype coeff_ram_address is integer range 0 to 63;
+
+end package coeff_ram_types;
+
+
+
+use work.coeff_ram_types.all;
+
+-- end not in book
+
+
+entity coeff_ram is
+ port ( rd, wr : in bit; addr : in coeff_ram_address;
+ d_in : in real; d_out : out real );
+end entity coeff_ram;
+
+--------------------------------------------------
+
+architecture abstract of coeff_ram is
+begin
+
+ memory : process is
+ type coeff_array is array (coeff_ram_address) of real;
+ variable coeff : coeff_array;
+ begin
+ for index in coeff_ram_address loop
+ coeff(index) := 0.0;
+ end loop;
+ loop
+ wait on rd, wr, addr, d_in;
+ if rd = '1' then
+ d_out <= coeff(addr);
+ end if;
+ if wr = '1' then
+ coeff(addr) := d_in;
+ end if;
+ end loop;
+ end process memory;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd
new file mode 100644
index 000000000..2fd0f47db
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book:
+
+entity computer is
+
+end entity computer;
+
+-- end not in book
+
+
+architecture system_level of computer is
+
+ type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, -- . . .);
+ -- not in book:
+ nop);
+ -- end not in book
+ type reg_number is range 0 to 31;
+ constant r0 : reg_number := 0; constant r1 : reg_number := 1; -- . . .
+ -- not in book:
+ constant r2 : reg_number := 2;
+ -- end not in book
+
+ type instruction is record
+ opcode : opcodes;
+ source_reg1, source_reg2, dest_reg : reg_number;
+ displacement : integer;
+ end record instruction;
+
+ type word is record
+ instr : instruction;
+ data : bit_vector(31 downto 0);
+ end record word;
+
+ signal address : natural;
+ signal read_word, write_word : word;
+ signal mem_read, mem_write : bit := '0';
+ signal mem_ready : bit := '0';
+
+begin
+
+ cpu : process is
+ variable instr_reg : instruction;
+ variable PC : natural;
+ -- . . . -- other declarations for register file, etc.
+ begin
+ address <= PC;
+ mem_read <= '1';
+ wait until mem_ready = '1';
+ instr_reg := read_word.instr;
+ mem_read <= '0';
+ -- not in book:
+ wait until mem_ready = '0';
+ -- end not in book
+ PC := PC + 4;
+ case instr_reg.opcode is -- execute the instruction
+ -- . . .
+ -- not in book:
+ when others => null;
+ -- end not in book
+ end case;
+ end process cpu;
+
+ memory : process is
+ subtype address_range is natural range 0 to 2**14 - 1;
+ type memory_array is array (address_range) of word;
+ variable store : memory_array :=
+ ( 0 => ( ( ld, r0, r0, r2, 40 ), X"00000000" ),
+ 1 => ( ( breq, r2, r0, r0, 5 ), X"00000000" ),
+ -- . . .
+ 40 => ( ( nop, r0, r0, r0, 0 ), X"FFFFFFFE"),
+ others => ( ( nop, r0, r0, r0, 0 ), X"00000000") );
+ begin
+ -- . . .
+ -- not in book:
+ wait until mem_read = '1';
+ read_word <= store(address);
+ mem_ready <= '1';
+ wait until mem_read = '0';
+ mem_ready <= '0';
+ -- end not in book
+ end process memory;
+
+end architecture system_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/index-ams.txt
new file mode 100644
index 000000000..9bcec8138
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/index-ams.txt
@@ -0,0 +1,39 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 4 - Composite Data Types
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+coeff_ram.vhd package coeff_ram_types -- Section 4.1
+-- entity coeff_ram abstract Figure 4-1
+transmission_lines.vhd package transmission_lines_types -- Section 4.1
+-- entity transmission_lines abstract Figure 4-2
+modem_controller.vhd entity modem_controller test Figure 4-4
+and_multiple.vhd entity and_multiple behavioral Figure 4-5
+tb_and_multiple.vhd tb_and_multiple test_behavioral Section 4.2
+byte_swap.vhd package byte_swap_types -- Section 4.3
+-- entity byte_swap behavior Figure 4-6
+computer.vhd entity computer system_level Figure 4-7
+inline_01.vhd entity inline_01 test Section 4.1
+inline_02a.vhd entity inline_02a test Section 4.1
+inline_03.vhd entity inline_03 test Section 4.1
+inline_04a.vhd entity inline_04a test Section 4.1
+inline_05.vhd entity inline_05 test Section 4.1
+inline_06a.vhd entity inline_06a test Section 4.1
+inline_07a.vhd entity inline_07a test Section 4.1
+inline_08.vhd entity inline_08 test Section 4.2
+inline_09a.vhd entity inline_09a test Section 4.2
+inline_10.vhd entity inline_10 test Section 4.2
+inline_11a.vhd entity inline_11a test Section 4.2
+inline_12.vhd entity inline_12 test Section 4.3
+inline_13.vhd entity inline_13 test Section 4.3
+inline_14a.vhd entity inline_14a test Section 4.3
+inline_15.vhd entity inline_15 test Section 4.3
+inline_16.vhd entity inline_16 test Section 4.4
+inline_17a.vhd entity inline_17a test Section 4.4
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_coeff_ram.vhd entity tb_coeff_ram test_abstract coeff_ram.vhd
+tb_byte_swap.vhd entity tb_byte_swap test_behavior byte_swap.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd
new file mode 100644
index 000000000..4997a79e2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+ block_1_a : block is
+
+ -- code from book:
+
+ type word is array (0 to 31) of bit;
+
+ --
+
+ type controller_state is (initial, idle, active, error);
+
+ type state_counts is array (idle to error) of natural;
+
+ -- end of code from book
+
+ begin
+ end block block_1_a;
+
+
+ process_1_a : process is
+
+ -- code from book:
+
+ type word is array (31 downto 0) of bit;
+
+ --
+
+ type controller_state is (initial, idle, active, error);
+
+ --
+
+ type state_counts is
+ array (controller_state range idle to error) of natural;
+
+ --
+
+ subtype coeff_ram_address is integer range 0 to 63;
+ type coeff_array is array (coeff_ram_address) of real;
+
+ --
+
+ variable buffer_register, data_register : word;
+ variable counters : state_counts;
+ variable coeff : coeff_array;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ coeff(0) := 0.0;
+
+ counters(active) := counters(active) + 1;
+
+ data_register := buffer_register;
+
+ -- end of code from book
+
+ wait;
+ end process process_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd
new file mode 100644
index 000000000..cac5cfb65
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+use ieee_proposed.fluidic_systems.all;
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02a is
+begin
+
+
+ block_1_a : block is
+
+ -- code from book:
+
+ nature electrical_bus is array (0 to 31) of electrical;
+
+ -- end of code from book
+
+ begin
+ end block block_1_a;
+
+
+ block_1_b : block is
+
+ -- code from book:
+
+ nature electrical_bus is array (31 downto 0) of electrical;
+
+ -- end of code from book
+
+ begin
+ end block block_1_b;
+
+
+ block_1_c : block is
+
+ -- code from book:
+
+ type engine_nodes is (intake, compressor, combustion, exhaust);
+
+ --
+
+ nature engine_flows is array (intake to exhaust) of fluidic;
+
+ --
+
+ subtype bus_lines is integer range 0 to 31;
+ nature electrical_bus is array (bus_lines) of electrical;
+
+ --
+
+ subtype pressure is real tolerance "default_pressure";
+ subtype pipes is integer range 0 to 15;
+
+ --
+
+ type gas_pressures is array (pipes) of pressure;
+
+ --
+
+ terminal system_bus : electrical_bus;
+ terminal ferrari_engine, chevy_engine : engine_flows;
+
+ --
+
+ quantity bus_voltages across bus_currents through
+ system_bus to electrical_ref;
+
+ -- end of code from book
+
+ begin
+ end block block_1_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd
new file mode 100644
index 000000000..54145541f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+begin
+
+
+ process_1_b : process is
+
+ -- code from book:
+
+ type symbol is ('a', 't', 'd', 'h', digit, cr, error);
+ type state is range 0 to 6;
+
+ type transition_matrix is array (state, symbol) of state;
+
+ variable transition_table : transition_matrix;
+
+ -- end of code from book
+
+ variable next_state : state;
+
+ -- code from book:
+
+ type point is array (1 to 3) of real;
+ type matrix is array (1 to 3, 1 to 3) of real;
+
+ variable p, q : point;
+ variable transform : matrix;
+
+ -- end of code from book
+
+ begin
+
+ next_state :=
+ -- code from book:
+
+ transition_table(5, 'd');
+
+
+ -- end of code from book
+
+ for i in 1 to 3 loop
+ for j in 1 to 3 loop
+ if i = j then
+ transform(i, j) := -1.0;
+ else
+ transform(i, j) := 0.0;
+ end if;
+ end loop;
+ end loop;
+ p := (1.0, 2.0, 3.0);
+
+ -- code from book:
+
+ for i in 1 to 3 loop
+ q(i) := 0.0;
+ for j in 1 to 3 loop
+ q(i) := q(i) + transform(i, j) * p(j);
+ end loop;
+ end loop;
+ -- end of code from book
+
+ wait;
+ end process process_1_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd
new file mode 100644
index 000000000..6b44e1dc2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.mechanical_systems.all;
+use ieee_proposed.fluidic_systems.all;
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04a is
+
+ -- code from book:
+
+ type engine_nodes is (intake, compressor, combustion, exhaust);
+ type engines is range 1 to 4;
+ nature aircraft_engine_flows is array (engine_nodes, engines) of fluidic;
+
+ --
+
+ nature sensor_matrix is array (1 to 100, 1 to 100) of translational;
+
+ --
+
+ terminal sensor_grid : sensor_matrix;
+
+ --
+
+ quantity sensor_data across sensor_grid to translational_ref;
+
+ -- end of code from book
+
+begin
+
+
+ process_1_b : process is
+ variable total_displacement, average_displacement : real;
+ begin
+
+ -- code from book:
+
+ total_displacement := 0.0;
+ for x in 1 to 100 loop
+ for y in 1 to 100 loop
+ total_displacement := total_displacement + sensor_data(x, y);
+ end loop;
+ end loop;
+ average_displacement := total_displacement / 10000.0;
+
+ --end code from book
+
+ wait;
+ end process process_1_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd
new file mode 100644
index 000000000..c3e12392d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd
@@ -0,0 +1,125 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+ subtype coeff_ram_address is integer range 0 to 63;
+
+ -- code from book:
+
+ type coeff_array is array (coeff_ram_address) of real;
+
+ -- end of code from book
+
+
+begin
+
+
+ process_1_c : process is
+
+ -- code from book:
+
+ type point is array (1 to 3) of real;
+ constant origin : point := (0.0, 0.0, 0.0);
+ variable view_point : point := (10.0, 20.0, 0.0);
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_1_c;
+
+
+ process_1_d : process is
+
+ type point is array (1 to 3) of real;
+
+ -- code from book:
+
+ variable view_point : point := (1 => 10.0, 2 => 20.0, 3 => 0.0);
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_1_d;
+
+
+ process_1_e : process is
+
+ -- code from book:
+
+ variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, 3 to 63 => 0.0);
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_1_e;
+
+
+ process_1_f : process is
+
+ -- code from book:
+
+ variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, others => 0.0);
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_1_f;
+
+
+ process_1_g : process is
+
+ -- code from book:
+
+ variable coeff : coeff_array := (0 | 2 => 1.6, 1 => 2.3, others => 0.0);
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_1_g;
+
+
+ process_1_h : process is
+
+ -- code from book:
+
+ -- error: Associations in array aggregate must be all named or all positional
+ -- variable coeff : coeff_array := (1.6, 2.3, 2 => 1.6, others => 0.0); -- illegal
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_1_h;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd
new file mode 100644
index 000000000..317ea13a5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_06a is
+
+end entity inline_06a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06a is
+
+ -- code from book:
+
+ subtype resistance is real tolerance "default_resistance";
+ type resistance_array is array (1 to 4) of resistance;
+ quantity resistances : resistance_array := (10.0, 20.0, 50.0, 75.0);
+
+ -- end of code from book
+
+
+begin
+
+
+ block_1_f : block is
+
+ -- code from book:
+
+ quantity resistances : resistance_array := (1 => 10.0, 2 => 20.0, 3 => 50.0, 4 => 75.0);
+
+ -- end of code from book
+
+ begin
+ end block block_1_f;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd
new file mode 100644
index 000000000..1a3daf38a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_07a is
+
+end entity inline_07a;
+
+
+----------------------------------------------------------------
+
+
+library ieee_proposed; use ieee_proposed.thermal_systems.all;
+
+architecture test of inline_07a is
+
+ -- code from book:
+
+ type A is array (1 to 4, 31 downto 0) of boolean;
+
+ nature B is array (1 to 10, 19 downto 0) of thermal;
+
+ -- end of code from book
+
+begin
+
+
+ process_1_i : process is
+
+ variable free_map : bit_vector(1 to 10) := "0011010110";
+ variable count : natural;
+
+ begin
+
+ -- code from book (just the conditions):
+
+ assert A'low(1) = 1; assert B'left(1) = 1;
+ assert A'high(2) = 31; assert B'right(2) = 0;
+
+-- assert A'reverse_range(2) is 0 to 31; assert B'range(1) is 1 to 10;
+
+ assert A'length(2) = 32; assert B'length(1) = 10;
+
+ assert A'ascending(2) = false; assert B'ascending(1) = true;
+
+ assert A'low = 1; assert A'length = 4;
+ assert B'high = 10; assert B'length = 10;
+
+ --
+
+ count := 0;
+ for index in free_map'range loop
+ if free_map(index) = '1' then
+ count := count + 1;
+ end if;
+ end loop;
+
+ -- end of code from book
+
+ wait;
+ end process process_1_i;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd
new file mode 100644
index 000000000..51d617ff6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_08 is
+begin
+
+
+ process_2_a : process is
+
+ -- code from book:
+
+ type sample is array (natural range <>) of integer;
+
+ variable short_sample_buf : sample(0 to 63);
+
+ subtype long_sample is sample(0 to 255);
+ variable new_sample_buf, old_sample_buf : long_sample;
+
+ constant lookup_table : sample := ( 1 => 23, 3 => -16, 2 => 100, 4 => 11);
+
+ constant beep_sample : sample := ( 127, 63, 0, -63, -127, -63, 0, 63 );
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd
new file mode 100644
index 000000000..7b4c161cb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_09a is
+
+end entity inline_09a;
+
+
+----------------------------------------------------------------
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+architecture test of inline_09a is
+
+ -- code from book:
+
+ nature electrical_vector is array (natural range <>) of electrical;
+
+ terminal local_bus : electrical_vector(15 downto 0);
+
+ subnature long_bus is electrical_vector(7 downto 0);
+ terminal remote_bus : long_bus;
+
+ -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd
new file mode 100644
index 000000000..b5dc185c6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_10 is
+
+end entity inline_10;
+
+
+----------------------------------------------------------------
+
+
+library ieee; use ieee.std_logic_1164.std_ulogic;
+
+architecture test of inline_10 is
+
+ -- code from book:
+
+ type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+
+ --
+
+ subtype std_ulogic_word is std_ulogic_vector(0 to 31);
+
+ --
+
+ signal csr_offset : std_ulogic_vector(2 downto 1);
+
+ -- end of code from book
+
+begin
+
+
+ process_2_b : process is
+
+ -- code from book:
+
+ type string is array (positive range <>) of character;
+
+ --
+
+ constant LCD_display_len : positive := 20;
+ subtype LCD_display_string is string(1 to LCD_display_len);
+ variable LCD_display : LCD_display_string := (others => ' ');
+
+ --
+
+ type bit_vector is array (natural range <>) of bit;
+
+ --
+
+ subtype byte is bit_vector(7 downto 0);
+
+ --
+
+ variable channel_busy_register : bit_vector(1 to 4);
+
+ --
+
+ constant ready_message : string := "Ready ";
+
+ --
+
+ variable current_test : std_ulogic_vector(0 to 13) := "ZZZZZZZZZZ----";
+
+ --
+
+ constant all_ones : std_ulogic_vector(15 downto 0) := X"FFFF";
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ channel_busy_register := b"0000";
+
+ -- end of code from book
+
+ wait;
+ end process process_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd
new file mode 100644
index 000000000..1ba0a3480
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_11a is
+
+end entity inline_11a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_11a is
+
+ -- code from book:
+
+ type real_vector is array (natural range <>) of real;
+
+ --
+
+ subtype gains is real_vector(15 downto 0);
+
+ --
+
+ quantity max_temperatures : real_vector(1 to 10);
+
+ -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd
new file mode 100644
index 000000000..84c242f47
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_12 is
+
+end entity inline_12;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_12 is
+begin
+
+
+ process_3_a : process is
+
+ -- code from book:
+
+ subtype pixel_row is bit_vector (0 to 15);
+ variable current_row, mask : pixel_row;
+
+ -- end of code from book
+
+ begin
+
+ current_row := "0000000011111111";
+ mask := "0000111111110000";
+
+ -- code from book:
+
+ current_row := current_row and not mask;
+ current_row := current_row xor X"FFFF";
+
+ -- end of code from book
+
+ -- code from book (conditions only):
+
+ assert B"10001010" sll 3 = B"01010000";
+ assert B"10001010" sll -2 = B"00100010";
+
+ assert B"10010111" srl 2 = B"00100101";
+ assert B"10010111" srl -6 = B"11000000";
+
+ assert B"01001011" sra 3 = B"00001001";
+ assert B"10010111" sra 3 = B"11110010";
+ assert B"00001100" sla 2 = B"00110000";
+ assert B"00010001" sla 2 = B"01000111";
+
+ assert B"00010001" sra -2 = B"01000111";
+ assert B"00110000" sla -2 = B"00001100";
+
+ assert B"10010011" rol 1 = B"00100111";
+ assert B"10010011" ror 1 = B"11001001";
+
+ assert "abc" & 'd' = "abcd";
+ assert 'w' & "xyz" = "wxyz";
+ assert 'a' & 'b' = "ab";
+
+ -- end of code from book
+
+ wait;
+ end process process_3_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd
new file mode 100644
index 000000000..9eef5af3f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_13 is
+
+end entity inline_13;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_13 is
+begin
+
+
+ process_3_b : process is
+
+ -- code from book:
+
+ type array1 is array (1 to 100) of integer;
+ type array2 is array (100 downto 1) of integer;
+
+ variable a1 : array1;
+ variable a2 : array2;
+
+ -- end of code from book
+
+ begin
+
+ a1(11 to 20) := a1(11 to 20);
+ a2(50 downto 41) := a2(50 downto 41);
+
+ a1(10 to 1) := a1(10 to 1);
+ a2(1 downto 10) := a2(1 downto 10);
+
+ a1(10 downto 1) := a1(10 downto 1); -- illegal
+ a2(1 to 10) := a2(1 to 10); -- illegal;
+
+ wait;
+ end process process_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd
new file mode 100644
index 000000000..ab0fa8b94
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_14a is
+
+end entity inline_14a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_14a is
+
+ -- code from book:
+
+ type array3 is array (10 downto 1) of real tolerance "default";
+
+ quantity a3 : array3;
+
+ -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd
new file mode 100644
index 000000000..cd58766ca
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_15 is
+
+end entity inline_15;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_15 is
+begin
+
+
+ process_3_c : process is
+
+ -- code from book:
+
+ subtype name is string(1 to 20);
+ type display_string is array (integer range 0 to 19) of character;
+
+ variable item_name : name;
+ variable display : display_string;
+
+ --
+
+ subtype big_endian_upper_halfword is bit_vector(0 to 15);
+ subtype little_endian_upper_halfword is bit_vector(31 downto 16);
+
+ variable big : big_endian_upper_halfword;
+ variable little : little_endian_upper_halfword;
+
+ -- end of code from book
+
+ begin
+
+ -- error: Incompatible types for assignment
+ -- display := item_name; -- ilegal
+
+ item_name := (others => 'A');
+
+ little := x"AAAA";
+
+ -- code from book:
+
+ display := display_string(item_name);
+
+ --
+
+ big := little;
+ little := big;
+
+ -- end of code from book
+
+ wait;
+ end process process_3_c;
+
+
+ ----------------
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd
new file mode 100644
index 000000000..3ffbd2c4b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_16 is
+
+end entity inline_16;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_16 is
+
+ -- code from book:
+
+ type time_stamp is record
+ seconds : integer range 0 to 59;
+ minutes : integer range 0 to 59;
+ hours : integer range 0 to 23;
+ end record time_stamp;
+
+ -- end of code from book
+
+begin
+
+
+ process_4_a : process is
+
+ -- code from book:
+
+ variable sample_time, current_time : time_stamp;
+
+ --
+
+ constant midday : time_stamp := (0, 0, 12);
+
+ -- end of code from book
+
+ constant clock : integer := 79;
+ variable sample_hour : integer;
+
+ begin
+
+ current_time := (30, 15, 2);
+
+ -- code from book:
+
+ sample_time := current_time;
+
+ sample_hour := sample_time.hours;
+
+ current_time.seconds := clock mod 60;
+
+ -- end of code from book
+
+ wait;
+ end process process_4_a;
+
+
+ process_4_b : process is
+
+ type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop);
+ type reg_number is range 0 to 31;
+
+ type instruction is record
+ opcode : opcodes;
+ source_reg1, source_reg2, dest_reg : reg_number;
+ displacement : integer;
+ end record instruction;
+
+ -- code from book:
+
+ constant midday : time_stamp := (hours => 12, minutes => 0, seconds => 0);
+
+ --
+
+ constant nop_instr : instruction :=
+ ( opcode => addu,
+ source_reg1 | source_reg2 | dest_reg => 0,
+ displacement => 0 );
+
+ variable latest_event : time_stamp := (others => 0); -- initially midnight
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_4_b;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd
new file mode 100644
index 000000000..a3f4a69e3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_17a is
+
+end entity inline_17a;
+
+
+----------------------------------------------------------------
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+architecture test of inline_17a is
+
+ -- code from book:
+
+ nature electrical_bus is record
+ strobe : electrical;
+ bus_lines : electrical_vector(0 to 15);
+ end record electrical_bus;
+
+ terminal address_bus, data_bus : electrical_bus;
+
+ quantity data_voltages across data_currents through data_bus;
+
+ -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd
new file mode 100644
index 000000000..3a4af645c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity modem_controller is
+
+end entity modem_controller;
+
+
+----------------------------------------------------------------
+
+
+architecture test of modem_controller is
+begin
+
+ -- code from book:
+
+ modem_controller : process is
+
+ type symbol is ('a', 't', 'd', 'h', digit, cr, other);
+ type symbol_string is array (1 to 20) of symbol;
+ type state is range 0 to 6;
+ type transition_matrix is array (state, symbol) of state;
+
+ constant next_state : transition_matrix :=
+ ( 0 => ('a' => 1, others => 6),
+ 1 => ('t' => 2, others => 6),
+ 2 => ('d' => 3, 'h' => 5, others => 6),
+ 3 => (digit => 4, others => 6),
+ 4 => (digit => 4, cr => 0, others => 6),
+ 5 => (cr => 0, others => 6),
+ 6 => (cr => 0, others => 6) );
+
+ variable command : symbol_string;
+ variable current_state : state := 0;
+
+ -- not in book:
+ type sample_array is array (positive range <>) of symbol_string;
+ constant sample_command : sample_array :=
+ ( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ),
+ 2 => ( 'a', 't', 'h', cr, others => other ),
+ 3 => ( 'a', 't', other, other, cr, others => other ) );
+ -- end not in book
+
+ begin
+ -- . . .
+ -- not in book:
+ for command_index in sample_command'range loop
+ command := sample_command(command_index);
+ -- end not in book
+ for index in 1 to 20 loop
+ current_state := next_state( current_state, command(index) );
+ case current_state is
+ -- . . .
+ -- not in book:
+ when 0 => exit;
+ when others => null;
+ -- end not in book
+ end case;
+ end loop;
+ -- . . .
+ -- not in book:
+ end loop;
+ wait;
+ -- end not in book
+ end process modem_controller;
+
+ -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd
new file mode 100644
index 000000000..6723631b2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_and_multiple is
+
+end entity tb_and_multiple;
+
+
+----------------------------------------------------------------
+
+
+architecture test_behavioral of tb_and_multiple is
+
+ -- code from book:
+
+ signal count_value : bit_vector(7 downto 0);
+ signal terminal_count : bit;
+
+ -- end of code from book
+
+begin
+
+ -- code from book:
+
+ tc_gate : entity work.and_multiple(behavioral)
+ port map ( i => count_value, y => terminal_count);
+
+ -- end of code from book
+
+ stumulus : process is
+ begin
+ wait for 10 ns;
+ count_value <= "10000000"; wait for 10 ns;
+ count_value <= "11111110"; wait for 10 ns;
+ count_value <= "01111111"; wait for 10 ns;
+ count_value <= "11111111"; wait for 10 ns;
+ count_value <= "00000000"; wait for 10 ns;
+
+ wait;
+ end process stumulus;
+
+end architecture test_behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd
new file mode 100644
index 000000000..865378a46
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_byte_swap is
+
+end entity tb_byte_swap;
+
+
+----------------------------------------------------------------
+
+
+use work.byte_swap_types.all;
+
+
+architecture test_behavior of tb_byte_swap is
+
+ signal input, output : halfword := x"0000";
+
+begin
+
+ dut : entity work.byte_swap(behavior)
+ port map ( input => input, output => output );
+
+ stumulus : process is
+ begin
+ wait for 10 ns;
+ input <= x"ff00"; wait for 10 ns;
+ input <= x"00ff"; wait for 10 ns;
+ input <= x"aa33"; wait for 10 ns;
+
+ wait;
+ end process stumulus;
+
+end architecture test_behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd
new file mode 100644
index 000000000..0b7fd1fa8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_coeff_ram is
+
+end entity tb_coeff_ram;
+
+
+----------------------------------------------------------------
+
+
+architecture test_abstract of tb_coeff_ram is
+
+ use work.coeff_ram_types.all;
+
+ signal rd, wr : bit := '0';
+ signal addr : coeff_ram_address := 0;
+ signal d_in, d_out : real := 0.0;
+
+begin
+
+ dut : entity work.coeff_ram(abstract)
+ port map ( rd => rd, wr => wr,
+ addr => addr,
+ d_in => d_in, d_out => d_out );
+
+ stumulus : process is
+
+ begin
+ wait for 100 ns;
+
+ addr <= 10; d_in <= 10.0; wait for 10 ns;
+ wr <= '1'; wait for 10 ns;
+ d_in <= 20.0; wait for 10 ns;
+ wr <= '0'; wait for 70 ns;
+
+ addr <= 20; wait for 10 ns;
+ rd <= '1'; wait for 10 ns;
+ addr <= 10; wait for 10 ns;
+ rd <= '0'; wait for 10 ns;
+
+ wait;
+ end process stumulus;
+
+end architecture test_abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd
new file mode 100644
index 000000000..200e58774
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+package transmission_lines_types is
+
+ type word is array (0 to 31) of bit;
+
+ subtype bus_lines is integer range 0 to 31;
+ nature electrical_bus is array (bus_lines) of electrical;
+
+end package transmission_lines_types;
+
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+use work.transmission_lines_types.all;
+
+-- end not in book
+
+entity transmission_lines is
+ port ( terminal data_bus : electrical_bus;
+ signal clk : in bit; signal data_out : out word );
+end entity transmission_lines;
+
+----------------------------------------------------------------
+
+architecture abstract of transmission_lines is
+ constant threshold : voltage := 1.5;
+ quantity bus_voltages across bus_currents through
+ data_bus to electrical_ref;
+begin
+
+ logic_value_maps : process (clk) is
+ begin
+ if clk = '1' then
+ for index in bus_lines loop
+ if bus_voltages(index) > threshold then
+ data_out(index) <= '1';
+ else
+ data_out(index) <= '0';
+ end if;
+ end loop;
+ end if;
+ end process logic_value_maps;
+
+ -- additional VHDL-AMS code to describe reflections and attenuation
+ -- ...
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd
new file mode 100644
index 000000000..f52bcb8da
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+ port ( terminal node1, node2 : electrical );
+end entity resistor;
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity capacitor is
+ port ( terminal node1, node2 : electrical );
+end entity capacitor;
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity LF353_opamp is
+ port ( terminal plus, minus, output, pos_supply, neg_supply : electrical );
+end entity LF353_opamp;
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity active_filter is
+end entity active_filter;
+
+-- end not in book
+
+
+
+library widget_parts, wasp_lib;
+
+architecture component_based of active_filter is
+
+ -- declaration of signals, terminals, quantities, etc
+ -- ...
+
+ -- not in book
+
+ terminal input, node2, node3, node4, node7, node15, Vdd, Vss : electrical;
+
+ -- end not in book
+
+begin
+
+ R1 : entity wasp_lib.resistor
+ port map ( node1 => input, node2 => node2 );
+
+ C1 : entity widget_parts.capacitor
+ port map ( node1 => node3, node2 => ground );
+
+ Amp1 : entity work.LF353_opamp
+ port map ( plus => node4, minus => node7, output => node15,
+ pos_supply => Vdd, neg_supply => Vss );
+
+ -- other component instantiations
+ -- ...
+
+end architecture component_based;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd
new file mode 100644
index 000000000..9532e9c6d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity dff is
+ port ( signal d, clk : in std_ulogic; q : out std_ulogic );
+end entity dff;
+
+----------------------------------------------------------------
+
+architecture behav of dff is
+begin
+
+ storage : process ( clk ) is
+ begin
+ if clk'event and (clk = '1' or clk = 'H') then
+ q <= d after 5 ns;
+ end if;
+ end process storage;
+
+end architecture behav;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/index-ams.txt
new file mode 100644
index 000000000..a01c3762b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/index-ams.txt
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 7 - Design Processing
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+inverting_integrator.vhd entity inverting_integrator structural Figure 7-3
+dff.vhd entity dff behav Figure 7-4
+volume_sensor.vhd entity volume_sensor structural Figure 7-5
+active_filter.vhd entity resistor -- --
+-- entity capacitor -- --
+-- entity LF353_opamp -- --
+-- entity active_filter component_based Figure 7-7
+inline_01a.vhd entity inline_01a test Section 7.1
+inline_02a.vhd entity inline_02a test Section 7.1
+inline_03a.vhd entity bottom bottom_arch Section 7.2
+-- entity other_ent other_arch --
+-- entity inline_03a test Section 7.2
+inline_04a.vhd entity battery wrong, correct Section 7.2
+-- entity inline_04a test Section 7.2
+inline_05a.vhd entity inline_05a test Section 7.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_volume_sensor.vhd entity tb_volume_sensor test_bench volume_sensor.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd
new file mode 100644
index 000000000..09ff94759
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_01a is
+
+end entity inline_01a;
+
+
+----------------------------------------------------------------
+
+
+-- code from book:
+
+library widget_parts, wasp_lib;
+
+use widget_parts.capacitor;
+
+-- end of code from book
+
+
+architecture test of inline_01a is
+
+ terminal node3 : electrical;
+
+begin
+
+ -- code from book:
+
+ C1 : entity capacitor
+ port map ( node1 => node3, node2 => ground );
+
+ -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd
new file mode 100644
index 000000000..f1b8e8a6e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+----------------------------------------------------------------
+
+
+library wasp_lib;
+
+-- code from book:
+
+use wasp_lib.all;
+
+-- end of code from book
+
+
+architecture test of inline_02a is
+begin
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd
new file mode 100644
index 000000000..3b2ac9f9c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd
@@ -0,0 +1,121 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+-- code from book
+
+entity bottom is
+ port ( terminal Tb : electrical; -- ... );
+ -- not in book
+ terminal Tz : electrical );
+ -- end not in book
+end entity bottom;
+
+-- end code from book
+
+
+architecture bottom_arch of bottom is
+
+ -- code from book
+
+ quantity -- ...
+ i_b1 through Tb to Tz; -- ...;
+ quantity -- ...
+ i_b2 through Tb to Tz; -- ...;
+ quantity -- ...
+ i_b3 through Tz to Tb; -- ... to Tb;
+ quantity -- ...
+ i_b4 through Tz to Tb; -- ... to Tb;
+
+ -- end code from book
+
+begin
+
+ assert
+ -- code from book
+ Tb'contribution = ( i_b1 + i_b2 ) - ( i_b3 + i_b4 )
+ -- end code from book
+ ;
+
+end architecture bottom_arch;
+
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity other_ent is
+ port ( terminal Tx, Tz : electrical );
+end entity other_ent;
+
+
+architecture other_arch of other_ent is
+begin
+end architecture other_arch;
+
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_03a is
+
+end entity inline_03a;
+
+
+architecture test of inline_03a is
+
+ terminal Ty, Tb, Tx : electrical;
+
+ -- code from book
+
+ terminal T : electrical;
+ quantity -- ...
+ i_t1, i_t2 through T to Ty; -- ...;
+ quantity -- ...
+ i_t3 through Ty to T; -- ... to T;
+ -- ...
+
+ -- end code from book
+
+begin
+
+ -- code from book
+
+ comp1 : entity work.bottom(bottom_arch)
+ port map ( Tb => T, -- ... );
+ -- not in book
+ Tz => Ty );
+ -- end not in book
+
+ comp2 : entity work.other_ent(other_arch)
+ port map ( Tx => T, -- ... );
+ -- not in book
+ Tz => Ty );
+ -- end not in book
+
+ -- end code from book
+
+
+ assert
+ -- code from book
+ T'contribution = ( i_t1 + i_t2 ) - ( i_t3 ) + ( Tb'contribution + Tx'contribution )
+ -- end code from book
+ ;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd
new file mode 100644
index 000000000..a3e8cf0f8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+-- code from book
+
+entity battery is
+ port ( terminal plus, minus : electrical );
+end entity battery;
+
+architecture wrong of battery is
+ constant v_nominal : real := 9.0;
+ quantity v across plus to minus;
+begin
+ v == v_nominal;
+end architecture wrong;
+
+--
+
+architecture correct of battery is
+ constant v_nominal : real := 9.0;
+ quantity v across i through plus to minus;
+begin
+ v == v_nominal;
+end architecture correct;
+
+-- end code from book
+
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+architecture test of inline_04a is
+
+ signal clamp : bit;
+ quantity v1, v2 : real;
+
+begin
+
+ -- code from book
+
+ if clamp = '1' use
+ v1 == 5.0;
+ v2 == 0.0;
+ else
+ v1 == v2;
+ end use;
+
+ -- end code from book
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd
new file mode 100644
index 000000000..7cfd1fc51
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_05a is
+
+end entity inline_05a;
+
+
+architecture test of inline_05a is
+
+ -- code from book
+
+ type domain_type is (quiescent_domain, time_domain, frequency_domain);
+
+ signal domain : domain_type := quiescent_domain;
+
+ -- end code from book
+
+begin
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd
new file mode 100644
index 000000000..82e86c05c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inverting_integrator is
+ port ( terminal input, output : electrical;
+ signal rst : in std_ulogic );
+end entity inverting_integrator;
+
+----------------------------------------------------------------
+
+architecture structural of inverting_integrator is
+ terminal internal : electrical;
+begin
+
+ r1 : entity work.resistor(ideal)
+ port map ( node1 => input, node2 => internal);
+
+ c1 : entity work.capacitor(leakage)
+ port map ( node1 => internal, node2 => output );
+
+ amp : entity work.opamp(slew_limited)
+ port map ( plus_in => electrical_ref, minus_in => internal,
+ output => output);
+
+ switch : entity work.analog_switch(ideal)
+ port map ( n1 => internal, n2 => output, control => rst );
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd
new file mode 100644
index 000000000..82307fa35
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- created by: Veribest WaveBench Version 16.00.00.02
+library work; use work.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+library ieee; use ieee.std_logic_1164.all;
+
+entity tb_volume_sensor is
+end tb_volume_sensor;
+
+architecture test_bench of tb_volume_sensor is
+ -- Component declarations
+ -- Signal declarations
+ signal clk, full, rst : std_logic;
+ terminal flow, minus_ref : electrical;
+
+begin
+ -- Signal assignments
+ -- Component instances
+
+ vol1 : entity work.volume_sensor(structural)
+ port map(
+ clk => clk,
+ full => full,
+ rst => rst,
+ flow => flow,
+ minus_ref => minus_ref
+ );
+ vio : entity work.v_sine(ideal)
+ generic map(
+ freq => 1.0,
+ amplitude => 16.0
+ )
+ port map(
+ pos => flow,
+ neg => ELECTRICAL_REF
+ );
+ vm_ref : entity work.v_constant(ideal)
+ generic map(
+ level => -10.0
+ )
+ port map(
+ pos => minus_ref,
+ neg => ELECTRICAL_REF
+ );
+-- Test code generation processes
+ -- clk
+ P_clk :
+ process
+ begin
+ clk <= '1';
+ wait for 500000.000 ns;
+ clk <= '0';
+ wait for 500000.000 ns;
+ end process P_clk;
+
+ -- rst
+ P_rst :
+ process
+ begin
+ wait for 0.0 ms; rst <= '0';
+ wait for 2.0 ms; rst <= '1';
+ wait for 2.0 ms; rst <= '0';
+ wait;
+ end process;
+
+ end test_bench;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd
new file mode 100644
index 000000000..6791450ef
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity volume_sensor is
+ port ( terminal flow, minus_ref : electrical;
+ signal clk, rst : in std_ulogic;
+ signal full : out std_ulogic );
+end entity volume_sensor;
+
+----------------------------------------------------------------
+
+architecture structural of volume_sensor is
+
+ terminal minus_volume : electrical;
+ signal async_full, sync1_full : std_ulogic;
+
+begin
+
+ int : entity work.inverting_integrator(structural)
+ port map ( input => flow, output => minus_volume, rst => rst );
+
+ comp : entity work.comparator(hysteresis)
+ port map ( plus_in => minus_volume, minus_in => minus_ref,
+ output => async_full );
+
+ sync1 : entity work.dff(behav)
+ port map ( d => async_full, clk => clk, q => sync1_full );
+
+ sync2 : entity work.dff(behav)
+ port map ( d => sync1_full, clk => clk, q => full );
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd
new file mode 100644
index 000000000..9702b9751
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd
@@ -0,0 +1,28 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity S_R_flipflop is
+ port ( s, r : in bit; q, q_n : out bit );
+
+begin
+
+ check : assert not (s = '1' and r = '1')
+ report "Incorrect use of S_R_flip_flop: s and r both '1'";
+
+end entity S_R_flipflop;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd
new file mode 100644
index 000000000..a726b736d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity S_R_flipflop is
+ port ( s, r : in bit; q, q_n : out bit );
+end entity S_R_flipflop;
+
+--------------------------------------------------
+
+architecture functional of S_R_flipflop is
+
+begin
+
+ q <= '1' when s = '1' else
+ '0' when r = '1';
+
+ q_n <= '0' when s = '1' else
+ '1' when r = '1';
+
+ check : assert not (s = '1' and r = '1')
+ report "Incorrect use of S_R_flip_flop: s and r both '1'";
+
+end architecture functional;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd
new file mode 100644
index 000000000..4d9e5cac6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd
@@ -0,0 +1,138 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity alu is
+end entity alu;
+
+
+architecture test of alu is
+
+ constant Tpd : delay_length := 2 ns;
+
+ function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+ alias op1 : bit_vector(1 to bv1'length) is bv1;
+ alias op2 : bit_vector(1 to bv2'length) is bv2;
+ variable result : bit_vector(1 to bv1'length);
+ variable carry_in : bit;
+ variable carry_out : bit := '0';
+
+ begin
+ for index in result'reverse_range loop
+ carry_in := carry_out; -- of previous bit
+ result(index) := op1(index) xor op2(index) xor carry_in;
+ carry_out := (op1(index) and op2(index))
+ or (carry_in and (op1(index) xor op2(index)));
+ end loop;
+ return result;
+ end function "+";
+
+ function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+ -- subtraction implemented by adding ((not bv2) + 1), ie -bv2
+
+ alias op1 : bit_vector(1 to bv1'length) is bv1;
+ alias op2 : bit_vector(1 to bv2'length) is bv2;
+ variable result : bit_vector(1 to bv1'length);
+ variable carry_in : bit;
+ variable carry_out : bit := '1';
+
+ begin
+ for index in result'reverse_range loop
+ carry_in := carry_out; -- of previous bit
+ result(index) := op1(index) xor (not op2(index)) xor carry_in;
+ carry_out := (op1(index) and (not op2(index)))
+ or (carry_in and (op1(index) xor (not op2(index))));
+ end loop;
+ return result;
+ end function "-";
+
+ type alu_function_type is (alu_pass_a, alu_add, alu_sub,
+ alu_add_unsigned, alu_sub_unsigned,
+ alu_and, alu_or);
+
+ signal alu_function : alu_function_type := alu_pass_a;
+ signal a, b : bit_vector(15 downto 0);
+ signal functional_result, equivalent_result : bit_vector(15 downto 0);
+
+begin
+
+ functional_alu : block is
+ port ( result : out bit_vector(15 downto 0) );
+ port map ( result => functional_result );
+ begin
+
+ -- code from book
+
+ alu : with alu_function select
+ result <= a + b after Tpd when alu_add | alu_add_unsigned,
+ a - b after Tpd when alu_sub | alu_sub_unsigned,
+ a and b after Tpd when alu_and,
+ a or b after Tpd when alu_or,
+ a after Tpd when alu_pass_a;
+
+ -- end code from book
+
+ end block functional_alu;
+
+ --------------------------------------------------
+
+ equivalent_alu : block is
+ port ( result : out bit_vector(15 downto 0) );
+ port map ( result => equivalent_result );
+ begin
+
+ -- code from book
+
+ alu : process is
+ begin
+ case alu_function is
+ when alu_add | alu_add_unsigned => result <= a + b after Tpd;
+ when alu_sub | alu_sub_unsigned => result <= a - b after Tpd;
+ when alu_and => result <= a and b after Tpd;
+ when alu_or => result <= a or b after Tpd;
+ when alu_pass_a => result <= a after Tpd;
+ end case;
+ wait on alu_function, a, b;
+ end process alu;
+
+ -- end code from book
+
+ end block equivalent_alu;
+
+ --------------------------------------------------
+
+ stimulus : process is
+ begin
+ alu_function <= alu_add; wait for 10 ns;
+ a <= X"000A"; wait for 10 ns;
+ b <= X"0003"; wait for 10 ns;
+ alu_function <= alu_sub; wait for 10 ns;
+ alu_function <= alu_and; wait for 10 ns;
+ alu_function <= alu_or; wait for 10 ns;
+ alu_function <= alu_pass_a; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+ verifier :
+ assert functional_result = equivalent_result
+ report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd
new file mode 100644
index 000000000..479c3af75
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity and2 is
+ port ( a, b : in std_ulogic; y : out std_ulogic );
+end entity and2;
+
+--------------------------------------------------
+
+architecture detailed_delay of and2 is
+
+ signal result : std_ulogic;
+
+begin
+
+ gate : process (a, b) is
+ begin
+ result <= a and b;
+ end process gate;
+
+ delay : process (result) is
+ begin
+ if result = '1' then
+ y <= reject 400 ps inertial '1' after 1.5 ns;
+ elsif result = '0' then
+ y <= reject 300 ps inertial '0' after 1.2 ns;
+ else
+ y <= reject 300 ps inertial 'X' after 500 ps;
+ end if;
+ end process delay;
+
+end architecture detailed_delay;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd
new file mode 100644
index 000000000..15c325da8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity and_or_inv is
+ port ( a1, a2, b1, b2 : in bit := '1';
+ y : out bit );
+end entity and_or_inv;
+
+-- end not in book
+
+
+architecture primitive of and_or_inv is
+
+ signal and_a, and_b : bit;
+ signal or_a_b : bit;
+
+begin
+
+ and_gate_a : process (a1, a2) is
+ begin
+ and_a <= a1 and a2;
+ end process and_gate_a;
+
+ and_gate_b : process (b1, b2) is
+ begin
+ and_b <= b1 and b2;
+ end process and_gate_b;
+
+ or_gate : process (and_a, and_b) is
+ begin
+ or_a_b <= and_a or and_b;
+ end process or_gate;
+
+ inv : process (or_a_b) is
+ begin
+ y <= not or_a_b;
+ end process inv;
+
+end architecture primitive;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd
new file mode 100644
index 000000000..122e95c5f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity asym_delay is
+end entity asym_delay;
+
+
+
+architecture test of asym_delay is
+
+ signal a, z : bit;
+
+begin
+
+ -- code from book
+
+ asym_delay : process (a) is
+ constant Tpd_01 : time := 800 ps;
+ constant Tpd_10 : time := 500 ps;
+ begin
+ if a = '1' then
+ z <= transport a after Tpd_01;
+ else -- a = '0'
+ z <= transport a after Tpd_10;
+ end if;
+ end process asym_delay;
+
+ -- end code from book
+
+
+ stimulus : process is
+ begin
+ a <= '1' after 2000 ps,
+ '0' after 4000 ps,
+ '1' after 6000 ps,
+ '0' after 6200 ps;
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd
new file mode 100644
index 000000000..e1ff36b7b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity clock_gen is
+end entity clock_gen;
+
+architecture test of clock_gen is
+
+ constant T_pw : time := 10 ns;
+
+ signal clk : bit;
+
+begin
+
+ -- code from book
+
+ clock_gen : process is
+ begin
+ clk <= '1' after T_pw, '0' after 2*T_pw;
+ wait until clk = '0';
+ end process clock_gen;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd
new file mode 100644
index 000000000..af7a7d4ad
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity clock_gen is
+end entity clock_gen;
+
+architecture test of clock_gen is
+
+ constant T_pw : time := 10 ns;
+
+ signal clk : bit;
+
+begin
+
+ -- code from book
+
+ clock_gen : process is
+ begin
+ clk <= '1' after T_pw, '0' after 2*T_pw;
+ wait for 2*T_pw;
+ end process clock_gen;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd
new file mode 100644
index 000000000..10b54b4fe
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity clock_gen is
+end entity clock_gen;
+
+architecture test of clock_gen is
+
+ constant T_pw : time := 10 ns;
+
+ signal clk : bit;
+
+begin
+
+ -- code from book
+
+ clock_gen : process (clk) is
+ begin
+ if clk = '0' then
+ clk <= '1' after T_pw, '0' after 2*T_pw;
+ end if;
+ end process clock_gen;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd
new file mode 100644
index 000000000..15753d1bb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+architecture abstract of computer_system is
+
+ subtype word is bit_vector(31 downto 0);
+
+ signal address : natural;
+ signal read_data, write_data : word;
+ signal mem_read, mem_write : bit := '0';
+ signal mem_ready : bit := '0';
+
+begin
+
+ cpu : process is
+ variable instr_reg : word;
+ variable PC : natural;
+ -- . . . -- other declarations
+ begin
+ loop
+ address <= PC;
+ mem_read <= '1';
+ wait until mem_ready = '1';
+ instr_reg := read_data;
+ mem_read <= '0';
+ wait until mem_ready = '0';
+ PC := PC + 4;
+ -- . . . -- execute the instruction
+ end loop;
+ end process cpu;
+
+ memory : process is
+ type memory_array is array (0 to 2**14 - 1) of word;
+ variable store : memory_array := (
+ -- . . .
+ -- not in book
+ 0 => X"0000_0000",
+ 1 => X"0000_0004",
+ 2 => X"0000_0008",
+ 3 => X"0000_000C",
+ 4 => X"0000_0010",
+ 5 => X"0000_0014",
+ others => X"0000_0000"
+ -- end not in book
+ );
+ begin
+ wait until mem_read = '1' or mem_write = '1';
+ if mem_read = '1' then
+ read_data <= store( address / 4 );
+ mem_ready <= '1';
+ wait until mem_read = '0';
+ mem_ready <= '0';
+ else
+ -- . . . -- perform write access
+ end if;
+ end process memory;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd
new file mode 100644
index 000000000..faf5f1414
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd
@@ -0,0 +1,137 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+package counter_types is
+
+ -- code in book (in text)
+
+ subtype digit is bit_vector(3 downto 0);
+
+ -- end code in book (in text)
+
+end package counter_types;
+
+
+entity add_1 is
+ port ( d0, d1, d2, d3 : in bit;
+ y0, y1, y2, y3 : out bit );
+end entity add_1;
+
+
+architecture boolean_eqn of add_1 is
+begin
+
+ y0 <= not d0 after 4 ns;
+
+ y1 <= (not d1 and d0)
+ or (d1 and not d0) after 4 ns;
+
+ y2 <= (not d2 and d1 and d0)
+ or (d2 and not (d1 and d0)) after 4 ns;
+
+ y3 <= (not d3 and d2 and d1 and d0)
+ or (d3 and not (d2 and d1 and d0)) after 4 ns;
+
+end architecture boolean_eqn;
+
+
+entity buf4 is
+ port ( a0, a1, a2, a3 : in bit;
+ y0, y1, y2, y3 : out bit );
+end entity buf4;
+
+
+architecture basic of buf4 is
+begin
+
+ y0 <= a0 after 2 ns;
+ y1 <= a1 after 2 ns;
+ y2 <= a2 after 2 ns;
+ y3 <= a3 after 2 ns;
+
+end architecture basic;
+
+
+use work.counter_types.all;
+
+-- end not in book
+
+
+entity counter is
+ port ( clk, clr : in bit;
+ q0, q1 : out digit );
+end entity counter;
+
+--------------------------------------------------
+
+architecture registered of counter is
+
+ signal current_val0, current_val1, next_val0, next_val1 : digit;
+
+begin
+
+ val0_reg : entity work.reg4(struct)
+ port map ( d0 => next_val0(0), d1 => next_val0(1),
+ d2 => next_val0(2), d3 => next_val0(3),
+ q0 => current_val0(0), q1 => current_val0(1),
+ q2 => current_val0(2), q3 => current_val0(3),
+ clk => clk, clr => clr );
+
+ val1_reg : entity work.reg4(struct)
+ port map ( d0 => next_val1(0), d1 => next_val1(1),
+ d2 => next_val1(2), d3 => next_val1(3),
+ q0 => current_val1(0), q1 => current_val1(1),
+ q2 => current_val1(2), q3 => current_val1(3),
+ clk => clk, clr => clr );
+
+ incr0 : entity work.add_1(boolean_eqn) -- . . .;
+ -- not in book
+ port map ( d0 => current_val0(0), d1 => current_val0(1),
+ d2 => current_val0(2), d3 => current_val0(3),
+ y0 => next_val0(0), y1 => next_val0(1),
+ y2 => next_val0(2), y3 => next_val0(3) );
+ -- end not in book
+
+ incr1 : entity work.add_1(boolean_eqn) -- . . .;
+ -- not in book
+ port map ( d0 => current_val1(0), d1 => current_val1(1),
+ d2 => current_val1(2), d3 => current_val1(3),
+ y0 => next_val1(0), y1 => next_val1(1),
+ y2 => next_val1(2), y3 => next_val1(3) );
+ -- end not in book
+
+ buf0 : entity work.buf4(basic) -- . . .;
+ -- not in book
+ port map ( a0 => current_val0(0), a1 => current_val0(1),
+ a2 => current_val0(2), a3 => current_val0(3),
+ y0 => q0(0), y1 => q0(1),
+ y2 => q0(2), y3 => q0(3) );
+ -- end not in book
+
+ buf1 : entity work.buf4(basic) -- . . .;
+ -- not in book
+ port map ( a0 => current_val1(0), a1 => current_val1(1),
+ a2 => current_val1(2), a3 => current_val1(3),
+ y0 => q1(0), y1 => q1(1),
+ y2 => q1(2), y3 => q1(3) );
+ -- end not in book
+
+end architecture registered;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd
new file mode 100644
index 000000000..d061a397c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity edge_triggered_Dff is
+ port ( D : in bit; clk : in bit; clr : in bit;
+ Q : out bit );
+end entity edge_triggered_Dff;
+
+--------------------------------------------------
+
+architecture behavioral of edge_triggered_Dff is
+begin
+
+ state_change : process (clk, clr) is
+ begin
+ if clr = '1' then
+ Q <= '0' after 2 ns;
+ elsif clk'event and clk = '1' then
+ Q <= D after 2 ns;
+ end if;
+ end process state_change;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd
new file mode 100644
index 000000000..9b17dc184
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity full_adder is
+ port ( a, b, c_in : bit; s, c_out : out bit );
+end entity full_adder;
+
+
+architecture truth_table of full_adder is
+begin
+
+ with bit_vector'(a, b, c_in) select
+ (c_out, s) <= bit_vector'("00") when "000",
+ bit_vector'("01") when "001",
+ bit_vector'("01") when "010",
+ bit_vector'("10") when "011",
+ bit_vector'("01") when "100",
+ bit_vector'("10") when "101",
+ bit_vector'("10") when "110",
+ bit_vector'("11") when "111";
+
+end architecture truth_table;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/index-ams.txt
new file mode 100644
index 000000000..aa17bf41c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/index-ams.txt
@@ -0,0 +1,82 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 5 - Digital Modeling Constructs
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+program_rom.vhd entity program_rom -- Figure 5-1
+and_or_inv.vhd entity and_or_inv primitive Figure 5-2
+clock_gen.vhd entity clock_gen test Figure 5-3
+mux.vhd entity mux test Figure 5-4
+edge_triggered_Dff.vhd entity edge_triggered_Dff behavioral Figure 5-5
+mux2.vhd entity mux2 behavioral Figure 5-6
+clock_gen-1.vhd entity clock_gen test Figure 5-7
+clock_gen-2.vhd entity clock_gen test Figure 5-8
+computer_system.vhd entity computer_system abstract Figure 5-9
+asym_delay.vhd entity asym_delay test Figure 5-12
+and2.vhd entity and2 detailed_delay Figure 5-16
+zmux.vhd entity zmux test Figure 5-17
+zmux-1.vhd entity zmux test Figure 5-18
+scheduler.vhd entity scheduler test Figure 5-19
+alu.vhd entity alu test Figure 5-20
+full_adder.vhd entity full_adder truth_table Figure 5-21
+S_R_flipflop.vhd entity S_R_flipflop functional Figure 5-22
+S_R_flipflop-1.vhd entity S_R_flipflop -- Figure 5-23
+rom.vhd entity rom -- Figure 5-24
+reg4.vhd entity reg4 struct Figure 5-25
+counter.vhd package counter_types -- Section 5.4
+-- entity add_1 boolean_eqn --
+-- entity buf4 basic --
+-- counter registered Figure 5-27
+microprocessor.vhd reg -- Figure 5-28
+-- microprocessor RTL Figure 5-28
+inline_01.vhd package adder_types -- --
+-- entity adder -- Section 5.1
+inline_02.vhd package adder_types -- --
+-- entity adder -- Section 5.1
+inline_03.vhd entity and_or_inv -- Section 5.1
+inline_04.vhd entity top_level -- Section 5.1
+inline_05.vhd -- abstract Section 5.2
+inline_06.vhd entity inline_06 test Section 5.3
+inline_07.vhd entity inline_07 test Section 5.3
+inline_08.vhd entity inline_08 test Section 5.3
+inline_09.vhd entity inline_09 test Section 5.3
+inline_10.vhd entity inline_10 test Section 5.3
+inline_11.vhd entity inline_11 test Section 5.3
+inline_12.vhd entity inline_12 test Section 5.3
+inline_13.vhd entity inline_13 test Section 5.3
+inline_14.vhd entity inline_14 test Section 5.3
+inline_15.vhd entity inline_15 test Section 5.3
+inline_16.vhd entity inline_16 test Section 5.3
+inline_17.vhd entity inline_17 test Section 5.3
+inline_18.vhd entity DRAM_controller fpld Section 5.4
+-- entity inline_18 test Section 5.4
+inline_19.vhd package inline_19 -- Section 5.4
+inline_20.vhd package inline_20_types -- Section 5.4
+-- entity FIFO -- --
+-- entity inline_20 test Section 5.4
+inline_21.vhd entity and_gate behavioral Section 5.4
+-- entity inline_21 test Section 5.4
+inline_22.vhd entity mux4 functional Section 5.4
+-- entity inline_22 test Section 5.4
+inline_23.vhd entity and_or_inv functional Section 5.4
+-- entity inline_23 test Section 5.4
+inline_24.vhd entity and3 functional Section 5.4
+-- entity inline_24 test Section 5.4
+inline_28a.vhd entity inline_28a test Section 5.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_and_or_inv.vhd entity tb_and_or_inv test and_or_inv.vhd
+tb_edge_triggered_Dff.vhd entity tb_edge_triggered_Dff test edge_triggered_Dff.vhd
+tb_mux2.vhd entity tb_mux2 test mux2.vhd
+tb_and2.vhd entity tb_and2 test and2.vhd
+tb_full_adder.vhd entity tb_full_adder test full_adder.vhd
+tb_S_R_flipflop.vhd entity tb_S_R_flipflop test S_R_flipflop.vhd
+tb_S_R_flipflop-1.vhd -- functional S_R_flipflop.vhd
+-- entity tb_S_R_flipflop test --
+tb_rom.vhd -- do_nothing rom.vhd
+-- entity tb_rom test --
+tb_reg4.vhd entity tb_reg4 test reg4.vhd
+tb_counter.vhd entity tb_counter test counter.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd
new file mode 100644
index 000000000..adb54ff85
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+package adder_types is
+
+ subtype word is integer;
+
+end package adder_types;
+
+
+use work.adder_types.all;
+
+-- end not in book
+
+entity adder is
+ port ( a : in word;
+ b : in word;
+ sum : out word );
+end entity adder;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd
new file mode 100644
index 000000000..898acfe7e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+package adder_types is
+
+ subtype word is integer;
+
+end package adder_types;
+
+
+use work.adder_types.all;
+
+-- end not in book
+
+entity adder is
+ port ( a, b : in word;
+ sum : out word );
+end entity adder;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd
new file mode 100644
index 000000000..2708126e0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd
@@ -0,0 +1,23 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity and_or_inv is
+ port ( a1, a2, b1, b2 : in bit := '1';
+ y : out bit );
+end entity and_or_inv;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd
new file mode 100644
index 000000000..7b83355e9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd
@@ -0,0 +1,21 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity top_level is
+end entity top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd
new file mode 100644
index 000000000..a1ef02cc2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd
@@ -0,0 +1,28 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+architecture abstract of adder is
+begin
+
+ add_a_b : process (a, b) is
+ begin
+ sum <= a + b;
+ end process add_a_b;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd
new file mode 100644
index 000000000..3fbe1ed08
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+ signal y : bit := '0';
+ signal or_a_b : bit := '0';
+ signal clk : bit := '0';
+
+begin
+
+
+ process_3_a : process is
+ begin
+
+ -- code from book:
+
+ y <= not or_a_b after 5 ns;
+
+ -- end of code from book
+
+ wait on or_a_b;
+ end process process_3_a;
+
+
+ stimulus_3_a : process is
+ begin
+ or_a_b <= '1' after 20 ns,
+ '0' after 40 ns;
+ wait;
+ end process stimulus_3_a;
+
+
+ process_3_b : process is
+ constant T_pw : delay_length := 10 ns;
+ begin
+
+ -- code from book:
+
+ clk <= '1' after T_pw, '0' after 2*T_pw;
+
+ -- end of code from book
+
+ wait for 2*T_pw;
+ end process process_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd
new file mode 100644
index 000000000..8a4554d9c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+architecture test of inline_07 is
+
+ signal clk, d : std_ulogic;
+
+ constant Tpw_clk : delay_length := 10 ns;
+ constant Tsu : delay_length := 4 ns;
+
+begin
+
+
+ process_3_c : process (clk, d) is
+ begin
+
+ -- code from book:
+
+ if clk'event and (clk = '1' or clk = 'H')
+ and (clk'last_value = '0' or clk'last_value = 'L')
+ then
+ assert d'last_event >= Tsu
+ report "Timing error: d changed within setup time of clk";
+ end if;
+
+ -- end of code from book
+
+ end process process_3_c;
+
+
+ ----------------
+
+
+ process_3_d : process (clk, d) is
+ begin
+
+ -- code from book:
+
+ assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
+ report "Clock frequency too high";
+
+ -- end of code from book
+
+ end process process_3_d;
+
+
+ ----------------
+
+
+ process_3_e : process is
+ begin
+
+ -- code from book:
+
+ wait until clk = '1';
+
+ -- end of code from book
+
+ report "clk changed to '1'";
+ end process process_3_e;
+
+
+ ----------------
+
+
+ stimulus_3_c_d : process is
+ begin
+
+ clk <= '1' after 15 ns,
+ '0' after 30 ns,
+ '1' after 40 ns,
+ '0' after 50 ns,
+ 'H' after 60 ns,
+ '0' after 70 ns,
+ '1' after 80 ns,
+ 'L' after 90 ns,
+ 'H' after 100 ns,
+ 'L' after 120 ns,
+ '1' after 125 ns, -- should cause error
+ '0' after 130 ns; -- should cause error
+
+ d <= '1' after 35 ns,
+ '0' after 77 ns, -- should cause error
+ '1' after 102 ns;
+
+ wait;
+ end process stimulus_3_c_d;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd
new file mode 100644
index 000000000..bcc6d1a93
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+library util; use util.stimulus_generators.all;
+
+architecture test of inline_08 is
+
+ constant T_pd : delay_length := 5 ns;
+
+ signal a, b : bit := '0';
+ signal test_inputs : bit_vector(1 to 2);
+
+begin
+
+
+ block_3_f : block is
+
+ signal sum, carry : bit;
+
+ begin
+
+ -- code from book:
+
+ half_add : process is
+ begin
+ sum <= a xor b after T_pd;
+ carry <= a and b after T_pd;
+ wait on a, b;
+ end process half_add;
+
+ -- end of code from book
+
+ end block block_3_f;
+
+
+ ----------------
+
+
+ block_3_g : block is
+
+ signal sum, carry : bit;
+
+ begin
+
+ -- code from book:
+
+ half_add : process (a, b) is
+ begin
+ sum <= a xor b after T_pd;
+ carry <= a and b after T_pd;
+ end process half_add;
+
+ -- end of code from book
+
+ end block block_3_g;
+
+
+ ----------------
+
+
+ stimulus_3_f_g :
+ all_possible_values(test_inputs, 20 ns);
+
+ (a, b) <= test_inputs;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd
new file mode 100644
index 000000000..7839e859d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd
@@ -0,0 +1,119 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+
+ signal clk, reset, trigger, test0, test1 : bit := '0';
+
+begin
+
+
+ process_3_h : process is
+ begin
+
+ -- code from book:
+
+ wait until clk = '1';
+
+ -- end of code from book
+
+ report "clk rising edge detected";
+
+ end process process_3_h;
+
+
+ ----------------
+
+
+ process_3_i : process is
+ begin
+
+ -- code from book:
+
+ wait on clk until reset = '0';
+
+ -- end of code from book
+
+ report "synchronous reset detected";
+
+ end process process_3_i;
+
+
+ ----------------
+
+
+ process_3_j : process is
+ begin
+
+ -- code from book:
+
+ wait until trigger = '1' for 1 ms;
+
+ -- end of code from book
+
+ if trigger'event and trigger = '1' then
+ report "trigger rising edge detected";
+ else
+ report "trigger timeout";
+ end if;
+
+ end process process_3_j;
+
+
+ ----------------
+
+
+ -- code from book:
+
+ test_gen : process is
+ begin
+ test0 <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
+ test1 <= '0' after 10 ns, '1' after 30 ns;
+ wait;
+ end process test_gen;
+
+ -- end of code from book
+
+
+ ----------------
+
+
+ stimulus_3_h_i_j : process is
+ begin
+ clk <= '1' after 10 ns, '0' after 20 ns,
+ '1' after 30 ns, '0' after 40 ns,
+ '1' after 50 ns, '0' after 60 ns,
+ '1' after 70 ns, '0' after 80 ns;
+ reset <= '1' after 45 ns, '0' after 75 ns;
+ trigger <= '1' after 10 ns, '0' after 20 ns,
+ '1' after 30 ns, '0' after 40 ns;
+
+ wait;
+ end process stimulus_3_h_i_j;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd
new file mode 100644
index 000000000..bca36c805
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_10 is
+
+end entity inline_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_10 is
+
+ signal data : bit_vector(7 downto 0) := X"FF";
+ signal s : bit := '0';
+
+begin
+
+
+ process_3_l : process is
+ begin
+ wait for 10 ns;
+
+ -- code from book:
+
+ data <= X"00";
+
+ -- end of code from book
+
+ wait for 10 ns;
+
+ -- code from book:
+
+ s <= '1';
+ -- . . .
+ if s = '1' then -- . . .
+ -- not in book
+ report "s is '1'";
+ else
+ report "s is '0'";
+ end if;
+ -- end not in boook
+
+ -- end of code from book
+
+ wait;
+ end process process_3_l;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd
new file mode 100644
index 000000000..c86fd0a05
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_11 is
+
+end entity inline_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_11 is
+
+ signal line_in, line_out : bit := '0';
+
+begin
+
+
+ -- code from book:
+
+ transmission_line : process (line_in) is
+ begin
+ line_out <= transport line_in after 500 ps;
+ end process transmission_line;
+
+ -- end of code from book
+
+
+ ----------------
+
+
+ stimulus : process is
+ begin
+ line_in <= '1' after 2000 ps,
+ '0' after 4000 ps,
+ '1' after 6000 ps,
+ '0' after 6200 ps,
+ '1' after 8000 ps,
+ '0' after 8200 ps,
+ '1' after 8300 ps,
+ '0' after 8400 ps;
+
+ wait;
+ end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd
new file mode 100644
index 000000000..3892d65c2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_12 is
+
+end entity inline_12;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_12 is
+
+ signal top_a, bottom_a : bit := '0';
+ signal top_y, bottom_y : bit;
+
+begin
+
+
+ block_3_m : block is
+ port ( a : in bit; y : out bit := '1' );
+ port map ( a => top_a, y => top_y );
+
+ begin
+
+ -- code from book:
+
+ inv : process (a) is
+ begin
+ y <= inertial not a after 3 ns;
+ end process inv;
+
+ -- end of code from book
+
+ end block block_3_m;
+
+
+ ----------------
+
+
+ block_3_n : block is
+ port ( a : in bit; y : out bit := '1' );
+ port map ( a => bottom_a, y => bottom_y);
+
+ begin
+
+ -- code from book:
+
+ inv : process (a) is
+ begin
+ y <= reject 2 ns inertial not a after 3 ns;
+ end process inv;
+
+ -- end of code from book
+
+ end block block_3_n;
+
+
+ ----------------
+
+
+ stimulus_3_m_n : process is
+ begin
+ top_a <= '1' after 1 ns,
+ '0' after 6 ns,
+ '1' after 8 ns;
+ bottom_a <= '1' after 1 ns,
+ '0' after 6 ns,
+ '1' after 9 ns,
+ '0' after 11.5 ns,
+ '1' after 16 ns,
+ '0' after 18 ns,
+ '1' after 19 ns,
+ '0' after 20 ns;
+
+ wait;
+ end process stimulus_3_m_n;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd
new file mode 100644
index 000000000..54acc1142
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_13 is
+
+end entity inline_13;
+
+
+----------------------------------------------------------------
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+architecture test of inline_13 is
+
+ signal s : std_ulogic;
+
+begin
+
+
+ process_3_o : process is
+ begin
+ s <= '1' after 11 ns,
+ 'X' after 12 ns,
+ '1' after 14 ns,
+ '0' after 15 ns,
+ '1' after 16 ns,
+ '1' after 17 ns,
+ '1' after 20 ns,
+ '0' after 25 ns;
+ wait for 10 ns;
+
+ -- code from book:
+
+ s <= reject 5 ns inertial '1' after 8 ns;
+
+ -- end of code from book
+
+ wait;
+ end process process_3_o;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd
new file mode 100644
index 000000000..359f880ea
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_14 is
+
+end entity inline_14;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_14 is
+
+ signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
+
+begin
+
+
+ block_3_p : block is
+ port ( next_PC : out integer );
+ port map ( next_PC => functional_next_PC );
+ begin
+
+ -- code from book:
+
+ PC_incr : next_PC <= PC + 4 after 5 ns;
+
+ -- end of code from book
+
+ end block block_3_p;
+
+
+ ----------------
+
+
+ block_3_q : block is
+ port ( next_PC : out integer );
+ port map ( next_PC => equivalent_next_PC );
+ begin
+
+ -- code from book:
+
+ PC_incr : process is
+ begin
+ next_PC <= PC + 4 after 5 ns;
+ wait on PC;
+ end process PC_incr;
+
+ -- end of code from book
+
+ end block block_3_q;
+
+
+ ----------------
+
+
+ stimulus : process is
+ begin
+ for i in 1 to 10 loop
+ PC <= i after 20 ns;
+ wait for 20 ns;
+ end loop;
+ wait;
+ end process stimulus;
+
+ verifier :
+ assert functional_next_PC = equivalent_next_PC
+ report "Functional and equivalent models give different results";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd
new file mode 100644
index 000000000..a0cd6e827
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_15 is
+ generic ( extended_reset : boolean := false );
+end entity inline_15;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_15 is
+
+ signal functional_reset, equivalent_reset : bit := '0';
+
+begin
+
+
+ block_3_r : block is
+ port ( reset : out bit );
+ port map ( reset => functional_reset );
+ begin
+
+ -- code from book:
+
+ reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
+ '1', '0' after 50 ns;
+
+ -- end of code from book
+
+ end block block_3_r;
+
+
+ ----------------
+
+
+ block_3_s : block is
+ port ( reset : out bit );
+ port map ( reset => equivalent_reset );
+ begin
+
+ -- code from book:
+
+ reset_gen : process is
+ begin
+ if extended_reset then
+ reset <= '1', '0' after 200 ns;
+ else
+ reset <= '1', '0' after 50 ns;
+ end if;
+ wait;
+ end process reset_gen;
+
+ -- end of code from book
+
+ end block block_3_s;
+
+
+ ----------------
+
+
+ verifier :
+ assert functional_reset = equivalent_reset
+ report "Functional and equivalent models give different results";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd
new file mode 100644
index 000000000..8be519e72
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_16 is
+
+end entity inline_16;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_16 is
+
+ constant Tpd_01 : time := 800 ps;
+ constant Tpd_10 : time := 500 ps;
+
+ signal a, z : bit;
+
+begin
+
+
+ -- code from book:
+
+ asym_delay : z <= transport a after Tpd_01 when a = '1' else
+ a after Tpd_10;
+
+ -- end of code from book
+
+
+ ----------------
+
+
+ stimulus : process is
+ begin
+ a <= '1' after 2000 ps,
+ '0' after 4000 ps,
+ '1' after 6000 ps,
+ '0' after 6200 ps;
+
+ wait;
+ end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd
new file mode 100644
index 000000000..f0a40ce37
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_17 is
+
+end entity inline_17;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_17 is
+
+ signal s, r, q, q_n : bit := '0';
+
+begin
+
+ q <= '1' when s = '1' else
+ '0' when r = '1';
+
+ q_n <= '0' when s = '1' else
+ '1' when r = '1';
+
+
+ -- code from book:
+
+ check : process is
+ begin
+ assert not (s = '1' and r = '1')
+ report "Incorrect use of S_R_flip_flop: s and r both '1'";
+ wait on s, r;
+ end process check;
+
+ -- end of code from book
+
+
+ stimulus : process is
+ begin
+ wait for 10 ns;
+ s <= '1'; wait for 10 ns;
+ s <= '0'; wait for 10 ns;
+ r <= '1'; wait for 10 ns;
+ r <= '0'; wait for 10 ns;
+ s <= '1'; wait for 10 ns;
+ r <= '1'; wait for 10 ns;
+ s <= '0'; wait for 10 ns;
+ r <= '0'; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd
new file mode 100644
index 000000000..dee1aae59
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book:
+
+entity DRAM_controller is
+ port ( rd, wr, mem : in bit;
+ ras, cas, we, ready : out bit );
+end entity DRAM_controller;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture fpld of DRAM_controller is
+begin
+end architecture fpld;
+
+
+----------------------------------------------------------------
+
+
+entity inline_18 is
+
+end entity inline_18;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_18 is
+
+
+
+begin
+
+
+ block_4_a : block is
+ signal cpu_rd, cpu_wr, cpu_mem,
+ mem_ras, mem_cas, mem_we, cpu_rdy : bit;
+ begin
+
+ -- code from book:
+
+ main_mem_controller : entity work.DRAM_controller(fpld)
+ port map ( cpu_rd, cpu_wr, cpu_mem,
+ mem_ras, mem_cas, mem_we, cpu_rdy );
+
+ -- end of code from book
+
+ end block block_4_a;
+
+
+ ----------------
+
+
+ block_4_b : block is
+ signal cpu_rd, cpu_wr, cpu_mem,
+ mem_ras, mem_cas, mem_we, cpu_rdy : bit;
+ begin
+
+ -- code from book:
+
+ main_mem_controller : entity work.DRAM_controller(fpld)
+ port map ( rd => cpu_rd, wr => cpu_wr,
+ mem => cpu_mem, ready => cpu_rdy,
+ ras => mem_ras, cas => mem_cas, we => mem_we );
+
+ -- end of code from book
+
+ end block block_4_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd
new file mode 100644
index 000000000..b24c90fc6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd
@@ -0,0 +1,28 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package inline_19 is
+
+ -- code from book:
+
+ subtype digit is bit_vector(3 downto 0);
+
+ -- end of code from book
+
+end package inline_19;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd
new file mode 100644
index 000000000..ab99cf818
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package inline_20_types is
+
+ -- code from book:
+
+ type FIFO_status is record
+ nearly_full, nearly_empty, full, empty : bit;
+ end record FIFO_status;
+
+ -- end of code from book
+
+end package inline_20_types;
+
+
+----------------------------------------------------------------
+
+
+use work.inline_20_types.all;
+
+entity FIFO is
+ port ( status : out FIFO_status;
+ other_ports : out bit );
+end entity FIFO;
+
+
+----------------------------------------------------------------
+
+
+entity inline_20 is
+
+end entity inline_20;
+
+
+----------------------------------------------------------------
+
+
+use work.inline_20_types.all;
+
+architecture test of inline_20 is
+
+ signal start_flush, end_flush, DMA_buffer_full, DMA_buffer_empty : bit;
+
+begin
+
+ -- code from book:
+
+ DMA_buffer : entity work.FIFO
+ port map ( -- . . .,
+ status.nearly_full => start_flush,
+ status.nearly_empty => end_flush,
+ status.full => DMA_buffer_full,
+ status.empty => DMA_buffer_empty, -- . . . );
+ -- not in book
+ other_ports => open );
+ -- end not in book
+
+ -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd
new file mode 100644
index 000000000..d76021849
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book:
+
+entity and_gate is
+ port ( i : in bit_vector; y : out bit );
+end entity and_gate;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture behavioral of and_gate is
+begin
+
+ reducer : process (i) is
+ constant Tpd : delay_length := 2 ns;
+ variable result : bit;
+ begin
+ result := '1';
+ for index in i'range loop
+ result := result and i(index);
+ end loop;
+ y <= result after Tpd;
+ end process reducer;
+
+end architecture behavioral;
+
+
+----------------------------------------------------------------
+
+
+entity inline_21 is
+
+end entity inline_21;
+
+
+----------------------------------------------------------------
+
+
+library util; use util.stimulus_generators.all;
+
+architecture test of inline_21 is
+
+ -- code from book:
+
+ signal serial_select, write_en, bus_clk, serial_wr : bit;
+
+ -- end of code from book
+
+ signal test_input : bit_vector(2 downto 0);
+
+begin
+
+ -- code from book:
+
+ serial_write_gate : entity work.and_gate
+ port map ( i(1) => serial_select,
+ i(2) => write_en,
+ i(3) => bus_clk,
+ y => serial_wr );
+
+ -- end of code from book
+
+
+ ----------------
+
+
+ stimulus : all_possible_values( bv => test_input,
+ delay_between_values => 10 ns );
+
+ (serial_select, write_en, bus_clk) <= test_input;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd
new file mode 100644
index 000000000..bcdf9bd2b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book:
+
+entity mux4 is
+ port ( i0, i1, i2, i3, sel0, sel1 : in bit;
+ z : out bit );
+end entity mux4;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture functional of mux4 is
+begin
+
+ out_select : process (sel0, sel1, i0, i1, i2, i3) is
+ subtype bits_2 is bit_vector(1 downto 0);
+ begin
+ case bits_2'(sel1, sel0) is
+ when "00" => z <= i0;
+ when "01" => z <= i1;
+ when "10" => z <= i2;
+ when "11" => z <= i3;
+ end case;
+ end process out_select;
+
+end architecture functional;
+
+
+----------------------------------------------------------------
+
+
+entity inline_22 is
+
+end entity inline_22;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_22 is
+
+ signal select_line, line0, line1, result_line : bit;
+
+begin
+
+
+ -- code from book:
+
+ a_mux : entity work.mux4
+ port map ( sel0 => select_line, i0 => line0, i1 => line1,
+ z => result_line,
+ sel1 => '0', i2 => '1', i3 => '1' );
+
+ -- end of code from book
+
+
+ ----------------
+
+
+ stimulus : process is
+ begin
+ wait for 5 ns;
+ line0 <= '1'; wait for 5 ns;
+ line1 <= '1'; wait for 5 ns;
+ select_line <= '1'; wait for 5 ns;
+ line1 <= '0'; wait for 5 ns;
+ line0 <= '0'; wait for 5 ns;
+
+ wait;
+ end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd
new file mode 100644
index 000000000..3f9ebc599
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book:
+
+entity and_or_inv is
+ port ( a1, a2, b1, b2 : in bit := '1';
+ y : out bit );
+end entity and_or_inv;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture functional of and_or_inv is
+begin
+
+ func : y <= not ((a1 and a2) or (b1 and b2));
+
+end architecture functional;
+
+
+----------------------------------------------------------------
+
+
+entity inline_23 is
+
+end entity inline_23;
+
+
+----------------------------------------------------------------
+
+
+library util; use util.stimulus_generators.all;
+
+architecture test of inline_23 is
+
+ signal A, B, C, F : bit;
+ signal test_input : bit_vector(2 downto 0);
+
+begin
+
+
+ -- code from book:
+
+ f_cell : entity work.and_or_inv
+ port map ( a1 => A, a2 => B, b1 => C, b2 => open, y => F );
+
+ -- end of code from book
+
+
+ ----------------
+
+
+ stimulus : all_possible_values( bv => test_input,
+ delay_between_values => 10 ns );
+
+ (A, B, C) <= test_input;
+
+ verifier :
+ postponed assert F = not ((A and B) or C)
+ report "function model produced unexpected result";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd
new file mode 100644
index 000000000..b3658c020
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book:
+
+entity and3 is
+ port ( a, b, c : in bit := '1';
+ z, not_z : out bit);
+end entity and3;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture functional of and3 is
+begin
+
+ non_inverting:
+ z <= a and b and c;
+
+ inverting:
+ not_z <= not (a and b and c);
+
+end architecture functional;
+
+
+----------------------------------------------------------------
+
+
+entity inline_24 is
+
+end entity inline_24;
+
+
+----------------------------------------------------------------
+
+
+library util; use util.stimulus_generators.all;
+
+architecture test of inline_24 is
+
+ signal s1, s2, ctrl1_a, ctrl1_b : bit;
+ signal test_input : bit_vector(1 to 2);
+
+begin
+
+
+ block_4_a : block is
+ port ( ctrl1 : out bit );
+ port map ( ctrl1 => ctrl1_a );
+ begin
+
+ -- code from book:
+
+ g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1 );
+
+ -- end of code from book
+
+ end block block_4_a;
+
+
+ ----------------
+
+
+ block_4_b : block is
+ port ( ctrl1 : out bit );
+ port map ( ctrl1 => ctrl1_b );
+ begin
+
+ -- code from book:
+
+ g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1,
+ c => open, z => open );
+
+ -- end of code from book
+
+ end block block_4_b;
+
+
+ ----------------
+
+
+ stimulus : all_possible_values( bv => test_input,
+ delay_between_values => 10 ns );
+
+ (s1, s2) <= test_input;
+
+ verifier :
+ assert ctrl1_a = ctrl1_b
+ report "versions differ";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd
new file mode 100644
index 000000000..d0f0b2178
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_28a is
+
+end entity inline_28a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_28a is
+
+ quantity disp : real;
+ constant min_high : real := 2.5;
+
+begin
+
+
+ process_3_h : process is
+ begin
+
+ -- code from book:
+
+ wait until disp'above(min_high) for 2.0;
+
+ -- end of code from book
+
+ wait;
+ end process process_3_h;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd
new file mode 100644
index 000000000..14bf0b905
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity reg is
+ port ( d : in bit_vector(7 downto 0);
+ q : out bit_vector(7 downto 0);
+ clk : in bit );
+end entity reg;
+
+--------------------------------------------------
+
+-- not in book
+
+entity microprocessor is
+end entity microprocessor;
+
+-- end not in book
+
+architecture RTL of microprocessor is
+
+ signal interrupt_req : bit;
+ signal interrupt_level : bit_vector(2 downto 0);
+ signal carry_flag, negative_flag, overflow_flag, zero_flag : bit;
+ signal program_status : bit_vector(7 downto 0);
+ signal clk_PSR : bit;
+ -- . . .
+
+begin
+
+ PSR : entity work.reg
+ port map ( d(7) => interrupt_req,
+ d(6 downto 4) => interrupt_level,
+ d(3) => carry_flag, d(2) => negative_flag,
+ d(1) => overflow_flag, d(0) => zero_flag,
+ q => program_status,
+ clk => clk_PSR );
+ -- . . .
+
+end architecture RTL;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd
new file mode 100644
index 000000000..7baf3571d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity mux is
+end entity mux;
+
+architecture test of mux is
+
+ constant prop_delay : time := 5 ns;
+
+ signal a, b, sel, z : bit;
+
+begin
+
+ -- code from book
+
+ mux : process (a, b, sel) is
+ begin
+ case sel is
+ when '0' =>
+ z <= a after prop_delay;
+ when '1' =>
+ z <= b after prop_delay;
+ end case;
+ end process mux;
+
+ -- end code from book
+
+
+ stimulus : process is
+ subtype stim_vector_type is bit_vector(0 to 3);
+ type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+ constant stim_vector : stim_vector_array
+ := ( "0000",
+ "0010",
+ "0100",
+ "0111",
+ "1001",
+ "1010",
+ "1101",
+ "1111" );
+ begin
+ for i in stim_vector'range loop
+ (a, b, sel) <= stim_vector(i)(0 to 2);
+ wait for 10 ns;
+ assert z = stim_vector(i)(3);
+ end loop;
+ wait;
+ end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd
new file mode 100644
index 000000000..2b3b0f104
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity mux2 is
+ port ( a, b, sel : in bit;
+ z : out bit );
+end entity mux2;
+
+--------------------------------------------------
+
+architecture behavioral of mux2 is
+
+ constant prop_delay : time := 2 ns;
+
+begin
+
+ slick_mux : process is
+ begin
+ case sel is
+ when '0' =>
+ z <= a after prop_delay;
+ wait on sel, a;
+ when '1' =>
+ z <= b after prop_delay;
+ wait on sel, b;
+ end case;
+ end process slick_mux;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd
new file mode 100644
index 000000000..34d3d35bc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee; use ieee.std_logic_1164.all;
+
+-- end not in book
+
+
+entity program_ROM is
+ port ( address : in std_ulogic_vector(14 downto 0);
+ data : out std_ulogic_vector(7 downto 0);
+ enable : in std_ulogic );
+
+ subtype instruction_byte is bit_vector(7 downto 0);
+ type program_array is array (0 to 2**14 - 1) of instruction_byte;
+ constant program : program_array
+ := ( X"32", X"3F", X"03", -- LDA $3F03
+ X"71", X"23", -- BLT $23
+ -- not in book
+ others => X"00"
+ -- end not in book
+ -- . . .
+ );
+
+end entity program_ROM;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd
new file mode 100644
index 000000000..4451f4fd3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity reg4 is
+ port ( clk, clr, d0, d1, d2, d3 : in bit;
+ q0, q1, q2, q3 : out bit );
+end entity reg4;
+
+----------------------------------------------
+
+architecture struct of reg4 is
+begin
+
+ bit0 : entity work.edge_triggered_Dff(behavioral)
+ port map (d0, clk, clr, q0);
+ bit1 : entity work.edge_triggered_Dff(behavioral)
+ port map (d1, clk, clr, q1);
+ bit2 : entity work.edge_triggered_Dff(behavioral)
+ port map (d2, clk, clr, q2);
+ bit3 : entity work.edge_triggered_Dff(behavioral)
+ port map (d3, clk, clr, q3);
+
+end architecture struct;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd
new file mode 100644
index 000000000..9c1165b4d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity ROM is
+ port ( address : in natural;
+ data : out bit_vector(0 to 7);
+ enable : in bit );
+
+begin
+
+ trace_reads : process (enable) is
+ begin
+ if enable = '1' then
+ report "ROM read at time " & time'image(now)
+ & " from address " & natural'image(address);
+ end if;
+ end process trace_reads;
+
+end entity ROM;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd
new file mode 100644
index 000000000..930990104
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity scheduler is
+end entity scheduler;
+
+
+architecture test of scheduler is
+
+ constant scheduling_delay : delay_length := 5 ns;
+
+ subtype request_type is natural range 0 to 20;
+ type server_status_type is (ready, busy);
+
+ signal first_priority_request,
+ first_normal_request,
+ reset_request : request_type := 0;
+ signal functional_request, equivalent_request : request_type;
+ signal priority_waiting : boolean := false;
+ signal server_status : server_status_type := busy;
+
+begin
+
+ functional_scheduler : block is
+ port ( request : out request_type );
+ port map ( request => functional_request );
+ begin
+
+ -- code from book
+
+ scheduler :
+ request <= first_priority_request after scheduling_delay
+ when priority_waiting and server_status = ready else
+ first_normal_request after scheduling_delay
+ when not priority_waiting and server_status = ready else
+ unaffected
+ when server_status = busy else
+ reset_request after scheduling_delay;
+
+ -- end code from book
+
+ end block functional_scheduler;
+
+ --------------------------------------------------
+
+ equivalent_scheduler : block is
+ port ( request : out request_type );
+ port map ( request => equivalent_request );
+ begin
+
+ -- code from book
+
+ scheduler : process is
+ begin
+ if priority_waiting and server_status = ready then
+ request <= first_priority_request after scheduling_delay;
+ elsif not priority_waiting and server_status = ready then
+ request <= first_normal_request after scheduling_delay;
+ elsif server_status = busy then
+ null;
+ else
+ request <= reset_request after scheduling_delay;
+ end if;
+ wait on first_priority_request, priority_waiting, server_status,
+ first_normal_request, reset_request;
+ end process scheduler;
+
+ -- end code from book
+
+ end block equivalent_scheduler;
+
+ --------------------------------------------------
+
+ stimulus : process is
+ begin
+ first_priority_request <= 10; wait for 20 ns;
+ first_normal_request <= 5; wait for 20 ns;
+ server_status <= ready; wait for 20 ns;
+ server_status <= busy; wait for 20 ns;
+ priority_waiting <= true; wait for 20 ns;
+ server_status <= ready; wait for 20 ns;
+ first_normal_request <= 7; wait for 20 ns;
+ first_priority_request <= 12; wait for 20 ns;
+
+ wait;
+ end process stimulus;
+
+ verifier :
+ assert functional_request = equivalent_request
+ report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd
new file mode 100644
index 000000000..0c747f63a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+architecture functional of S_R_flipflop is
+
+begin
+
+ q <= '1' when s = '1' else
+ '0' when r = '1';
+
+ q_n <= '0' when s = '1' else
+ '1' when r = '1';
+
+end architecture functional;
+
+
+entity tb_S_R_flipflop is
+end entity tb_S_R_flipflop;
+
+
+architecture test of tb_S_R_flipflop is
+
+ signal s, r : bit := '0';
+ signal q, q_n : bit;
+
+begin
+
+ dut : entity work.S_R_flipflop(functional)
+ port map ( s => s, r => r, q => q, q_n => q_n );
+
+ stimulus : process is
+ begin
+ wait for 10 ns;
+ s <= '1'; wait for 10 ns;
+ s <= '0'; wait for 10 ns;
+ r <= '1'; wait for 10 ns;
+ r <= '0'; wait for 10 ns;
+ s <= '1'; wait for 10 ns;
+ r <= '1'; wait for 10 ns;
+ s <= '0'; wait for 10 ns;
+ r <= '0'; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd
new file mode 100644
index 000000000..b694ff17d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_S_R_flipflop is
+end entity tb_S_R_flipflop;
+
+
+architecture test of tb_S_R_flipflop is
+
+ signal s, r : bit := '0';
+ signal q, q_n : bit;
+
+begin
+
+ dut : entity work.S_R_flipflop(functional)
+ port map ( s => s, r => r, q => q, q_n => q_n );
+
+ stimulus : process is
+ begin
+ wait for 10 ns;
+ s <= '1'; wait for 10 ns;
+ s <= '0'; wait for 10 ns;
+ r <= '1'; wait for 10 ns;
+ r <= '0'; wait for 10 ns;
+ s <= '1'; wait for 10 ns;
+ r <= '1'; wait for 10 ns;
+ s <= '0'; wait for 10 ns;
+ r <= '0'; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd
new file mode 100644
index 000000000..f1da3ee30
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_and2 is
+end entity tb_and2;
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+architecture test of tb_and2 is
+
+ signal a, b : std_ulogic := '0';
+ signal y : std_ulogic;
+
+begin
+
+ dut : entity work.and2(detailed_delay)
+ port map ( a => a, b => b, y => y );
+
+ stimulus : process is
+ begin
+ wait for 10 ns;
+ a <= '1'; wait for 10 ns;
+ b <= '1'; wait for 10 ns;
+ b <= '0'; wait for 10 ns;
+
+ b <= '1', '0' after 250 ps; wait for 10 ns;
+ b <= '1', '0' after 350 ps; wait for 10 ns;
+ b <= '1', '0' after 450 ps; wait for 10 ns;
+ b <= '1', '0' after 550 ps; wait for 10 ns;
+ b <= '1', '0' after 650 ps; wait for 10 ns;
+ b <= '1', '0' after 750 ps; wait for 10 ns;
+ b <= '1', '0' after 850 ps; wait for 10 ns;
+
+ b <= '1'; wait for 10 ns;
+ b <= '0', '1' after 250 ps; wait for 10 ns;
+ b <= '0', '1' after 350 ps; wait for 10 ns;
+ b <= '0', '1' after 450 ps; wait for 10 ns;
+
+ b <= 'X'; wait for 10 ns;
+ b <= '0'; wait for 10 ns;
+ b <= 'X', '0' after 250 ps; wait for 10 ns;
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd
new file mode 100644
index 000000000..3d2cb6a48
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_and_or_inv is
+end entity tb_and_or_inv;
+
+
+architecture test of tb_and_or_inv is
+
+ signal a1, a2, b1, b2, y : bit;
+
+begin
+
+ dut : entity work.and_or_inv(primitive)
+ port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2,
+ y => y );
+
+ stimulus : process is
+ subtype stim_vector_type is bit_vector(0 to 3);
+ type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+ constant stim_vector : stim_vector_array
+ := ( "0000",
+ "0001",
+ "0010",
+ "0011",
+ "0100",
+ "0101",
+ "0110",
+ "0111",
+ "1000",
+ "1001",
+ "1010",
+ "1011",
+ "1100",
+ "1101",
+ "1110",
+ "1111" );
+ begin
+ for i in stim_vector'range loop
+ (a1, a2, b1, b2) <= stim_vector(i);
+ wait for 10 ns;
+ assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1))
+ or (stim_vector(i)(2) and stim_vector(i)(3)) );
+ end loop;
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd
new file mode 100644
index 000000000..31fb9c088
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_counter is
+end entity tb_counter;
+
+
+use work.counter_types.all;
+
+architecture test of tb_counter is
+
+ signal clk, clr : bit := '0';
+ signal q0, q1 : digit;
+
+begin
+
+ dut : entity work.counter(registered)
+ port map ( clk => clk, clr => clr,
+ q0 => q0, q1 => q1 );
+
+ clk_gen : clk <= not clk after 20 ns;
+
+ clr_gen : clr <= '1' after 95 ns,
+ '0' after 135 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd
new file mode 100644
index 000000000..725520a06
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_edge_triggered_Dff is
+end entity tb_edge_triggered_Dff;
+
+
+architecture test of tb_edge_triggered_Dff is
+
+ signal D, clk, clr, Q : bit := '0';
+
+begin
+
+ dut : entity work.edge_triggered_Dff(behavioral)
+ port map ( D => D, clk => clk, clr => clr,
+ Q => Q );
+
+ stimulus : process is
+ begin
+ D <= '1'; wait for 10 ns;
+ clk <= '1'; wait for 10 ns;
+ D <= '0'; wait for 10 ns;
+ clk <= '0'; wait for 10 ns;
+ D <= '1'; wait for 10 ns;
+ clr <= '1'; wait for 10 ns;
+ clk <= '1'; wait for 10 ns;
+ clr <= '0'; wait for 10 ns;
+ clk <= '0'; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd
new file mode 100644
index 000000000..f4f8c00ba
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_full_adder is
+end entity tb_full_adder;
+
+
+library util; use util.stimulus_generators.all;
+
+architecture test of tb_full_adder is
+
+ signal a, b, c_in, s, c_out : bit;
+ signal test_vector : bit_vector(1 to 3);
+
+begin
+
+ dut : entity work.full_adder
+ port map ( a => a, b => b, c_in => c_in, s => s, c_out => c_out );
+
+ all_possible_values ( test_vector, 10 ns );
+
+ (a, b, c_in) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd
new file mode 100644
index 000000000..e7bd163fd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_mux2 is
+end entity tb_mux2;
+
+architecture test of tb_mux2 is
+
+ signal a, b, sel, z : bit;
+
+begin
+
+ dut : entity work.mux2(behavioral)
+ port map ( a => a, b => b, sel => sel, z => z );
+
+ stimulus : process is
+ subtype stim_vector_type is bit_vector(0 to 3);
+ type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+ constant stim_vector : stim_vector_array
+ := ( "0000",
+ "0100",
+ "1001",
+ "1101",
+ "0010",
+ "0111",
+ "1010",
+ "1111" );
+ begin
+ for i in stim_vector'range loop
+ (a, b, sel) <= stim_vector(i)(0 to 2);
+ wait for 10 ns;
+ assert z = stim_vector(i)(3);
+ end loop;
+ wait;
+ end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd
new file mode 100644
index 000000000..d05be9c7d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_reg4 is
+end entity tb_reg4;
+
+
+architecture test of tb_reg4 is
+
+ signal clk, clr, d0, d1, d2, d3 : bit := '0';
+ signal q0, q1, q2, q3 : bit;
+
+begin
+
+ dut : entity work.reg4(struct)
+ port map ( clk => clk, clr => clr,
+ d0 => d0, d1 => d1, d2 => d2, d3 => d3,
+ q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
+
+ stimulus : process is
+ begin
+ (d3, d2, d1, d0) <= bit_vector'(b"1010"); wait for 10 ns;
+ clk <= '1'; wait for 10 ns;
+ (d3, d2, d1, d0) <= bit_vector'(b"0101"); wait for 10 ns;
+ clk <= '0'; wait for 10 ns;
+ (d3, d2, d1, d0) <= bit_vector'(b"1111"); wait for 10 ns;
+ clr <= '1'; wait for 10 ns;
+ clk <= '1'; wait for 10 ns;
+ clr <= '0'; wait for 10 ns;
+ clk <= '0'; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd
new file mode 100644
index 000000000..d69e8b7ec
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+architecture do_nothing of ROM is
+begin
+end architecture do_nothing;
+
+
+entity tb_rom is
+end entity tb_rom;
+
+
+architecture test of tb_rom is
+
+ signal address : natural := 0;
+ signal data : bit_vector(0 to 7);
+ signal enable : bit := '0';
+
+begin
+
+ dut : entity work.ROM(do_nothing)
+ port map ( address => address, data => data, enable => enable );
+
+ stimulus : process is
+ begin
+ wait for 100 ns;
+ address <= 1000; wait for 10 ns;
+ enable <= '1', '0' after 10 ns; wait for 90 ns;
+ address <= 1004; wait for 10 ns;
+ enable <= '1', '0' after 10 ns; wait for 90 ns;
+ address <= 1008; wait for 10 ns;
+ enable <= '1', '0' after 10 ns; wait for 90 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd
new file mode 100644
index 000000000..a42ae1248
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity zmux is
+end entity zmux;
+
+
+library util; use util.stimulus_generators.all;
+
+architecture test of zmux is
+
+ signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
+ signal functional_z, equivalent_z : bit;
+
+begin
+
+ functional_mux : block is
+ port ( z : out bit );
+ port map ( z => functional_z );
+ begin
+
+ -- code from book
+
+ zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
+ d1 when sel1 = '0' and sel0 = '1' else
+ d2 when sel1 = '1' and sel0 = '0' else
+ d3;
+
+ -- end code from book
+
+ end block functional_mux;
+
+ --------------------------------------------------
+
+ equivalent_mux : block is
+ port ( z : out bit );
+ port map ( z => equivalent_z );
+ begin
+
+ -- code from book
+
+ zmux : process is
+ begin
+ if sel1 = '0' and sel0 = '0' then
+ z <= d0;
+ elsif sel1 = '0' and sel0 = '1' then
+ z <= d1;
+ elsif sel1 = '1' and sel0 = '0' then
+ z <= d2;
+ else
+ z <= d3;
+ end if;
+ wait on d0, d1, d2, d3, sel0, sel1;
+ end process zmux;
+
+ -- end code from book
+
+ end block equivalent_mux;
+
+ --------------------------------------------------
+
+ stimulus :
+ all_possible_values( bv(0) => sel0, bv(1) => sel1,
+ bv(2) => d0, bv(3) => d1,
+ bv(4) => d2, bv(5) => d3,
+ delay_between_values => 10 ns );
+
+ verifier :
+ assert functional_z = equivalent_z
+ report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd
new file mode 100644
index 000000000..2f27a8c96
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity zmux is
+end entity zmux;
+
+
+library util; use util.stimulus_generators.all;
+
+architecture test of zmux is
+
+ signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
+ signal functional_z, equivalent_z : bit;
+
+begin
+
+ functional_mux : block is
+ port ( z : out bit );
+ port map ( z => functional_z );
+ begin
+
+ -- code from book
+
+ zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
+ d1 when sel1 = '0' and sel0 = '1' else
+ d2 when sel1 = '1' and sel0 = '0' else
+ d3 when sel1 = '1' and sel0 = '1';
+
+ -- end code from book
+
+ end block functional_mux;
+
+ --------------------------------------------------
+
+ equivalent_mux : block is
+ port ( z : out bit );
+ port map ( z => equivalent_z );
+ begin
+
+ -- code from book
+
+ zmux : process is
+ begin
+ if sel1 = '0' and sel0 = '0' then
+ z <= d0;
+ elsif sel1 = '0' and sel0 = '1' then
+ z <= d1;
+ elsif sel1 = '1' and sel0 = '0' then
+ z <= d2;
+ elsif sel1 = '1' and sel0 = '1' then
+ z <= d3;
+ end if;
+ wait on d0, d1, d2, d3, sel0, sel1;
+ end process zmux;
+
+ -- end code from book
+
+ end block equivalent_mux;
+
+ --------------------------------------------------
+
+ stimulus :
+ all_possible_values( bv(0) => sel0, bv(1) => sel1,
+ bv(2) => d0, bv(3) => d1,
+ bv(4) => d2, bv(5) => d3,
+ delay_between_values => 10 ns );
+
+ verifier :
+ assert functional_z = equivalent_z
+ report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/CPU.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/CPU.vhd
new file mode 100644
index 000000000..59c5d4594
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/CPU.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.numeric_bit.all;
+
+package CPU_types is
+
+ subtype word is unsigned(0 to 31);
+ subtype byte is unsigned(0 to 7);
+
+ alias convert_to_natural is
+ to_integer [ unsigned return natural ];
+
+ constant halt_opcode : byte := "00000000";
+
+ type code_array is array (natural range <>) of word;
+ constant code : code_array := ( X"01000000", X"01000000", X"02000000",
+ X"01000000", X"01000000", X"02000000",
+ X"00000000" );
+
+end package CPU_types;
+
+
+
+use work.CPU_types.all;
+
+entity CPU is
+end entity CPU;
+
+
+-- code from book
+
+architecture instrumented of CPU is
+
+ type count_file is file of natural;
+ file instruction_counts : count_file open write_mode is "instructions";
+
+begin
+
+ interpreter : process is
+
+ variable IR : word;
+ alias opcode : byte is IR(0 to 7);
+ variable opcode_number : natural;
+ type counter_array is array (0 to 2**opcode'length - 1) of natural;
+ variable counters : counter_array := (others => 0);
+ -- . . .
+
+ -- not in book
+ variable code_index : natural := 0;
+ -- end not in book
+
+ begin
+
+ -- . . . -- initialize the instruction set interpreter
+
+ instruction_loop : loop
+
+ -- . . . -- fetch the next instruction into IR
+
+ -- not in book
+ IR := code(code_index);
+ code_index := code_index + 1;
+ -- end not in book
+
+ -- decode the instruction
+ opcode_number := convert_to_natural(opcode);
+ counters(opcode_number) := counters(opcode_number) + 1;
+ -- . . .
+
+ -- execute the decoded instruction
+ case opcode is
+ -- . . .
+ when halt_opcode => exit instruction_loop;
+ -- . . .
+ -- not in book
+ when others => null;
+ -- end not in book
+ end case;
+
+ end loop instruction_loop;
+
+ for index in counters'range loop
+ write(instruction_counts, counters(index));
+ end loop;
+ wait; -- program finished, wait forever
+
+ end process interpreter;
+
+end architecture instrumented;
+
+-- code from book
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/ROM.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/ROM.vhd
new file mode 100644
index 000000000..8d033db7f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/ROM.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity ROM is
+ generic ( load_file_name : string );
+ port ( sel : in std_logic;
+ address : in std_logic_vector;
+ data : inout std_logic_vector );
+end entity ROM;
+
+--------------------------------------------------
+
+architecture behavioral of ROM is
+
+begin
+
+ behavior : process is
+
+ subtype word is std_logic_vector(0 to data'length - 1);
+ type storage_array is
+ array (natural range 0 to 2**address'length - 1) of word;
+ variable storage : storage_array;
+ variable index : natural;
+ -- . . . -- other declarations
+
+ type load_file_type is file of word;
+ file load_file : load_file_type open read_mode is load_file_name;
+
+ begin
+
+ -- load ROM contents from load_file
+ index := 0;
+ while not endfile(load_file) loop
+ read(load_file, storage(index));
+ index := index + 1;
+ end loop;
+
+ -- respond to ROM accesses
+ loop
+ -- . . .
+ end loop;
+
+ end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd
new file mode 100644
index 000000000..df3116c4a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity bus_monitor is
+end entity bus_monitor;
+
+
+
+architecture test of bus_monitor is
+
+ subtype byte is bit_vector(7 downto 0);
+ type byte_array is array (natural range <>) of byte;
+
+ function resolve_bytes ( drivers : in byte_array ) return byte is
+ begin
+ return drivers(drivers'left);
+ end function resolve_bytes;
+
+ function resolve_bits ( drivers : in bit_vector ) return bit is
+ begin
+ return drivers(drivers'left);
+ end function resolve_bits;
+
+ -- code from book (in text)
+
+ signal address : bit_vector(15 downto 0);
+ signal data : resolve_bytes byte;
+ signal rd, wr, io : bit; -- read, write, io/mem select
+ signal ready : resolve_bits bit;
+
+ -- end code from book
+
+begin
+
+-- code from book
+
+bus_monitor : process is
+
+ constant header : string(1 to 44)
+ := FF & " Time R/W I/M Address Data";
+
+ use std.textio.all;
+
+ file log : text open write_mode is "buslog";
+ variable trace_line : line;
+ variable line_count : natural := 0;
+
+begin
+
+ if line_count mod 60 = 0 then
+ write ( trace_line, header );
+ writeline ( log, trace_line );
+ writeline ( log, trace_line ); -- empty line
+ end if;
+ wait until (rd = '1' or wr = '1') and ready = '1';
+ write ( trace_line, now, justified => right, field => 10, unit => us );
+ write ( trace_line, string'(" ") );
+ if rd = '1' then
+ write ( trace_line, 'R' );
+ else
+ write ( trace_line, 'W' );
+ end if;
+ write ( trace_line, string'(" ") );
+ if io = '1' then
+ write ( trace_line, 'I' );
+ else
+ write ( trace_line, 'M' );
+ end if;
+ write ( trace_line, string'(" ") );
+ write ( trace_line, address );
+ write ( trace_line, ' ');
+ write ( trace_line, data );
+ writeline ( log, trace_line );
+ line_count := line_count + 1;
+
+end process bus_monitor;
+
+-- end code from book
+
+ stimulus : process is
+ begin
+ wait for 0.4 us - now;
+ rd <= '1', '0' after 10 ns;
+ address <= X"0000";
+ data <= B"10011110";
+ ready <= '1', '0' after 10 ns;
+
+ wait for 0.9 us - now;
+ rd <= '1', '0' after 10 ns;
+ address <= X"0001";
+ data <= B"00010010";
+ ready <= '1', '0' after 10 ns;
+
+ wait for 2.0 us - now;
+ rd <= '1', '0' after 10 ns;
+ address <= X"0014";
+ data <= B"11100111";
+ ready <= '1', '0' after 10 ns;
+
+ wait for 2.7 us - now;
+ wr <= '1', '0' after 10 ns;
+ io <= '1', '0' after 10 ns;
+ address <= X"0007";
+ data <= X"00";
+ ready <= '1', '0' after 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd
new file mode 100644
index 000000000..b357670f0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity cache is
+ generic ( cache_size, block_size, associativity : positive;
+ benchmark_name : string(1 to 10) );
+ port ( halt : in bit );
+end entity cache;
+
+
+
+architecture instrumented of cache is
+
+begin
+
+ -- code from book
+
+ cache_monitor : process is
+
+ type measurement_record is
+ record
+ cache_size, block_size, associativity : positive;
+ benchmark_name : string(1 to 10);
+ miss_rate : real;
+ ave_access_time : delay_length;
+ end record;
+ type measurement_file is file of measurement_record;
+ file measurements : measurement_file
+ open append_mode is "cache-measurements";
+ -- . . .
+
+ -- not in book
+ constant miss_count : natural := 100;
+ constant total_accesses : natural := 1000;
+ constant total_delay : delay_length := 2400 ns;
+ -- end not in book
+
+ begin
+ -- . . .
+ loop
+ -- . . .
+ -- not in book
+ wait on halt;
+ -- end not in book
+ exit when halt = '1';
+ -- . . .
+ end loop;
+
+ write ( measurements,
+ measurement_record'(
+ -- write values of generics for this run
+ cache_size, block_size, associativity, benchmark_name,
+ -- calculate performance metrics
+ miss_rate => real(miss_count) / real(total_accesses),
+ ave_access_time => total_delay / total_accesses ) );
+ wait;
+
+ end process cache_monitor;
+
+ -- end code from book
+
+end architecture instrumented;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/index-ams.txt
new file mode 100644
index 000000000..2a5e7972a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/index-ams.txt
@@ -0,0 +1,38 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 21 - Files and Input/Output
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+ROM.vhd entity ROM behavioral Figure 21-1
+stimulate_network.vhd entity stimulate_network_write_data writer --
+-- entity stimulate_network test Figure 21-2
+CPU.vhd package CPU_types -- --
+-- entity CPU instrumented Figure 21-3
+cache.vhd entity cache instrumented Figure 21-4
+read_array.vhd entity read_array_write_data writer --
+-- entity read_array test Section 21.1, Figure 21-5
+stimulus_generator.vhd entity stimulus_generator test Figure 21-6
+read_transform.vhd entity read_transform_write_data writer --
+-- entity read_transform test Section 21.1, Figure 21-7
+textio.vhd package textio -- Figure 21-8
+stimulus_interpreter-1.vhd entity stimulus_interpreter test Figure 21-9
+bus_monitor.vhd entity bus_monitor test Figure 21-10
+inline_01.vhd entity inline_01 test Section 21.1
+inline_02.vhd entity inline_02_write_data writer --
+-- entity inline_02 test Section 21.1
+inline_03.vhd entity inline_03 test Section 21.1
+inline_04.vhd entity inline_04 test Section 21.1
+inline_05.vhd entity inline_05 test Section 21.1
+inline_06.vhd entity inline_06 test Section 21.1
+inline_08.vhd entity inline_08 test Section 21.2
+inline_09.vhd entity inline_09 test Section 21.2
+inline_10.vhd entity inline_10 test Section 21.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_ROM.vhd entity tb_ROM_write_data writer --
+-- entity tb_ROM test ROM.vhd
+tb_cache.vhd entity tb_cache test cache.vhd
+-- entity tb_cache_read_data reader --
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd
new file mode 100644
index 000000000..3b7bf1579
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+ process is
+
+ -- code from book:
+
+ type integer_file is file of integer;
+
+ file lookup_table_file : integer_file is "lookup-values";
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process;
+
+
+ process is
+
+ -- code from book:
+
+ type file_open_kind is (read_mode, write_mode, append_mode);
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process;
+
+
+ process is
+
+ type element_type is (t1, t2, t3);
+
+ -- code from book:
+
+ type file_type is file of element_type;
+
+ procedure read ( file f : file_type; value : out element_type );
+
+ function endfile ( file f : file_type ) return boolean;
+
+ -- end of code from book
+
+ procedure read ( file f : file_type; value : out element_type ) is
+ begin
+ end;
+
+ function endfile ( file f : file_type ) return boolean is
+ begin
+ end;
+
+ begin
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_02.vhd
new file mode 100644
index 000000000..f31a157ae
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_02.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_02_write_data is
+end entity inline_02_write_data;
+
+
+architecture writer of inline_02_write_data is
+begin
+
+ process is
+ type bit_vector_file is file of bit_vector;
+ file vectors : bit_vector_file open write_mode is "vectors.dat";
+ begin
+ write(vectors, bit_vector'(""));
+ write(vectors, bit_vector'("1"));
+ write(vectors, bit_vector'("10"));
+ write(vectors, bit_vector'("011"));
+ write(vectors, bit_vector'("0100"));
+ write(vectors, bit_vector'("00101"));
+ write(vectors, bit_vector'("000110"));
+ write(vectors, bit_vector'("0000111"));
+ write(vectors, bit_vector'("00001000"));
+ write(vectors, bit_vector'("111111111111111111111111111111111111111111111111111111111111111111111111"));
+ wait;
+ end process;
+
+end architecture writer;
+
+
+----------------------------------------------------------------
+
+
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+begin
+
+
+ process is
+
+ type element_type is (t1, t2, t3);
+ type file_type is file of element_type;
+
+ -- code from book:
+
+ type bit_vector_file is file of bit_vector;
+
+ procedure read ( file f : file_type;
+ value : out element_type; length : out natural );
+
+ -- end of code from book
+
+ procedure read ( file f : file_type;
+ value : out element_type; length : out natural ) is
+ begin
+ end;
+
+ begin
+ wait;
+ end process;
+
+
+ process is
+
+ type bit_vector_file is file of bit_vector;
+
+ -- code from book:
+
+ file vectors : bit_vector_file open read_mode is "vectors.dat";
+ variable next_vector : bit_vector(63 downto 0);
+ variable actual_len : natural;
+
+ -- end of code from book
+
+ variable lost : boolean;
+
+ begin
+ while not endfile(vectors) loop
+
+ -- code from book:
+
+ read(vectors, next_vector, actual_len);
+
+ -- end of code from book
+
+ lost :=
+ -- code from book:
+
+ actual_len > next_vector'length
+
+ -- end of code from book
+ ;
+
+ end loop;
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_03.vhd
new file mode 100644
index 000000000..3813e2466
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_03.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+begin
+
+
+ process is
+
+ type element_type is (t1, t2, t3);
+
+ type file_type is file of element_type;
+
+ -- code from book:
+
+ procedure write ( file f : file_type; value : in element_type );
+
+ -- end of code from book
+
+ procedure write ( file f : file_type; value : in element_type ) is
+ begin
+ end;
+
+ begin
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_04.vhd
new file mode 100644
index 000000000..725af8af8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_04.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_04 is
+
+end entity inline_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04 is
+begin
+
+
+ process is
+
+ type data_file_type is file of character;
+ variable ch : character;
+
+ -- code from book:
+
+ procedure write_to_file is
+ file data_file : data_file_type open write_mode is "datafile";
+ begin
+ -- . . .
+ -- not in book
+ write(data_file, ch);
+ -- end not in book
+ end procedure write_to_file;
+
+ -- end of code from book
+
+ begin
+ ch := 'A';
+ write_to_file;
+ ch := 'B';
+ write_to_file;
+ ch := 'C';
+ write_to_file;
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_05.vhd
new file mode 100644
index 000000000..bcbe6bd65
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_05.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+ type log_file is file of string;
+
+ -- code from book:
+
+ file log_info : log_file open write_mode is "logfile";
+
+ -- end of code from book
+
+begin
+
+
+ process is
+ begin
+ write(log_info, string'("AAAA"));
+ wait for 1 ns;
+ write(log_info, string'("BBBB"));
+ wait;
+ end process;
+
+
+ process is
+ begin
+ write(log_info, string'("CCCC"));
+ wait for 1 ns;
+ write(log_info, string'("DDDD"));
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd
new file mode 100644
index 000000000..2086041ef
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd
@@ -0,0 +1,142 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+ type integer_file is file of integer;
+
+begin
+
+
+ process is
+
+ -- code from book:
+
+ file lookup_table_file, result_file : integer_file;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process;
+
+
+ process is
+
+ type element_type is (t1, t2, t3);
+
+ -- code from book:
+
+ type file_type is file of element_type;
+
+ procedure file_open ( file f : file_type;
+ external_name : in string;
+ open_kind : in file_open_kind := read_mode );
+
+ -- end of code from book
+
+ procedure file_open ( file f : file_type;
+ external_name : in string;
+ open_kind : in file_open_kind := read_mode ) is
+ begin
+ end;
+
+ begin
+ wait;
+ end process;
+
+
+ process is
+
+ -- code from book:
+
+ file lookup_table_file : integer_file open read_mode is "lookup-values";
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process;
+
+
+ process is
+
+ -- code from book:
+
+ file lookup_table_file : integer_file;
+ -- . . .
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ file_open ( lookup_table_file,
+ external_name => "lookup-values", open_kind => read_mode );
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+
+ process is
+
+ type element_type is (t1, t2, t3);
+ type file_type is file of element_type;
+
+ -- code from book:
+
+ type file_open_status is (open_ok, status_error, name_error, mode_error);
+
+ procedure file_open ( status : out file_open_status;
+ file f : file_type;
+ external_name : in string;
+ open_kind : in file_open_kind := read_mode );
+
+ procedure file_close ( file f : file_type );
+
+ -- end of code from book
+
+ procedure file_open ( status : out file_open_status;
+ file f : file_type;
+ external_name : in string;
+ open_kind : in file_open_kind := read_mode ) is
+ begin
+ end;
+
+ procedure file_close ( file f : file_type ) is
+ begin
+ end;
+
+ begin
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_08.vhd
new file mode 100644
index 000000000..e43c83fab
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_08.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_08 is
+begin
+
+
+ process is
+
+ use std.textio.all;
+ file f : text open read_mode is "inline_08.dat";
+ variable L : line;
+ variable ch : character;
+ variable s : string(1 to 5);
+ variable i : integer;
+ variable r : real;
+
+ begin
+
+ readline(f, L);
+ read(L, ch);
+ report character'image(ch);
+ read(L, ch);
+ report character'image(ch);
+
+ readline(f, L);
+ read(L, s);
+ report '"' & s & '"';
+ read(L, s);
+ report '"' & s & '"';
+
+ readline(f, L);
+
+ -- code from book:
+
+ if L'length < s'length then
+ read(L, s(1 to L'length));
+ else
+ read(L, s);
+ end if;
+
+ -- end of code from book
+
+ report '"' & s & '"';
+
+ readline(f, L);
+ read(L, i);
+ report integer'image(i);
+ read(L, r);
+ report real'image(r);
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_09.vhd
new file mode 100644
index 000000000..f2cccc434
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_09.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+begin
+
+
+ process is
+
+ use std.textio.all;
+ variable L : line;
+
+ begin
+
+ write(L, 42, justified => left, field => 5);
+ writeline(output, L);
+ write(L, 42, justified => right, field => 5);
+ writeline(output, L);
+ write(L, 123, field => 2);
+ writeline(output, L);
+
+ -- code from book:
+
+ write ( L, string'( "fred" ) );
+ write ( L, ' ' );
+ write ( L, bit_vector'( X"3A" ) );
+
+ -- end of code from book
+
+ writeline(output, L);
+
+ write(L, 3.14159, digits => 2);
+ writeline(output, L);
+ write(L, 123.4567, digits => 0);
+ writeline(output, L);
+
+ write(L, 40 ns, unit => ps);
+ writeline(output, L);
+ write(L, 23 us, unit => ms);
+ writeline(output, L);
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_10.vhd
new file mode 100644
index 000000000..059075f28
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_10.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_10 is
+
+end entity inline_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_10 is
+begin
+
+
+ process is
+
+ use std.textio.all;
+ variable L : line;
+
+ -- code from book:
+
+ type speed_category is (stopped, slow, fast, maniacal);
+ variable speed : speed_category;
+
+ -- end of code from book
+
+ begin
+
+ speed := stopped;
+
+ -- code from book:
+
+ write ( L, speed_category'image(speed) );
+
+ -- end of code from book
+
+ writeline(output, L);
+
+ speed := slow;
+ write ( L, speed_category'image(speed) );
+ writeline(output, L);
+ speed := fast;
+ write ( L, speed_category'image(speed) );
+ writeline(output, L);
+ speed := maniacal;
+ write ( L, speed_category'image(speed) );
+ writeline(output, L);
+
+ -- code from book:
+
+ readline( input, L );
+ speed := speed_category'value(L.all);
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd
new file mode 100644
index 000000000..dbec79652
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity read_array_write_data is
+end entity read_array_write_data;
+
+
+architecture writer of read_array_write_data is
+begin
+
+ process is
+
+ type integer_file is file of integer;
+ file data_file : integer_file open write_mode is "coeff-data";
+
+ begin
+ write(data_file, 0);
+ write(data_file, 1);
+ write(data_file, 2);
+ write(data_file, 3);
+ write(data_file, 4);
+ write(data_file, 5);
+ write(data_file, 6);
+ write(data_file, 7);
+ write(data_file, 8);
+ write(data_file, 9);
+ write(data_file, 10);
+ write(data_file, 11);
+ write(data_file, 12);
+ write(data_file, 13);
+ write(data_file, 14);
+ write(data_file, 15);
+ write(data_file, 16);
+ write(data_file, 17);
+ write(data_file, 18);
+
+ wait;
+ end process;
+
+end architecture writer;
+
+
+
+entity read_array is
+end entity read_array;
+
+
+architecture test of read_array is
+begin
+
+ process is
+
+ -- code from book (in text)
+
+ type integer_vector is array (integer range <>) of integer;
+
+ -- end code from book
+
+ -- code from book (in Figure)
+
+ impure function read_array ( file_name : string; array_length : natural )
+ return integer_vector is
+ type integer_file is file of integer;
+ file data_file : integer_file open read_mode is file_name;
+ variable result : integer_vector(1 to array_length) := (others => 0);
+ variable index : integer := 1;
+ begin
+ while not endfile(data_file) and index <= array_length loop
+ read(data_file, result(index));
+ index := index + 1;
+ end loop;
+ return result;
+ end function read_array;
+
+ -- end code from book
+
+ -- code from book (in text)
+
+ constant coeffs : integer_vector := read_array("coeff-data", 16);
+
+ -- end code from book
+
+ begin
+ wait;
+ end process;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_transform.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_transform.vhd
new file mode 100644
index 000000000..74f1d727d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_transform.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity read_transform_write_data is
+end entity read_transform_write_data;
+
+
+architecture writer of read_transform_write_data is
+begin
+
+ process is
+ type transform_file is file of real;
+ file initial_transforms : transform_file open write_mode is "transforms.ini";
+ begin
+ for i in 1 to 50 loop
+ write(initial_transforms, real(i));
+ end loop;
+ wait;
+ end process;
+
+end architecture writer;
+
+
+
+
+entity read_transform is
+end entity read_transform;
+
+
+architecture test of read_transform is
+begin
+
+ process is
+
+ -- code from book (in text)
+
+ type transform_array is array (1 to 3, 1 to 3) of real;
+ variable transform1, transform2 : transform_array;
+
+ type transform_file is file of real;
+ file initial_transforms : transform_file open read_mode is "transforms.ini";
+
+ -- end code from book
+
+ -- code from book (in Figure)
+
+ procedure read_transform ( file f : transform_file;
+ variable transform : out transform_array ) is
+ begin
+ for i in transform'range(1) loop
+ for j in transform'range(2) loop
+ if endfile(f) then
+ report "unexpected end of file in read_transform - "
+ & "some array elements not read"
+ severity error;
+ return;
+ end if;
+ read ( f, transform(i, j) );
+ end loop;
+ end loop;
+ end procedure read_transform;
+
+ -- end code from book
+
+ begin
+
+ -- code from book (in text)
+
+ read_transform ( initial_transforms, transform1 );
+ read_transform ( initial_transforms, transform2 );
+
+ -- end code from book
+
+ wait;
+ end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulate_network.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulate_network.vhd
new file mode 100644
index 000000000..a7e7184d9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulate_network.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity stimulate_network_write_data is
+end entity stimulate_network_write_data;
+
+
+architecture writer of stimulate_network_write_data is
+begin
+
+ process is
+ type packet_file is file of bit_vector;
+ file stimulus_file : packet_file open write_mode is "test packets";
+ begin
+ write(stimulus_file, X"6C");
+ write(stimulus_file, X"05");
+ write(stimulus_file, X"3");
+
+ wait;
+ end process;
+
+end architecture writer;
+
+
+
+entity stimulate_network is
+end entity stimulate_network;
+
+
+architecture test of stimulate_network is
+
+ signal stimulus_network, stimulus_clock : bit;
+
+begin
+
+ clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
+
+ -- code from book
+
+ stimulate_network : process is
+
+ type packet_file is file of bit_vector;
+ file stimulus_file : packet_file open read_mode is "test packets";
+
+ -- variable packet : bit_vector(1 to 2048);
+ -- not in book (for testing only)
+ variable packet : bit_vector(1 to 8);
+ -- end not in book
+ variable packet_length : natural;
+
+ begin
+
+ while not endfile(stimulus_file) loop
+
+ read(stimulus_file, packet, packet_length);
+ if packet_length > packet'length then
+ report "stimulus packet too long - ignored" severity warning;
+ else
+ for bit_index in 1 to packet_length loop
+ wait until stimulus_clock = '1';
+ stimulus_network <= not stimulus_network;
+ wait until stimulus_clock = '0';
+ stimulus_network <= stimulus_network xor packet(bit_index);
+ end loop;
+ end if;
+
+ end loop;
+
+ wait; -- end of stimulation: wait forever
+
+ end process stimulate_network;
+
+ -- code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_generator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_generator.vhd
new file mode 100644
index 000000000..0393ff7ba
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_generator.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity stimulus_generator is
+end entity stimulus_generator;
+
+
+architecture test of stimulus_generator is
+
+
+
+begin
+
+ -- code from book
+
+ stimulus_generator : process is
+
+ type directory_file is file of string;
+ file directory : directory_file open read_mode is "stimulus-directory";
+ variable file_name : string(1 to 50);
+ variable file_name_length : natural;
+ variable open_status : file_open_status;
+
+ subtype stimulus_vector is std_logic_vector(0 to 9);
+ type stimulus_file is file of stimulus_vector;
+ file stimuli : stimulus_file;
+ variable current_stimulus : stimulus_vector;
+ -- . . .
+
+ begin
+ file_loop : while not endfile(directory) loop
+ read( directory, file_name, file_name_length );
+ if file_name_length > file_name'length then
+ report "file name too long: " & file_name & "... - file skipped"
+ severity warning;
+ next file_loop;
+ end if;
+ file_open ( open_status, stimuli,
+ file_name(1 to file_name_length), read_mode );
+ if open_status /= open_ok then
+ report file_open_status'image(open_status) & " while opening file "
+ & file_name(1 to file_name_length) & " - file skipped"
+ severity warning;
+ next file_loop;
+ end if;
+ stimulus_loop : while not endfile(stimuli) loop
+ read(stimuli, current_stimulus);
+ -- . . . -- apply the stimulus
+ end loop stimulus_loop;
+ file_close(stimuli);
+ end loop file_loop;
+ wait;
+ end process stimulus_generator;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_interpreter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_interpreter-1.vhd
new file mode 100644
index 000000000..138ece893
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_interpreter-1.vhd
@@ -0,0 +1,150 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity stimulus_interpreter is
+end entity stimulus_interpreter;
+
+
+architecture test of stimulus_interpreter is
+
+ quantity temperature : real;
+ signal temp_sig, setting : real;
+ signal enable, heater_fail : bit;
+
+begin
+
+-- code from book
+
+stimulus_interpreter : process is
+
+ use std.textio.all;
+
+ file control : text open read_mode is "control";
+
+ variable command : line;
+ variable read_ok : boolean;
+ variable next_time : time;
+ variable whitespace : character;
+ variable signal_id : string(1 to 4);
+ variable temp_value, set_value : real;
+ variable on_value, fail_value : bit;
+
+begin
+
+ command_loop : while not endfile(control) loop
+
+ readline ( control, command );
+
+ -- read next stimulus time, and suspend until then
+ read ( command, next_time, read_ok );
+ if not read_ok then
+ report "error reading time from line: " & command.all
+ severity warning;
+ next command_loop;
+ end if;
+ wait for next_time - now;
+
+ -- skip whitespace
+ while command'length > 0
+ and ( command(command'left) = ' ' -- ordinary space
+ or command(command'left) = ' ' -- non-breaking space
+ or command(command'left) = HT ) loop
+ read ( command, whitespace );
+ end loop;
+
+ -- read signal identifier string
+ read ( command, signal_id, read_ok );
+ if not read_ok then
+ report "error reading signal id from line: " & command.all
+ severity warning;
+ next command_loop;
+ end if;
+ -- dispatch based on signal id
+ case signal_id is
+
+ when "temp" =>
+ read ( command, temp_value, read_ok );
+ if not read_ok then
+ report "error reading temperature value from line: "
+ & command.all
+ severity warning;
+ next command_loop;
+ end if;
+ temp_sig <= temp_value;
+
+ when "set " =>
+ -- . . . -- similar to "temp"
+
+ -- not in book
+ read ( command, set_value, read_ok );
+ if not read_ok then
+ report "error reading setting value from line: "
+ & command.all
+ severity warning;
+ next command_loop;
+ end if;
+ setting <= set_value;
+ -- end not in book
+
+ when "on " =>
+ read ( command, on_value, read_ok );
+ if not read_ok then
+ report "error reading on value from line: "
+ & command.all
+ severity warning;
+ next command_loop;
+ end if;
+ enable <= on_value;
+
+ when "fail" =>
+ -- . . . -- similar to "on "
+
+ -- not in book
+ read ( command, fail_value, read_ok );
+ if not read_ok then
+ report "error reading fail value from line: "
+ & command.all
+ severity warning;
+ next command_loop;
+ end if;
+ heater_fail <= fail_value;
+ -- end not in book
+
+ when others =>
+ report "invalid signal id in line: " & signal_id
+ severity warning;
+ next command_loop;
+
+ end case;
+
+ end loop command_loop;
+
+ wait;
+
+end process stimulus_interpreter;
+
+-- end code from book
+
+-- code from book (in text)
+
+temperature == temp_sig'ramp;
+
+-- end code from book (in text)
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_ROM.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_ROM.vhd
new file mode 100644
index 000000000..7aece5fdc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_ROM.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity tb_ROM_write_data is
+end entity tb_ROM_write_data;
+
+
+architecture writer of tb_ROM_write_data is
+begin
+
+ process is
+
+ subtype word is std_logic_vector(0 to 7);
+ type load_file_type is file of word;
+ file load_file : load_file_type open write_mode is "tb_ROM.dat";
+
+ begin
+ write(load_file, word'(X"00"));
+ write(load_file, word'(X"01"));
+ write(load_file, word'(X"02"));
+ write(load_file, word'(X"03"));
+ write(load_file, word'(X"04"));
+ write(load_file, word'(X"05"));
+ write(load_file, word'(X"06"));
+ write(load_file, word'(X"07"));
+ write(load_file, word'(X"08"));
+ write(load_file, word'(X"09"));
+ write(load_file, word'(X"0A"));
+ write(load_file, word'(X"0B"));
+ write(load_file, word'(X"0C"));
+ write(load_file, word'(X"0D"));
+ write(load_file, word'(X"0E"));
+ write(load_file, word'(X"0F"));
+
+ wait;
+ end process;
+
+end architecture writer;
+
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity tb_ROM is
+end entity tb_ROM;
+
+
+architecture test of tb_ROM is
+
+ signal sel : std_logic;
+ signal address : std_logic_vector(3 downto 0);
+ signal data : std_logic_vector(0 to 7);
+
+begin
+
+ dut : entity work.ROM(behavioral)
+ generic map ( load_file_name => "tb_ROM.dat" )
+ port map ( sel, address, data );
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd
new file mode 100644
index 000000000..075901015
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_cache is
+end entity tb_cache;
+
+
+
+architecture test of tb_cache is
+
+ signal halt : bit := '0';
+
+begin
+
+ dut : entity work.cache(instrumented)
+ generic map ( cache_size => 128*1024, block_size => 16,
+ associativity => 2, benchmark_name => "dhrystone " )
+ port map ( halt => halt );
+
+ halt <= '1' after 10 ns;
+
+end architecture test;
+
+
+
+entity tb_cache_read_data is
+end entity tb_cache_read_data;
+
+
+architecture reader of tb_cache_read_data is
+begin
+
+ process is
+
+ type measurement_record is
+ record
+ cache_size, block_size, associativity : positive;
+ benchmark_name : string(1 to 10);
+ miss_rate : real;
+ ave_access_time : delay_length;
+ end record;
+ type measurement_file is file of measurement_record;
+ file measurements : measurement_file open read_mode is "cache-measurements";
+ variable measurement : measurement_record;
+
+ use std.textio.all;
+ variable L : line;
+
+ begin
+ while not endfile(measurements) loop
+ read(measurements, measurement);
+ write(L, measurement.cache_size);
+ write(L, ' ');
+ write(L, measurement.block_size);
+ write(L, ' ');
+ write(L, measurement.associativity);
+ write(L, ' ');
+ write(L, measurement.benchmark_name);
+ write(L, ' ');
+ write(L, measurement.miss_rate);
+ write(L, ' ');
+ write(L, measurement.ave_access_time);
+ writeline(output, L);
+
+ end loop;
+
+ wait;
+ end process;
+
+end architecture reader;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/textio.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/textio.vhd
new file mode 100644
index 000000000..7b5cffef6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/textio.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package textio is
+
+ type line is access string;
+
+ type text is file of string;
+
+ type side is (right, left);
+
+ subtype width is natural;
+
+ file input : text open read_mode is "std_input";
+ file output : text open write_mode is "std_output";
+
+ -- use this declaration for VHDL-2001
+ procedure readline(file f: text; l: inout line);
+
+ -- use this declaration for VHDL-AMS
+ procedure readline(file f: text; l: out line);
+
+ procedure read ( L : inout line; value: out bit; good : out boolean );
+ procedure read ( L : inout line; value: out bit );
+
+ procedure read ( L : inout line; value: out bit_vector; good : out boolean );
+ procedure read ( L : inout line; value: out bit_vector );
+
+ procedure read ( L : inout line; value: out boolean; good : out boolean );
+ procedure read ( L : inout line; value: out boolean );
+
+ procedure read ( L : inout line; value: out character; good : out boolean );
+ procedure read ( L : inout line; value: out character );
+
+ procedure read ( L : inout line; value: out integer; good : out boolean );
+ procedure read ( L : inout line; value: out integer );
+
+ procedure read ( L : inout line; value: out real; good : out boolean );
+ procedure read ( L : inout line; value: out real );
+
+ procedure read ( L : inout line; value: out string; good : out boolean );
+ procedure read ( L : inout line; value: out string );
+
+ procedure read ( L : inout line; value: out time; good : out boolean );
+ procedure read ( L : inout line; value: out time );
+
+ procedure writeline ( file f : text; L : inout line );
+
+ procedure write ( L : inout line; value : in bit;
+ justified: in side := right; field: in width := 0 );
+
+ procedure write ( L : inout line; value : in bit_vector;
+ justified: in side := right; field: in width := 0 );
+
+ procedure write ( L : inout line; value : in boolean;
+ justified: in side := right; field: in width := 0 );
+
+ procedure write ( L : inout line; value : in character;
+ justified: in side := right; field: in width := 0 );
+
+ procedure write ( L : inout line; value : in integer;
+ justified: in side := right; field: in width := 0 );
+
+ procedure write ( L : inout line; value : in real;
+ justified: in side := right; field: in width := 0;
+ digits: in natural := 0 );
+
+ procedure write ( L : inout line; value : in string;
+ justified: in side := right; field: in width := 0 );
+
+ procedure write ( L : inout line; value : in time;
+ justified: in side := right; field: in width := 0;
+ unit: in time := ns );
+
+end package textio;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/index-ams.txt
new file mode 100644
index 000000000..16e7ad519
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/index-ams.txt
@@ -0,0 +1,36 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 13 - Frequency and Transfer Function Modeling
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+v_source.vhd entity v_source behavior Figure 13-3
+v_source-1.vhd entity v_source behavior Figure 13-4
+nmos_transistor.vhd entity NMOS_transistor noisy Figure 13-5
+nmos_transistor_wa.vhd entity nmos_transistor_wa noisy --
+lowpass-1.vhd entity resistor ideal --
+-- entity capacitor ideal --
+-- entity lowpass RC Figure 13-7
+lowpass-2.vhd entity lowpass dot Figure 13-9
+lowpass-3.vhd entity lowpass ltf Figure 13-11
+opamp.vhd entity opamp slew_limited Figure 13-13
+opamp_2pole.vhd entity opamp_2pole dot, ltf Figure 13-15
+opamp_2pole_res.vhd entity opamp_2pole_res ltf Figure 13-16
+lowpass-4.vhd entity lowpass z_minus_1 Figure 13-17
+lowpass-5.vhd entity lowpass ztf Figure 13-19
+lowpass.vhd entity lowpass RC, dot, ltf, z_minus_1, ztf Figure 13-22
+inline_01a.vhd entity inline_01a test Section 13.1
+inline_02a.vhd entity inline_02a test Section 13.2
+inline_03a.vhd entity inline_03a test Section 13.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_v_source.vhd entity tb_v_source TB_v_source v_source.vhd
+tb_mosfet_noisy.vhd entity tb_mosfet_noisy TB_mosfet_noisy nmos_transistor_wa.vhd
+tb_opamp.vhd entity tb_opamp TB_opamp opamp.vhd
+tb_opamp_2pole.vhd entity tb_opamp_2pole TB_opamp_2pole opamp_2pole.vhd
+tb_lpf_dot_ltf_ztf-1.vhd entity tb_lpf_dot_ltf_ztf TB_lpf_dot_ltf_ztf lowpass-1.vhd, lowpass-2.vhd,
+-- lowpass-3.vhd, lowpass-4.vhd,
+-- lowpass-5.vhd
+tb_lpf_dot_ltf_ztf.vhd entity tb_lpf_dot_ltf_ztf TB_lpf_dot_ltf_ztf lowpass.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd
new file mode 100644
index 000000000..c6e2a9c25
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+library ieee; use ieee.math_real.all;
+
+entity inline_01a is
+
+end entity inline_01a;
+
+
+architecture test of inline_01a is
+
+ function inverse_exp ( x : real ) return real is
+ begin
+ return 10.0 * exp(-2.0e-6 * x);
+ end function inverse_exp;
+
+ -- code from book
+
+ type domain_type is (quiescent_domain, time_domain, frequency_domain);
+
+ --
+
+ quantity spec_source : real spectrum 2.5, math_pi / 2.0;
+
+ --
+
+ function frequency return real;
+
+ --
+
+ quantity source1 : real spectrum inverse_exp(frequency), math_pi / 4.0;
+
+ --
+
+ quantity source2 : real spectrum 5.0, 1.0E-6 * frequency / math_pi;
+
+ -- end code from book
+
+ function frequency return real is
+ begin
+ return std.standard.frequency;
+ end function frequency;
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd
new file mode 100644
index 000000000..6864aaa27
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+use ieee_proposed.energy_systems.all;
+
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+architecture test of inline_02a is
+
+ constant k_Boltzmann : real := K;
+ constant temp : real := 300.0;
+ constant res : real := 10_000.0;
+ terminal r_p1, r_p2 : electrical;
+ quantity resistor_voltage across resistor_current through r_p1 to r_p2;
+
+ constant k_noise : real := 1.0;
+
+ function G ( f : real ) return real is
+ begin
+ return 1.0;
+ end function G;
+
+ constant k_flicker : real := 1.0;
+ constant ids : real := 0.01;
+ constant af : real := 1.0;
+
+ -- code from book
+
+ quantity thermal_noise_source : real noise 4.0 * k_Boltzmann * temp * res;
+
+ --
+
+ quantity shaped_noise_source : real noise k_noise * temp * G(frequency);
+
+ --
+
+ quantity flicker_noise_source : real noise k_flicker * ids**af / frequency;
+
+ -- end code from book
+
+begin
+
+ -- code from book
+
+ resistor_voltage == resistor_current * res + thermal_noise_source;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd
new file mode 100644
index 000000000..e9889f00c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+library ieee; use ieee.math_real.all;
+
+entity inline_03a is
+
+end entity inline_03a;
+
+
+architecture test of inline_03a is
+
+ -- code from book
+
+ constant fp : real := 10.0; -- filter pole in hertz
+ constant wp : real := math_2_pi * fp; -- filter pole in rad/s
+ constant tp : real := 1.0 / wp; -- filter time constant
+
+ -- end code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd
new file mode 100644
index 000000000..c47c772e9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+ generic ( res : resistance );
+ port ( terminal p1, p2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+ quantity v across i through p1 to p2;
+begin
+ v == i * res;
+end architecture ideal;
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity capacitor is
+ generic ( cap : resistance );
+ port ( terminal p1, p2 : electrical );
+end entity capacitor;
+
+architecture ideal of capacitor is
+ quantity v across i through p1 to p2;
+begin
+ i == cap * v'dot;
+end architecture ideal;
+
+-- end not in book
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity lowpass is
+ port ( terminal input : electrical;
+ terminal output : electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture RC of lowpass is
+begin
+
+ R : entity work.resistor(ideal)
+ generic map ( res => 15.9e3 )
+ port map ( p1 => input, p2 => output );
+
+ C : entity work.capacitor(ideal)
+ generic map ( cap => 1.0e-6 )
+ port map ( p1 => output, p2 => electrical_ref );
+
+end architecture RC;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd
new file mode 100644
index 000000000..51624706c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity lowpass is
+ port ( terminal input : electrical;
+ terminal output : electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture dot of lowpass is
+
+ quantity vin across input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ constant tp : real := 15.9e-3; -- filter time constant
+
+begin
+
+ vin == vout + tp * vout'dot;
+
+end architecture dot;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd
new file mode 100644
index 000000000..9a1cbfa02
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+library ieee; use ieee.math_real.all;
+
+entity lowpass is
+ port ( terminal input : electrical;
+ terminal output : electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture ltf of lowpass is
+
+ quantity vin across input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ constant wp : real := 10.0 * math_2_pi; -- pole in rad/s
+ constant num : real_vector := (0 => wp); -- numerator in s
+ constant den : real_vector := (wp, 1.0); -- denominator in s
+
+begin
+
+ vout == vin'ltf(num, den);
+
+end architecture ltf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd
new file mode 100644
index 000000000..666d100e8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity lowpass is
+ generic ( fp : real := 10.0; -- pole in Hz for 'zoh, 'delayed
+ Fsmp : real := 10.0e3 ); -- sample frequency for 'zoh, 'delayed
+ port ( terminal input : electrical;
+ terminal output: electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture z_minus_1 of lowpass is
+
+ quantity vin across input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ quantity vin_sampled : real; -- discrete sample of input quantity
+ quantity vin_zm1, vout_zm1 : real; -- z**-1
+ constant Tsmp : real := 1.0 / Fsmp; -- sample period
+ constant wp : real := fp * math_2_pi; -- pole in rad/s
+ constant n0 : real := Tsmp * wp; -- z0 numerator coefficient
+ constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient
+ constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient
+ constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient
+
+begin
+
+ vin_sampled == vin'zoh(Tsmp);
+
+ vin_zm1 == vin_sampled'delayed(Tsmp);
+
+ vout_zm1 == vout'delayed(Tsmp);
+
+ vout == vin_sampled * n0 / d0 + n1 * vin_zm1 / d0 - d1 * vout_zm1 / d0;
+
+end z_minus_1;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd
new file mode 100644
index 000000000..d1f655c62
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity lowpass is
+ generic ( fp : real := 10.0; -- pole in Hz for 'ztf
+ Fsmp : real := 10.0e3); -- sample frequency for 'ztf
+ port ( terminal input: electrical;
+ terminal output: electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture ztf of lowpass is
+
+ quantity vin across input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ constant Tsmp : real := 1.0 / Fsmp; -- sample period
+ constant wp : real := fp * math_2_pi; -- pole in rad/s
+ constant n0 : real := Tsmp * wp; -- z0 numerator coefficient (a)
+ constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient (b)
+ constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient (c)
+ constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient (d)
+ constant num : real_vector := (n0, n1);
+ constant den : real_vector := (d0, d1);
+
+begin
+
+ vout == vin'ztf(num, den, Tsmp);
+
+end ztf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd
new file mode 100644
index 000000000..e553f1752
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd
@@ -0,0 +1,170 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+ generic ( res : resistance );
+ port ( terminal p1, p2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+ quantity v across i through p1 to p2;
+begin
+ v == i * res;
+end architecture ideal;
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity capacitor is
+ generic ( cap : resistance );
+ port ( terminal p1, p2 : electrical );
+end entity capacitor;
+
+architecture ideal of capacitor is
+ quantity v across i through p1 to p2;
+begin
+ i == cap * v'dot;
+end architecture ideal;
+
+-- end not in book
+
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity lowpass is
+ generic ( gain : real := 1.0; -- gain for 'dot, 'ltf, and 'ztf
+ fp : real := 10.0; -- pole in Hz for 'dot, 'ltf, and 'ztf
+ Fsmp : real := 10.0e3 ); -- sample frequency for ztf
+ port ( terminal input: electrical;
+ terminal output: electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture RC of lowpass is
+
+ constant cap : real := 1.0e-6;
+ constant res : real := 1.0 / (math_2_pi * cap * fp);
+
+begin
+
+ assert false
+ report "gain is ignored in architecture RC" severity note;
+ assert false
+ report "Fsmp is not used in architecture RC" severity note;
+
+ R : entity work.resistor(ideal)
+ generic map( res => res )
+ port map( p1 => input, p2 => output );
+
+ C : entity work.capacitor(ideal)
+ generic map( cap => cap )
+ port map( p1 => output, p2 => electrical_ref );
+
+end architecture RC;
+
+----------------------------------------------------------------
+
+architecture dot of lowpass is
+
+ quantity vin across input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ constant wp : real := fp * math_2_pi; -- pole in rad/s
+ constant tp : real := 1.0 / wp; -- time constant
+
+begin
+
+ assert false
+ report "Fsmp is not used in architecture dot" severity note;
+
+ vin == (vout + tp * vout'dot) / gain;
+
+end architecture dot;
+
+----------------------------------------------------------------
+
+architecture ltf of lowpass is
+
+ quantity vin across input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ constant wp : real := fp * math_2_pi; -- pole in rad/s
+ constant num : real_vector := (0 => wp);
+ constant den : real_vector := (wp, 1.0);
+
+begin
+
+ assert false
+ report "Fsmp is not used in architecture ltf" severity note;
+
+ vout == gain*vin'ltf(num, den);
+
+end architecture ltf;
+
+----------------------------------------------------------------
+
+architecture z_minus_1 of lowpass is
+
+ quantity vin across input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ quantity vin_sampled : real; -- sampled input
+ quantity vin_zm1, vout_zm1 : real; -- z**-1
+ constant Tsmp : real := 1.0 / Fsmp; -- sample period
+ constant wp : real := fp * math_2_pi; -- pole in rad/s
+ constant n0 : real := Tsmp * wp; -- z0 numerator coefficient
+ constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient
+ constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient
+ constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient
+
+begin
+
+ vin_sampled == gain*vin'zoh(Tsmp);
+
+ vin_zm1 == vin_sampled'delayed(Tsmp);
+
+ vout_zm1 == vout'delayed(Tsmp);
+
+ vout == vin_sampled * n0 / d0 + n1 * vin_zm1 / d0 - d1 * vout_zm1 / d0;
+
+end z_minus_1;
+
+----------------------------------------------------------------
+
+architecture ztf of lowpass is
+
+ quantity vin across input to electrical_ref;
+ quantity vout across iout through output to electrical_ref;
+ constant Tsmp : real := 1.0 / Fsmp; -- sample period
+ constant wp : real := fp * math_2_pi; -- pole in rad/s
+ constant n0 : real := Tsmp * wp; -- z0 numerator coefficient
+ constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient
+ constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient
+ constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient
+ constant num : real_vector := (n0, n1);
+ constant den : real_vector := (d0, d1);
+
+begin
+
+ vout == gain*vin'ztf(num, den, Tsmp);
+
+end ztf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd
new file mode 100644
index 000000000..763e46d73
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity NMOS_transistor is
+ generic ( Cgs : real := 1.0e-6; -- gate to source capacitance
+ Cgd : real := 1.0e-6; -- gate to drain capacitance
+ gm : real := 5.0e-4; -- transconductance
+ temp : real := 1.0; -- termperature
+ Ro : real := 500.0e3; -- ro resistance
+ af : real := 1.0; -- flicker noise exponent constant
+ k_flicker : real := 1.0 ); -- flicker noise constant
+ port ( terminal gate, drain, source : electrical );
+end entity NMOS_transistor;
+
+----------------------------------------------------------------
+
+architecture noisy of NMOS_transistor is
+
+ quantity vgs across igs through gate to source;
+ quantity vds across ids through drain to source;
+ quantity vsd across source to drain;
+ quantity vgd across igd through gate to drain;
+ constant threshold_voltage : voltage := 1.0;
+ constant k : real := 1.0e-5;
+ -- declare quantity in frequency domain for AC analysis
+ quantity MOS_noise_source : real noise
+ 4.0*K*temp/Ro + -- thermal noise
+ k_flicker*ids**af/frequency; -- flicker noise
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+
+ if vds >= 0.0 use -- transistor is forward biased
+ if vgs < threshold_voltage use -- cutoff region
+ ids == 0.0;
+ elsif vds > vgs - threshold_voltage use -- saturation region
+ ids == 0.5 * k * (vgs - threshold_voltage)**2;
+ else -- linear/triode region
+ ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
+ end use;
+ else -- transistor is reverse biased
+ if vgd < threshold_voltage use -- cutoff region
+ ids == 0.0;
+ elsif vsd > vgd - threshold_voltage use -- saturation region
+ ids == -0.5 * k * (vgd - threshold_voltage)**2;
+ else -- linear/triode region
+ ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
+ end use;
+ end use;
+
+ igs == 0.0;
+ igd == 0.0;
+
+ else -- noise and frequency model
+
+ igs == Cgs*vgs'dot;
+ igd == Cgd*vgd'dot;
+ ids == gm*vgs + vds/Ro + MOS_noise_source;
+
+ end use;
+
+end architecture noisy;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd
new file mode 100644
index 000000000..f5223e620
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity NMOS_transistor_wa is
+ port ( terminal gate, drain, source : electrical );
+end entity NMOS_transistor_wa;
+
+----------------------------------------------------------------
+
+architecture noisy of NMOS_transistor_wa is
+
+ quantity vgs across igs through gate to source;
+ quantity vds across ids through drain to source;
+ quantity vsd across source to drain;
+ quantity vgd across igd through gate to drain;
+ constant threshold_voltage : voltage := 1.0;
+ constant k : real := 1.0e-5;
+ -- declare quantity in frequency domain for AC analysis
+
+begin
+
+ if vds >= 0.0 use -- transistor is forward biased
+ if vgs < threshold_voltage use -- cutoff region
+ ids == 0.0;
+ elsif vds > vgs - threshold_voltage use -- saturation region
+ ids == 0.5 * k * (vgs - threshold_voltage)**2;
+ else -- linear/triode region
+ ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
+ end use;
+ else -- transistor is reverse biased
+ if vgd < threshold_voltage use -- cutoff region
+ ids == 0.0;
+ elsif vsd > vgd - threshold_voltage use -- saturation region
+ ids == -0.5 * k * (vgd - threshold_voltage)**2;
+ else -- linear/triode region
+ ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
+ end use;
+ end use;
+
+ igs == 0.0;
+ igd == 0.0;
+
+end architecture noisy;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd
new file mode 100644
index 000000000..4a7799c8d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity opamp is
+ port ( terminal plus_in, minus_in, output : electrical );
+end entity opamp;
+
+----------------------------------------------------------------
+
+architecture slew_limited of opamp is
+
+ constant gain : real := 50.0;
+ quantity v_in across plus_in to minus_in;
+ quantity v_out across i_out through output;
+ quantity v_amplified : voltage;
+
+begin
+
+ v_amplified == gain * v_in;
+
+ v_out == v_amplified'slew(1.0e6,-1.0e6);
+
+end architecture slew_limited;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd
new file mode 100644
index 000000000..8bef2bb8f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity opamp_2pole is
+ port ( terminal in_pos, in_neg, output : electrical );
+end entity opamp_2pole;
+
+----------------------------------------------------------------
+
+architecture dot of opamp_2pole is
+
+ constant A : real := 1.0e6; -- open loop gain
+ constant fp1 : real := 5.0; -- first pole
+ constant fp2 : real := 9.0e5; -- second pole
+ constant tp1 : real := 1.0 / (fp1 * math_2_pi); -- first time constant
+ constant tp2 : real := 1.0 / (fp2 * math_2_pi); -- second time constant
+ quantity v_in across in_pos to in_neg;
+ quantity v_out across i_out through output;
+
+begin
+
+ v_in == (tp1 * tp2) * v_out'dot'dot / A
+ + (tp1 + tp2) * v_out'dot / A + v_out / A;
+
+end architecture dot;
+
+----------------------------------------------------------------
+
+architecture ltf of opamp_2pole is
+
+ constant A : real := 1.0e6; -- open loop gain
+ constant fp1 : real := 5.0; -- first pole (Hz)
+ constant fp2 : real := 9.0e5; -- second pole (Hz)
+ constant wp1 : real := fp1 * math_2_pi; -- first pole (rad/s)
+ constant wp2 : real := fp2 * math_2_pi; -- second pole (rad/s)
+ constant num : real_vector := (0 => wp1 * wp2 * A);
+ constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0);
+ quantity v_in across in_pos to in_neg;
+ quantity v_out across i_out through output;
+
+begin
+
+ v_out == v_in'ltf(num, den);
+
+end architecture ltf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd
new file mode 100644
index 000000000..60ac210bb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity opamp_2pole_res is
+ generic ( A : real := 1.0e6; -- open loop gain
+ rin : real := 1.0e6; -- input resistance
+ rout : real := 100.0; -- output resistance
+ fp1 : real := 5.0; -- first pole
+ fp2 : real := 9.0e5 ); -- second pole
+ port ( terminal in_pos, in_neg, output : electrical );
+end entity opamp_2pole_res;
+
+----------------------------------------------------------------
+
+architecture ltf of opamp_2pole_res is
+
+ constant wp1 : real := fp1 * math_2_pi;
+ constant wp2 : real := fp2 * math_2_pi;
+ constant num : real_vector := (0 => wp1 * wp2 * A);
+ constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0);
+ quantity v_in across i_in through in_pos to in_neg;
+ quantity v_out across i_out through output;
+
+begin
+
+ i_in == v_in / rin; -- input current
+
+ v_out == v_in'ltf(num, den) + i_out * rout;
+
+end architecture ltf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd
new file mode 100644
index 000000000..a26499e6d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_lpf_dot_ltf_ztf is
+end tb_lpf_dot_ltf_ztf;
+
+architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src : electrical;
+ terminal out_dot, out_ltf, out_ztf1, out_ztf4, out_RC : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_sine(ideal)
+ generic map(
+ freq => 100.0,
+ amplitude => 5.0
+ )
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+
+ RC1 : entity work.lowpass(RC)
+
+ port map(
+ input => in_src,
+ output => out_RC
+ );
+ dot1 : entity work.lowpass(dot)
+
+ port map(
+ input => in_src,
+ output => out_dot
+ );
+ ltf1 : entity work.lowpass(ltf)
+
+ port map(
+ input => in_src,
+ output => out_ltf
+ );
+ ztf1 : entity work.lowpass(ztf)
+
+ port map(
+ input => in_src,
+ output => out_ztf1
+ );
+ ztf4 : entity work.lowpass(z_minus_1)
+
+ port map(
+ input => in_src,
+ output => out_ztf4
+ );
+end TB_lpf_dot_ltf_ztf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd
new file mode 100644
index 000000000..be639a4e6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_lpf_dot_ltf_ztf is
+end tb_lpf_dot_ltf_ztf;
+
+architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src : electrical;
+ terminal out_dot, out_ltf, out_ztf1, out_ztf2, out_ztf3, out_ztf4, out_RC : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_sine(ideal)
+ generic map(
+ freq => 100.0,
+ amplitude => 5.0
+ )
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+ RC1 : entity work.lowpass(RC)
+ generic map(
+ gain => 1.0,
+ fp => 1.0e1,
+ Fsmp => 10.0e3
+ )
+ port map(
+ input => in_src,
+ output => out_RC
+ );
+ dot1 : entity work.lowpass(dot)
+ generic map(
+ gain => 1.0,
+ fp => 1.0e1,
+ Fsmp => 10.0e3
+ )
+ port map(
+ input => in_src,
+ output => out_dot
+ );
+ ltf1 : entity work.lowpass(ltf)
+ generic map(
+ gain => 1.0,
+ fp => 1.0e1,
+ Fsmp => 10.0e3
+ )
+ port map(
+ input => in_src,
+ output => out_ltf
+ );
+ ztf1 : entity work.lowpass(ztf)
+ generic map(
+ gain => 1.0,
+ fp => 1.0e1,
+ Fsmp => 10.0e3
+ )
+ port map(
+ input => in_src,
+ output => out_ztf1
+ );
+ ztf2 : entity work.lowpass(ztf)
+ generic map(
+ gain => 1.0,
+ fp => 1.0e1,
+ Fsmp => 1000.0
+ )
+ port map(
+ input => in_src,
+ output => out_ztf2
+ );
+ ztf3 : entity work.lowpass(ztf)
+ generic map(
+ gain => 1.0,
+ fp => 1.0e1,
+ Fsmp => 100.0
+ )
+ port map(
+ input => in_src,
+ output => out_ztf3
+ );
+ ztf4 : entity work.lowpass(z_minus_1)
+ generic map(
+ gain => 1.0,
+ fp => 1.0e1,
+ Fsmp => 10.0e3
+ )
+ port map(
+ input => in_src,
+ output => out_ztf4
+ );
+end TB_lpf_dot_ltf_ztf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd
new file mode 100644
index 000000000..ebc499062
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_mosfet_noisy is
+end tb_mosfet_noisy ;
+
+architecture TB_mosfet_noisy of tb_mosfet_noisy is
+ -- Component declarations
+ -- Signal declarations
+ terminal d : electrical;
+ terminal g : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ mosfet1 : entity work.nmos_transistor_wa(noisy)
+ port map(
+ gate => g,
+ drain => d,
+ source => ELECTRICAL_REF
+ );
+ v1 : entity work.v_constant(ideal)
+ generic map(
+ level => 4.0
+ )
+ port map(
+ pos => g,
+ neg => ELECTRICAL_REF
+ );
+ mosfet2 : entity work.nmos_transistor_wa(noisy)
+ port map(
+ gate => g,
+ drain => ELECTRICAL_REF,
+ source => d
+ );
+ v4 : entity work.v_pulse(ideal)
+ generic map(
+ initial => 0.0,
+ pulse => 5.0,
+ ti2p => 1 ms,
+ tp2i => 1 ms,
+ delay => 1 us,
+ width => 1 us,
+ period => 2.002 ms
+ )
+ port map(
+ pos => d,
+ neg => ELECTRICAL_REF
+ );
+end TB_mosfet_noisy ;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd
new file mode 100644
index 000000000..9be54df36
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE; use IEEE.std_logic_1164.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_opamp is
+end tb_opamp;
+
+architecture TB_opamp of tb_opamp is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src, op_neg2, out_opamp2 : electrical;
+ terminal out_opamp1, op_neg1, op_neg3, out_opamp3, out_opamp3_res, op_neg3_res : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_sine(ideal)
+ generic map(
+ freq => 100.0,
+ amplitude => 5.0e-3
+ )
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+
+ OP1 : entity work.opamp(slew_limited)
+ port map(
+ plus_in => electrical_ref,
+ minus_in => op_neg1,
+ output => out_opamp1
+ );
+ R1in : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => in_src,
+ p2 => op_neg1
+ );
+ R1F : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e9
+ )
+ port map(
+ p1 => op_neg1,
+ p2 => out_opamp1
+ );
+ Rload1 : entity work.resistor(ideal)
+ generic map(
+ res => 1.0e3
+ )
+ port map(
+ p1 => out_opamp1,
+ p2 => electrical_ref
+ );
+end TB_opamp;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd
new file mode 100644
index 000000000..ddb9c5e1b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd
@@ -0,0 +1,134 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE; use IEEE.std_logic_1164.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_opamp_2pole is
+end tb_opamp_2pole;
+
+architecture TB_opamp_2pole of tb_opamp_2pole is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src, op_neg2, out_opamp2 : electrical;
+ terminal out_opamp1, op_neg1, out_opamp3_res, op_neg3_res : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_sine(ideal)
+ generic map(
+ freq => 100.0,
+ amplitude => 5.0
+ )
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+
+ OP1 : entity work.opamp_2pole(dot)
+ port map(
+ in_pos => electrical_ref,
+ in_neg => op_neg1,
+ output => out_opamp1
+ );
+ R1in : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => in_src,
+ p2 => op_neg1
+ );
+ R1F : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => op_neg1,
+ p2 => out_opamp1
+ );
+ Rload1 : entity work.resistor(ideal)
+ generic map(
+ res => 1.0e3
+ )
+ port map(
+ p1 => out_opamp1,
+ p2 => electrical_ref
+ );
+ OP2 : entity work.opamp_2pole(ltf)
+ port map(
+ in_pos => electrical_ref,
+ in_neg => op_neg2,
+ output => out_opamp2
+ );
+ R2in : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => in_src,
+ p2 => op_neg2
+ );
+ R2F : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => op_neg2,
+ p2 => out_opamp2
+ );
+ Rload2 : entity work.resistor(ideal)
+ generic map(
+ res => 1.0e3
+ )
+ port map(
+ p1 => out_opamp2,
+ p2 => electrical_ref
+ );
+ OP3R : entity work.opamp_2pole_res(ltf)
+ port map(
+ in_pos => electrical_ref,
+ in_neg => op_neg3_res,
+ output => out_opamp3_res
+ );
+ Rin3R : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => in_src,
+ p2 => op_neg3_res
+ );
+ R3F : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => op_neg3_res,
+ p2 => out_opamp3_res
+ );
+ Rload3R : entity work.resistor(ideal)
+ generic map(
+ res => 1.0e3
+ )
+ port map(
+ p1 => out_opamp3_res,
+ p2 => electrical_ref
+ );
+end TB_opamp_2pole;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd
new file mode 100644
index 000000000..17a776552
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_v_source is
+
+end tb_v_source ;
+
+architecture TB_v_source of tb_v_source is
+ terminal sin_out1, sin_out2 : electrical;
+ -- Component declarations
+ -- Signal declarations
+begin
+ -- Signal assignments
+ -- Component instances
+ v1 : entity work.v_source(behavior)
+ port map(
+ pos => sin_out1,
+ neg => ELECTRICAL_REF
+ );
+
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => sin_out1,
+ p2 => electrical_ref
+ );
+ v2 : entity work.v_constant(ideal)
+ generic map(
+ level => 1.0
+ )
+ port map(
+ pos => sin_out2,
+ neg => ELECTRICAL_REF
+ );
+
+ R2 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => sin_out2,
+ p2 => electrical_ref
+ );
+end TB_v_source ;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd
new file mode 100644
index 000000000..46264eb5a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity v_source is
+ generic ( DC : voltage := 1.0; -- output peak amplitude
+ min_freq : real := 10.0; -- minimum frequency for spectral source
+ max_freq : real := 1.0e4; -- maximum frequency for spectral source
+ ac_mag : voltage := 1.0; -- AC magnitude
+ ac_phase : real := 0.0 ); -- AC phase [degree]
+ port ( terminal pos, neg : electrical );
+end entity v_source;
+
+----------------------------------------------------------------
+
+architecture behavior of v_source is
+
+ function g (freq : real) return real is
+ begin
+ if (freq > min_freq and freq < max_freq) then
+ return 1.0;
+ else
+ return 0.0;
+ end if;
+ end function g;
+
+ quantity vout across iout through pos to neg;
+ -- declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag*g(frequency),
+ math_2_pi*ac_phase/360.0;
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+ vout == DC;
+ else
+ vout == ac_spec; -- used for frequency (AC) analysis
+ end use;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd
new file mode 100644
index 000000000..c8f12e01d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity v_source is
+ generic ( DC : voltage := 1.0; -- output peak amplitude
+ ac_mag : voltage := 1.0; -- AC magnitude
+ ac_phase : real := 0.0 ); -- AC phase [degree]
+ port ( terminal pos, neg : electrical );
+end entity v_source;
+
+----------------------------------------------------------------
+
+architecture behavior of v_source is
+
+ quantity vout across iout through pos to neg;
+ -- declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+ vout == DC;
+ else
+ vout == ac_spec; -- used for frequency (AC) analysis
+ end use;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd
new file mode 100644
index 000000000..089ea0dda
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity adc is
+ port ( quantity gain : in voltage;
+ terminal a : electrical;
+ signal clk : in bit;
+ signal d_out : out bit );
+end entity adc;
+
+architecture ideal of adc is
+
+ constant ref : real := 5.0;
+ quantity v_in across a;
+ quantity v_amplified : voltage;
+
+begin
+
+ v_amplified == v_in * gain;
+
+ adc_behavior: process is
+ variable stored_d : bit;
+ begin
+ if clk = '1' then
+ if v_amplified > ref / 2.0 then
+ stored_d := '1';
+ else
+ stored_d := '0';
+ end if;
+ end if;
+ d_out <= stored_d after 5 ns;
+ wait on clk;
+ end process adc_behavior;
+
+end architecture ideal;
+
+architecture struct of adc is
+
+ terminal a_amplified, ref, half_ref: electrical;
+ quantity v_ref across i_ref through ref;
+ signal d : bit;
+
+begin
+
+ res1 : entity work.resistor(ideal)
+ port map ( ref, half_ref);
+
+ res2 : entity work.resistor(ideal)
+ port map ( half_ref, electrical_ref );
+
+ amp : entity work.vc_amp(ideal)
+ port map ( gain, a, a_amplified );
+
+ comp : entity work.comparator(ideal)
+ port map ( a_amplified, half_ref, d);
+
+ ff : entity work.d_ff(basic)
+ port map ( d, clk, d_out );
+
+ v_ref == 5.0;
+
+end architecture struct;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd
new file mode 100644
index 000000000..7c3bb4d46
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity comparator is
+ port ( terminal plus, minus : electrical;
+ signal value : out bit );
+end entity comparator;
+
+architecture ideal of comparator is
+ quantity diff across plus to minus;
+begin
+
+ comp_behavior: process is
+ begin
+ if diff > 0.0 then
+ value <= '1' after 5 ns;
+ else
+ value <= '0' after 5 ns;
+ end if;
+ wait on diff'above(0.0);
+ end process comp_behavior;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd
new file mode 100644
index 000000000..b586f69ab
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity d_ff is
+ port ( d, clk : in bit; q : out bit );
+end d_ff;
+
+architecture basic of d_ff is
+begin
+
+ ff_behavior : process is
+ begin
+ if clk = '1' then
+ q <= d after 2 ns;
+ end if;
+ wait on clk;
+ end process ff_behavior;
+
+end architecture basic;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/index-ams.txt
new file mode 100644
index 000000000..d4fed24a7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/index-ams.txt
@@ -0,0 +1,18 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 1 - Fundamental Concepts
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+adc.vhd entity adc ideal, struct Figures 1-13, 1-14, 1-17
+resistor.vhd entity resistor ideal Figure 1-16
+vc_amp.vhd entity vc_amp ideal Figure 1-16
+comparator.vhd entity comparator ideal Figure 1-16
+d_ff.vhd entity d_ff basic Figure 1-16
+propulsion.vhd entity propulsion mixed Figure 1-18
+test_bench-1.vhd entity test_bench example Figure 1-19
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_adc.vhd entity tb_adc tb_adc adc.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd
new file mode 100644
index 000000000..a96bb0dfc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.mechanical_systems.all;
+use ieee_proposed.electrical_systems.all;
+
+entity propulsion is
+ port ( signal clk, reset : in bit; -- control inputs
+ signal rpm : in natural; -- requested rpm
+ signal forward : in bit ); -- requested direction
+end entity propulsion;
+
+architecture mixed of propulsion is
+ terminal p1, p2 : electrical;
+ terminal shaft1, shaft2, shaft3 : rotational_v;
+ signal forward_gear : bit;
+ -- ...
+begin
+
+ motor : entity work.dc_motor(ideal)
+ port map ( p1, p2, shaft1 );
+
+ gear : entity work.gear_av(ideal)
+ port map ( forward_gear, shaft1, shaft2 );
+
+ intertia : entity work.inertia_av(ideal)
+ port map ( shaft2, shaft3 );
+
+ prop : entity work.propeller(ideal)
+ port map ( shaft3 );
+
+ control_section : process is
+ -- variable declarations for control_section to control voltage inputs
+ -- and gear shifting
+ -- ...
+ begin
+ -- ...
+ wait on clk, reset;
+ end process control_section;
+
+ -- ...
+
+end architecture mixed;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd
new file mode 100644
index 000000000..5f492f448
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+ port ( terminal p1, p2 : electrical );
+end entity resistor ;
+
+architecture ideal of resistor is
+ quantity v across i through p1 to p2;
+ constant resistance : real := 10000.0;
+begin
+ v == i * resistance;
+end architecture ideal;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd
new file mode 100644
index 000000000..ef2517f02
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE; use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_adc is
+end tb_adc;
+
+architecture tb_adc of tb_adc is
+ -- Component declarations
+ -- Signal declarations
+ signal clk_in : bit;
+ signal clk_in_tmp : std_logic;
+ signal dig_out1, dig_out2 : bit;
+ terminal sine_in : electrical;
+ quantity gain : real;
+begin
+ -- Signal assignments
+ clk_in <= To_bit(clk_in_tmp); -- convert std_logic to bit
+ -- Component instances
+ v1 : entity work.v_sine(ideal)
+ generic map(
+ freq => 1.0,
+ amplitude => 5.0
+ )
+ port map(
+ pos => sine_in,
+ neg => ELECTRICAL_REF
+ );
+ adc25 : entity work.adc(struct)
+ port map(
+ gain => gain,
+ a => sine_in,
+ d_out => dig_out1,
+ clk => clk_in
+ );
+ adc26 : entity work.adc(ideal)
+ port map(
+ gain => gain,
+ a => sine_in,
+ d_out => dig_out2,
+ clk => clk_in
+ );
+ clock1 : entity work.clock_duty(ideal)
+ generic map(
+ on_time => 1 ms,
+ off_time => 0.5 ms
+ )
+ port map(
+ CLOCK_OUT => clk_in_tmp
+ );
+ src1 : entity work.src_constant(ideal)
+ generic map(
+ level => 1.0
+ )
+ port map(
+ output => gain
+ );
+end tb_adc;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd
new file mode 100644
index 000000000..eff53a3e3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.mechanical_systems.all;
+use ieee_proposed.electrical_systems.all;
+
+entity test_bench is
+end entity test_bench;
+
+architecture example of test_bench is
+
+ signal clk, reset: bit;
+ signal rpm : natural;
+ signal forward : bit;
+
+begin
+ dut : entity work.propulsion(mixed)
+ port map ( clk, reset, rpm, forward );
+
+ stimulus: process is
+ begin
+ clk <= '1'; reset <= '0'; rpm <= 0; forward <= '1'; wait for 10 sec;
+ clk <= '0'; wait for 10 sec;
+ clk <= '1'; rpm <= 50; wait for 20 sec;
+ clk <= '0'; wait for 20 sec;
+ clk <= '1'; rpm <= 0; wait for 20 sec;
+ clk <= '0'; wait for 20 sec;
+ clk <= '1'; rpm <= 50; forward <= '0'; wait for 20 sec;
+ clk <= '0'; wait for 20 sec;
+ -- ...
+ wait;
+ end process stimulus;
+
+end architecture example;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd
new file mode 100644
index 000000000..5347c283f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity vc_amp is
+ port ( quantity g : in voltage;
+ terminal a, o : electrical );
+end entity vc_amp;
+
+architecture ideal of vc_amp is
+ quantity v_in across a;
+ quantity v_out across i_out through o;
+begin
+ v_out == v_in * g;
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd
new file mode 100644
index 000000000..6398be12e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+configuration architectural of computer_system is
+
+ for block_level
+
+ -- . . . -- component configurations for cpu and memory, etc
+
+ for instrumentation
+
+ for cpu_bus_monitor : bus_monitor_pkg.bus_monitor
+ use entity work.bus_monitor(general_purpose)
+ generic map ( verbose => true, dump_stats => true );
+ end for;
+
+ end for;
+
+ end for;
+
+end configuration architectural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd
new file mode 100644
index 000000000..faf4b2a9a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity nmos is
+ port ( terminal gate, source, drain : electrical );
+end entity nmos;
+
+architecture ideal of nmos is
+begin
+end architecture ideal;
+
+architecture spice_equivalent of nmos is
+begin
+end architecture spice_equivalent;
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity pmos is
+ port ( terminal gate, source, drain : electrical );
+end entity pmos;
+
+architecture ideal of pmos is
+begin
+end architecture ideal;
+
+
+
+-- code from book
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity carry_chain is
+ generic ( n : positive );
+ port ( terminal clk, c_in, c_out, vdd, vss : electrical;
+ terminal p, g : electrical_vector (1 to n) );
+end entity carry_chain;
+
+----------------------------------------------------------------
+
+architecture device_level of carry_chain is
+
+ component nmos is
+ port ( terminal gate, source, drain : electrical );
+ end component nmos;
+
+ component pmos is
+ port ( terminal gate, source, drain : electrical );
+ end component pmos;
+
+ terminal c_neg : electrical_vector(0 to n-1);
+
+begin
+
+ bit_array : for index in 0 to n generate
+ terminal clk_pulldown_drain : electrical;
+ begin
+
+ clk_pulldown : component nmos
+ port map ( clk, vss, clk_pulldown_drain );
+
+ bit_0 : if index = 0 generate
+ begin
+ clk_precharge : component pmos
+ port map ( clk, c_neg(index), vdd );
+ g_pulldown : component nmos
+ port map ( c_in, clk_pulldown_drain, c_neg(index) );
+ end generate bit_0;
+
+ middle_bit : if index /= 0 and index /= n generate
+ begin
+ clk_precharge : component pmos
+ port map ( clk, c_neg(index), vdd );
+ g_pulldown : component nmos
+ port map ( g(index), clk_pulldown_drain, c_neg(index) );
+ p_pass : component nmos
+ port map ( p(index), c_neg(index - 1), c_neg(index) );
+ end generate middle_bit;
+
+ bit_n : if index = n generate
+ begin
+ clk_precharge : component pmos
+ port map ( clk, c_out, vdd );
+ g_pulldown : component nmos
+ port map ( g(index), clk_pulldown_drain, c_out );
+ p_pass : component nmos
+ port map ( p(index), c_neg(index - 1), c_out );
+ end generate bit_n;
+
+ end generate bit_array;
+
+end architecture device_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd
new file mode 100644
index 000000000..972be8b0b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd
@@ -0,0 +1,188 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package bus_monitor_pkg is
+
+ type stats_type is record
+ ifetch_freq, write_freq, read_freq : real;
+ end record stats_type;
+
+ component bus_monitor is
+ generic ( verbose, dump_stats : boolean := false );
+ port ( mem_req, ifetch, write : in bit;
+ bus_stats : out stats_type );
+ end component bus_monitor;
+
+end package bus_monitor_pkg;
+
+
+use work.bus_monitor_pkg.all;
+
+entity bus_monitor is
+ generic ( verbose, dump_stats : boolean := false );
+ port ( mem_req, ifetch, write : in bit;
+ bus_stats : out stats_type );
+end entity bus_monitor;
+
+
+architecture general_purpose of bus_monitor is
+begin
+
+ access_monitor : process is
+
+ variable access_count, ifetch_count,
+ write_count, read_count : natural := 0;
+ use std.textio;
+ variable L : textio.line;
+
+ begin
+ wait until mem_req = '1';
+ if ifetch = '1' then
+ ifetch_count := ifetch_count + 1;
+ if verbose then
+ textio.write(L, string'("Ifetch"));
+ textio.writeline(textio.output, L);
+ end if;
+ elsif write = '1' then
+ write_count := write_count + 1;
+ if verbose then
+ textio.write(L, string'("Write"));
+ textio.writeline(textio.output, L);
+ end if;
+ else
+ read_count := read_count + 1;
+ if verbose then
+ textio.write(L, string'("Read"));
+ textio.writeline(textio.output, L);
+ end if;
+ end if;
+ access_count := access_count + 1;
+ bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count);
+ bus_stats.write_freq <= real(write_count) / real(access_count);
+ bus_stats.read_freq <= real(read_count) / real(access_count);
+ if dump_stats and access_count mod 5 = 0 then
+ textio.write(L, string'("Ifetch frequency = "));
+ textio.write(L, real(ifetch_count) / real(access_count));
+ textio.writeline(textio.output, L);
+ textio.write(L, string'("Write frequency = "));
+ textio.write(L, real(write_count) / real(access_count));
+ textio.writeline(textio.output, L);
+ textio.write(L, string'("Read frequency = "));
+ textio.write(L, real(read_count) / real(access_count));
+ textio.writeline(textio.output, L);
+ end if;
+ end process access_monitor;
+
+end architecture general_purpose;
+
+
+
+-- code from book (in text)
+
+entity computer_system is
+ generic ( instrumented : boolean := false );
+ port ( -- . . . );
+ -- not in book
+ other_port : in bit := '0' );
+ -- end not in book
+end entity computer_system;
+
+-- end code from book
+
+
+-- code from book
+
+architecture block_level of computer_system is
+
+ -- . . . -- type and component declarations for cpu and memory, etc.
+
+ signal clock : bit; -- the system clock
+ signal mem_req : bit; -- cpu access request to memory
+ signal ifetch : bit; -- indicates access is to fetch an instruction
+ signal write : bit; -- indicates access is a write
+ -- . . . -- other signal declarations
+
+begin
+
+ -- . . . -- component instances for cpu and memory, etc.
+
+ instrumentation : if instrumented generate
+
+ use work.bus_monitor_pkg;
+ signal bus_stats : bus_monitor_pkg.stats_type;
+
+ begin
+
+ cpu_bus_monitor : component bus_monitor_pkg.bus_monitor
+ port map ( mem_req, ifetch, write, bus_stats );
+
+ end generate instrumentation;
+
+ -- not in book
+
+ stimulus : process is
+ begin
+ ifetch <= '1'; write <= '0';
+ mem_req <= '1', '0' after 10 ns;
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '1'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '1'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '0'; write <= '1';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '1'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '0'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '1'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '0'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '1'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '0'; write <= '0';
+ wait for 20 ns;
+
+ wait;
+ end process stimulus;
+
+ -- end not in book
+
+end architecture block_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd
new file mode 100644
index 000000000..19a5efcbb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book (in text)
+
+entity computer_system is
+ generic ( instrumented : boolean := false );
+ port ( -- . . . );
+ -- not in book
+ other_port : in bit := '0' );
+ -- end not in book
+end entity computer_system;
+
+-- end code from book
+
+
+-- code from book
+
+architecture block_level of computer_system is
+
+ -- . . . -- type and component declarations for cpu and memory, etc
+
+ signal clock : bit; -- the system clock
+ signal mem_req : bit; -- cpu access request to memory
+ signal ifetch : bit; -- indicates access is to fetch an instruction
+ signal write : bit; -- indicates access is a write
+ -- . . . -- other signal declarations
+
+begin
+
+ -- . . . -- component instances for cpu and memory, etc
+
+ instrumentation : if instrumented generate
+
+ signal ifetch_freq, write_freq, read_freq : real := 0.0;
+
+ begin
+
+ access_monitor : process is
+ variable access_count, ifetch_count,
+ write_count, read_count : natural := 0;
+ begin
+ wait until mem_req = '1';
+ if ifetch = '1' then
+ ifetch_count := ifetch_count + 1;
+ elsif write = '1' then
+ write_count := write_count + 1;
+ else
+ read_count := read_count + 1;
+ end if;
+ access_count := access_count + 1;
+ ifetch_freq <= real(ifetch_count) / real(access_count);
+ write_freq <= real(write_count) / real(access_count);
+ read_freq <= real(read_count) / real(access_count);
+ end process access_monitor;
+
+ end generate instrumentation;
+
+ -- not in book
+
+ stimulus : process is
+ begin
+ ifetch <= '1'; write <= '0';
+ mem_req <= '1', '0' after 10 ns;
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '1'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '1'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '0'; write <= '1';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '1'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '0'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '1'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '0'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '1'; write <= '0';
+ wait for 20 ns;
+
+ mem_req <= '1', '0' after 10 ns;
+ ifetch <= '0'; write <= '0';
+ wait for 20 ns;
+
+ wait;
+ end process stimulus;
+
+ -- end not in book
+
+end architecture block_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd
new file mode 100644
index 000000000..a6c82e065
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity DRAM_4M_by_4 is
+ port ( a : in std_logic_vector(0 to 10);
+ d : inout std_logic_vector(0 to 3);
+ cs, we, ras, cas : in std_logic );
+end entity DRAM_4M_by_4;
+
+
+architecture chip_function of DRAM_4M_by_4 is
+begin
+ d <= (others => 'Z');
+end architecture chip_function;
+
+
+-- code from book
+
+library chip_lib; use chip_lib.all;
+
+configuration down_to_chips of memory_board is
+
+ for chip_level
+
+ for bank_array
+
+ for nibble_array
+
+ for a_DRAM : DRAM
+ use entity DRAM_4M_by_4(chip_function);
+ end for;
+
+ end for;
+
+ end for;
+
+ -- . . . -- configurations of other component instances
+
+ end for;
+
+end configuration down_to_chips;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd
new file mode 100644
index 000000000..4d0cfa8fa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity buf is
+ port ( a : in std_logic; y : out std_logic );
+end entity buf;
+
+
+architecture basic of buf is
+begin
+ y <= a;
+end architecture basic;
+
+
+
+
+-- code from book
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity fanout_tree is
+ generic ( height : natural );
+ port ( input : in std_logic;
+ output : out std_logic_vector (0 to 2**height - 1) );
+end entity fanout_tree;
+
+--------------------------------------------------
+
+architecture recursive of fanout_tree is
+
+begin
+
+ degenerate_tree : if height = 0 generate
+ begin
+ output(0) <= input;
+ end generate degenerate_tree;
+
+ compound_tree : if height > 0 generate
+ signal buffered_input_0, buffered_input_1 : std_logic;
+ begin
+
+ buf_0 : entity work.buf(basic)
+ port map ( a => input, y => buffered_input_0 );
+
+ subtree_0 : entity work.fanout_tree(recursive)
+ generic map ( height => height - 1 )
+ port map ( input => buffered_input_0,
+ output => output(0 to 2**(height - 1) - 1) );
+
+ buf_1 : entity work.buf(basic)
+ port map ( a => input, y => buffered_input_1 );
+
+ subtree_1 : entity work.fanout_tree(recursive)
+ generic map ( height => height - 1 )
+ port map ( input => buffered_input_1,
+ output => output(2**(height - 1) to 2**height - 1) );
+
+ end generate compound_tree;
+
+end architecture recursive;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd
new file mode 100644
index 000000000..88b11acba
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity graphics_engine is
+end entity graphics_engine;
+
+-- end not in book
+
+
+architecture behavioral of graphics_engine is
+
+ type point is array (1 to 3) of real;
+ type transformation_matrix is array (1 to 3, 1 to 3) of real;
+
+ signal p, transformed_p : point;
+ signal a : transformation_matrix;
+ signal clock : bit;
+ -- . . .
+
+begin
+
+ transform_stage : for i in 1 to 3 generate
+ begin
+
+ cross_product_transform : process is
+ variable result1, result2, result3 : real := 0.0;
+ begin
+ wait until clock = '1';
+ transformed_p(i) <= result3;
+ result3 := result2;
+ result2 := result1;
+ result1 := a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
+ end process cross_product_transform;
+
+ end generate transform_stage;
+
+ -- . . . -- other stages in the pipeline, etc
+
+ -- not in book
+
+ clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
+
+ stimulus : process is
+ begin
+ a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
+ p <= ( 10.0, 10.0, 10.0 );
+ wait until clock = '0';
+ p <= ( 20.0, 20.0, 20.0 );
+ wait until clock = '0';
+ p <= ( 30.0, 30.0, 30.0 );
+ wait until clock = '0';
+ p <= ( 40.0, 40.0, 40.0 );
+ wait until clock = '0';
+ p <= ( 50.0, 50.0, 50.0 );
+ wait until clock = '0';
+ p <= ( 60.0, 60.0, 60.0 );
+
+ wait;
+ end process stimulus;
+
+ -- end not in book
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd
new file mode 100644
index 000000000..2e9e4601e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library device_lib;
+
+configuration identical_devices of led_bar_display is
+
+ for device_level
+
+ for device_array
+
+ for limiting_resistor : resistor
+ use entity device_lib.resistor(ideal);
+ end for;
+
+ for segment_led : led
+ use entity device_lib.led(ideal);
+ end for;
+
+ end for;
+
+ end for;
+
+end configuration identical_devices;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/index-ams.txt
new file mode 100644
index 000000000..bfbcd59b6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/index-ams.txt
@@ -0,0 +1,33 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 17 - Generate Statements
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+led_bar_display.vhd entity resistor ideal --
+-- entity led ideal --
+-- entity led_bar_display device_level Figure 17-2
+resistor_pack.vhd entity resistor_pack coupled Figure 17-3
+graphics_engine.vhd entity graphics_engine behavioral Figure 17-4
+memory_board.vhd entity DRAM empty --
+-- entity memory_board chip_level Figure 17-5
+carry_chain.vhd entity nmos ideal, spice_equivalent --
+-- entity carry_chain device_level Figure 17-8
+computer_system.vhd entity computer_system block_level Section 17.2, Figure 17-9
+fanout_tree.vhd entity buf basic --
+-- entity fanout_tree recursive Figure 17-11
+computer_system-1.vhd package bus_monitor_pkg -- --
+-- entity bus_monitor general_purpose --
+-- entity computer_system block_level Figure 17-12
+architectural.vhd configuration architectural -- Figure 17-13
+identical_devices.vhd configuration identical_devices -- Figure 17-14
+down_to_chips.vhd entity DRAM_4M_by_4 chip_function --
+-- configuration down_to_chips -- Figure 17-15
+last_pass_spice.vhd configuration last_pass_spice -- Figure 17-16
+inline_01.vhd entity inline_01 test --
+-- configuration inline_01_test -- Section 17.2
+inline_02.vhd entity inline_02 test Section 17.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd
new file mode 100644
index 000000000..61342d7a9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01 is
+end entity inline_01;
+
+
+architecture test of inline_01 is
+
+ component computer_system is
+ port ( other_port : in bit := '0' );
+ end component computer_system;
+
+begin
+
+ system_under_test : component computer_system
+ port map ( other_port => open );
+
+end architecture test;
+
+
+
+configuration inline_01_test of inline_01 is
+
+ for test
+
+ -- code from book (in text)
+
+ for system_under_test : computer_system
+ use entity work.computer_system(block_level)
+ generic map ( instrumented => true )
+ -- . . .
+ -- not in book
+ ;
+ -- end not in book
+ end for;
+
+ -- end code from book
+
+ end for;
+
+end configuration inline_01_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd
new file mode 100644
index 000000000..b6f9abaa2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity inline_02 is
+end entity inline_02;
+
+
+architecture test of inline_02 is
+
+ signal unbuffered_clock : std_logic;
+ signal buffered_clock_array : std_logic_vector(0 to 7);
+
+begin
+
+ -- code from book (in text)
+
+ clock_buffer_tree : entity work.fanout_tree(recursive)
+ generic map ( height => 3 )
+ port map ( input => unbuffered_clock,
+ output => buffered_clock_array );
+
+ -- end code from book
+
+ clock_gen : process is
+ begin
+ unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
+ wait for 10 ns;
+ end process clock_gen;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd
new file mode 100644
index 000000000..dae9ff282
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library device_lib;
+
+configuration last_pass_spice of carry_chain is
+
+ for device_level
+
+ for bit_array ( 0 to n - 1 )
+
+ for bit_0
+ for all : nmos
+ use entity device_lib.nmos(ideal);
+ end for;
+ for all : pmos
+ use entity device_lib.pmos(ideal);
+ end for;
+ end for;
+
+ for middle_bit
+ for all : nmos
+ use entity device_lib.nmos(ideal);
+ end for;
+ for all : pmos
+ use entity device_lib.pmos(ideal);
+ end for;
+ end for;
+
+ end for;
+
+ for bit_array ( n )
+
+ for bit_n
+ for p_pass : nmos
+ use entity device_lib.nmos(spice_equivalent);
+ end for;
+ for others : nmos
+ use entity device_lib.nmos(ideal);
+ end for;
+ for all : pmos
+ use entity device_lib.pmos(ideal);
+ end for;
+ end for;
+
+ end for;
+
+ end for;
+
+end configuration last_pass_spice;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd
new file mode 100644
index 000000000..d17e5a1f5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- analyze into resource library device_lib
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+ port ( terminal p1, p2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+begin
+end architecture ideal;
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity led is
+ port ( terminal anode, cathode : electrical );
+end entity led;
+
+architecture ideal of led is
+begin
+end architecture ideal;
+
+
+
+-- code from book
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity led_bar_display is
+ generic ( width : positive );
+ port ( terminal anodes : electrical_vector(1 to width);
+ terminal common_cathode : electrical );
+end entity led_bar_display;
+
+----------------------------------------------------------------
+
+architecture device_level of led_bar_display is
+
+ component resistor is
+ port ( terminal p1, p2 : electrical );
+ end component resistor;
+
+ component led is
+ port ( terminal anode, cathode : electrical );
+ end component led;
+
+begin
+
+ device_array : for segment in 1 to width generate
+
+ terminal led_anode : electrical;
+
+ begin
+
+ limiting_resistor : component resistor
+ port map ( p1 => anodes(segment), p2 => led_anode );
+
+ segment_led : component led
+ port map ( anode => led_anode, cathode => common_cathode );
+
+ end generate device_array;
+
+end architecture device_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd
new file mode 100644
index 000000000..65a35f181
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity DRAM is
+ port ( a : in std_logic_vector(0 to 10);
+ d : inout std_logic_vector(0 to 3);
+ cs, we, ras, cas : in std_logic );
+end entity DRAM;
+
+
+architecture empty of DRAM is
+begin
+ d <= (others => 'Z');
+end architecture empty;
+
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity memory_board is
+end entity memory_board;
+
+-- end not in book
+
+
+architecture chip_level of memory_board is
+
+ component DRAM is
+ port ( a : in std_logic_vector(0 to 10);
+ d : inout std_logic_vector(0 to 3);
+ cs, we, ras, cas : in std_logic );
+ end component DRAM;
+
+ signal buffered_address : std_logic_vector(0 to 10);
+ signal DRAM_data : std_logic_vector(0 to 31);
+ signal bank_select : std_logic_vector(0 to 3);
+ signal buffered_we, buffered_ras, buffered_cas : std_logic;
+
+ -- . . . -- other declarations
+
+begin
+
+ bank_array : for bank_index in 0 to 3 generate
+ begin
+
+ nibble_array : for nibble_index in 0 to 7 generate
+
+ constant data_lo : natural := nibble_index * 4;
+ constant data_hi : natural := nibble_index * 4 + 3;
+
+ begin
+
+ a_DRAM : component DRAM
+ port map ( a => buffered_address,
+ d => DRAM_data(data_lo to data_hi),
+ cs => bank_select(bank_index),
+ we => buffered_we,
+ ras => buffered_ras,
+ cas => buffered_cas );
+
+ end generate nibble_array;
+
+ end generate bank_array;
+
+ -- . . . -- other component instances, etc
+
+ -- not in book
+
+ buffered_address <= "01010101010";
+ DRAM_data <= X"01234567";
+
+ -- end not in book
+
+end architecture chip_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/resistor_pack.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/resistor_pack.vhd
new file mode 100644
index 000000000..42dec93f6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/resistor_pack.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all, ieee_proposed.thermal_systems.all;
+
+entity resistor_pack is
+ generic ( resistances_at_298K : real_vector;
+ temperature_coeff : real := 0.0 );
+ port ( terminal p1, p2 : electrical_vector(1 to resistances_at_298K'length);
+ quantity package_temp : in temperature );
+end entity resistor_pack;
+
+----------------------------------------------------------------
+
+architecture coupled of resistor_pack is
+
+ quantity v across i through p1 to p2;
+ quantity effective_resistance : real_vector(1 to resistances_at_298K'length);
+
+begin
+
+ resistor_array : for index in 1 to resistances_at_298K'length generate
+
+ effective_resistance(index)
+ == resistances_at_298K(index)
+ + ( package_temp - 298.0 ) * temperature_coeff;
+
+ v(index ) == i(index) * effective_resistance(index);
+
+ end generate resistor_array;
+
+end architecture coupled;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/control_unit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/control_unit.vhd
new file mode 100644
index 000000000..1fda52aaf
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/control_unit.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book
+
+entity control_unit is
+
+ generic ( Tpd_clk_out, Tpw_clk : delay_length;
+ debug : boolean := false );
+
+ port ( clk : in bit;
+ ready : in bit;
+ control1, control2 : out bit );
+
+end entity control_unit;
+
+-- end code from book
+
+
+
+architecture test of control_unit is
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/index-ams.txt
new file mode 100644
index 000000000..7be1d3678
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/index-ams.txt
@@ -0,0 +1,23 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 9 - Generic Constants
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+control_unit.vhd entity control_unit test Figure 12-1
+timer.vhd entity timer behavioral Figure 12-2
+reg.vhd entity reg behavioral Figure 12-3
+multiple_opamp.vhd entity multiple_opamp ideal Figure 12-4
+inline_01.vhd entity inline_01 test Section 12.1
+inline_02a.vhd entity resistor simple Section 12.1
+inline_03.vhd entity inline_03 test Section 12.1
+inline_05a.vhd entity inline_05a test Section 12.1
+inline_06.vhd entity inline_06 test Section 12.2
+inline_07.vhd entity inline_07 test Section 12.2
+inline_08.vhd entity inline_08 test Section 12.2
+inline_09a.vhd entity inline_09a test Section 12.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_timer_w_stim.vhd entity tb_timer_w_stim TB_timer_w_stim timer.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_01.vhd
new file mode 100644
index 000000000..b3ae86af1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_01.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book
+
+entity and2 is
+ generic ( Tpd : time );
+ port ( a, b : in bit; y : out bit );
+end entity and2;
+
+
+architecture simple of and2 is
+begin
+
+ and2_function :
+ y <= a and b after Tpd;
+
+end architecture simple;
+
+-- end code from book
+
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+library util; use util.stimulus_generators.all;
+
+architecture test of inline_01 is
+
+ signal a1, b1, sig1, sig2, sig_out : bit;
+ signal test_vector : bit_vector(1 to 3);
+
+begin
+
+ -- code from book
+
+ gate1 : entity work.and2(simple)
+ generic map ( Tpd => 2 ns )
+ port map ( a => sig1, b => sig2, y => sig_out );
+
+ gate2 : entity work.and2(simple)
+ generic map ( Tpd => 3 ns )
+ port map ( a => a1, b => b1, y => sig1 );
+
+ -- end code from book
+
+ stimulus : all_possible_values ( bv => test_vector,
+ delay_between_values => 10 ns );
+
+ (sig2, a1, b1) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_02a.vhd
new file mode 100644
index 000000000..fa207c9b0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_02a.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+-- code from book
+
+entity resistor is
+ generic ( resistance : real );
+ port ( terminal pos, neg : electrical );
+end entity resistor;
+
+architecture simple of resistor is
+ quantity v across i through pos to neg;
+begin
+ v == i * resistance;
+end architecture simple;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_03.vhd
new file mode 100644
index 000000000..a86e7af51
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_03.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_03 is
+end entity inline_03;
+
+
+
+architecture test of inline_03 is
+
+ signal clk, ready : bit;
+
+begin
+
+ dut1 : entity work.control_unit
+ -- code from book (in text)
+ generic map ( 200 ps, 1500 ps, false )
+ -- end code from book
+ port map ( clk, ready, open, open );
+
+ dut2 : entity work.control_unit
+ -- code from book (in text)
+ generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
+ -- end code from book
+ port map ( clk, ready, open, open );
+
+ dut3 : entity work.control_unit
+ -- code from book (in text)
+ generic map ( 200 ps, 1500 ps, debug => open )
+ -- end code from book
+ port map ( clk, ready, open, open );
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_05a.vhd
new file mode 100644
index 000000000..54ac662bb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_05a.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_05a is
+end entity inline_05a;
+
+
+
+architecture test of inline_05a is
+
+ signal start_n, reset, time_out : std_ulogic;
+ terminal interval_rc : electrical;
+
+begin
+
+ -- code from book (in text)
+
+ interval_timer : entity work.timer(behavioral)
+ generic map ( threshold => 2.5,
+ clamp_on_resistance => 0.01,
+ clamp_off_resistance => 10.0E+6 )
+ port map ( trigger_n => start_n, reset => reset, q => time_out,
+ rc_ext => interval_rc );
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd
new file mode 100644
index 000000000..baf7405e7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book
+
+entity reg is
+ port ( d : in bit_vector; q : out bit_vector; -- . . . );
+ -- not in book
+ other_port : in bit := '0' );
+ -- end not in book
+end entity reg;
+
+-- end code from book
+
+
+architecture test of reg is
+begin
+ q <= d;
+end architecture test;
+
+
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+ -- code from book
+
+ signal small_data : bit_vector(0 to 7);
+ signal large_data : bit_vector(0 to 15);
+ -- . . .
+
+ -- end code from book
+
+
+begin
+
+ -- code from book
+
+ problem_reg : entity work.reg
+ port map ( d => small_data, q => large_data, -- . . . );
+ -- not in book
+ other_port => open );
+ -- end not in book
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_07.vhd
new file mode 100644
index 000000000..c59b06cd1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_07.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book
+
+entity reg is
+ generic ( width : positive );
+ port ( d : in bit_vector(0 to width - 1);
+ q : out bit_vector(0 to width - 1);
+ -- . . . );
+ -- not in book
+ other_port : in bit := '0' );
+ -- end not in book
+end entity reg;
+
+-- end code from book
+
+
+architecture test of reg is
+begin
+ q <= d;
+end architecture test;
+
+
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_07 is
+
+ constant bus_size : positive := 16;
+
+ -- code from book
+
+ signal in_data, out_data : bit_vector(0 to bus_size - 1);
+ -- . . .
+
+ -- end code from book
+
+
+begin
+
+ -- code from book
+
+ ok_reg : entity work.reg
+ generic map ( width => bus_size )
+ port map ( d => in_data, q => out_data, -- . . . );
+ -- not in book
+ other_port => open );
+ -- end not in book
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_08.vhd
new file mode 100644
index 000000000..b1fea6421
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_08.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_08 is
+end entity inline_08;
+
+
+architecture test of inline_08 is
+
+ -- code from book
+
+ subtype state_vector is bit_vector(1 to 5);
+
+ -- end code from book
+
+ signal clk, reset : bit := '0';
+ signal word_in, word_out : bit_vector(0 to 31);
+ signal state_in, state_out : state_vector;
+
+begin
+
+ -- code from book
+
+ word_reg : entity work.reg(behavioral)
+ generic map ( width => 32 )
+ port map ( -- . . . );
+ -- not in book
+ d => word_in, q => word_out, clk => clk, reset => reset );
+ -- end not in book
+
+ state_reg : entity work.reg(behavioral)
+ generic map ( width => state_vector'length )
+ port map ( -- . . . );
+ -- not in book
+ d => state_in, q => state_out, clk => clk, reset => reset );
+
+ -- end code from book
+
+ clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+
+ reset_gen : reset <= '1' after 80 ns, '0' after 105 ns;
+
+ stimulus_word : word_in <= X"11111111" after 25 ns,
+ X"22222222" after 65 ns,
+ X"33333333" after 85 ns,
+ X"44444444" after 125 ns;
+
+ stimulus_state : state_in <= "00001" after 25 ns,
+ "00010" after 65 ns,
+ "00011" after 85 ns,
+ "00100" after 125 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_09a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_09a.vhd
new file mode 100644
index 000000000..3ef59fb28
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_09a.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity inline_09a is
+
+end entity inline_09a;
+
+
+architecture test of inline_09a is
+
+ -- code from book
+
+ constant num_sensors : positive := 8;
+ terminal sensors_raw,
+ sensors_buffered : electrical_vector(num_sensors - 1 downto 0);
+ -- ...
+
+ -- end code from book
+
+begin
+
+ -- code from book
+
+ buf_amps : entity work.multiple_opamp(ideal)
+ generic map ( size => num_sensors,
+ gains => real_vector'(num_sensors - 1 downto 0 => 1.0) )
+ port map ( sensors_raw, sensors_buffered );
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/multiple_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/multiple_opamp.vhd
new file mode 100644
index 000000000..ff3167bd5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/multiple_opamp.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity multiple_opamp is
+ generic ( size : positive;
+ gains : real_vector );
+ port ( terminal inputs, outputs : electrical_vector(1 to size) );
+end entity multiple_opamp;
+
+----------------------------------------------------------------
+
+architecture ideal of multiple_opamp is
+
+ quantity v_in across i_in through inputs to electrical_ref;
+ quantity v_out across outputs to electrical_ref;
+ alias gains_alias : real_vector(1 to size) is gains;
+
+begin
+
+ assert gains'length = size
+ report "gains vector size differs from input/output size";
+
+ amplify : procedural is
+ begin
+ for index in 1 to size loop
+ v_out(index) := v_in(index) * gains_alias(index);
+ end loop;
+ end procedural amplify;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd
new file mode 100644
index 000000000..181064e41
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity reg is
+ generic ( width : positive );
+ port ( d : in bit_vector(0 to width - 1);
+ q : out bit_vector(0 to width - 1);
+ clk, reset : in bit );
+end entity reg;
+
+--------------------------------------------------
+
+architecture behavioral of reg is
+begin
+
+ behavior : process (clk, reset) is
+ constant zero : bit_vector(0 to width - 1) := (others => '0');
+ begin
+ if reset = '1' then
+ q <= zero;
+ elsif clk'event and clk = '1' then
+ q <= d;
+ end if;
+ end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd
new file mode 100644
index 000000000..21d4b38a0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+library IEEE; use IEEE.std_logic_1164.all;
+
+entity tb_timer_w_stim is
+
+end tb_timer_w_stim;
+
+architecture TB_timer_w_stim of tb_timer_w_stim is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src, rc_ext : electrical;
+ signal trig, rst : std_ulogic;
+ signal tim_out : std_ulogic;
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_constant(ideal)
+ generic map(
+ level => 5.0
+ )
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+ R1 : entity work.resistor(simple)
+ generic map(
+ resistance => 10.0e3
+ )
+ port map(
+ pos => in_src,
+ neg => rc_ext
+ );
+ C1 : entity work.capacitor(ideal)
+ generic map(
+ cap => 10.0e-6
+ )
+ port map(
+ p1 => rc_ext,
+ p2 => electrical_ref
+ );
+ timer1 : entity work.timer(behavioral)
+ generic map(
+ threshold => 2.0,
+ clamp_on_resistance => 1.0e-3,
+ clamp_off_resistance => 1.0e6
+ )
+ port map(
+ trigger_n => trig,
+ reset => rst,
+ q => tim_out,
+ rc_ext => rc_ext
+ );
+ -- rst
+ P_rst :
+ process
+ begin
+
+ wait for 0.000 ns; rst <= '1';
+
+ wait for 1.000 ms; rst <= '0';
+
+ wait for 100.000 ms; rst <= '1';
+
+ wait for 1.000 ms; rst <= '0';
+
+ wait;
+ end process;
+
+ -- trig
+ P_trig :
+ process
+ begin
+ wait for 0.0 ns; trig <= '0';
+
+ wait for 5.000 ms; trig <= '1';
+
+ wait for 1.0 ms; trig <= '0';
+
+ wait for 1.0 ms; trig <= '1';
+
+ wait for 40.0 ms; trig <= '1';
+
+ wait for 1.0 ms; trig <= '0';
+
+ wait for 1.0 ms; trig <= '1';
+
+ wait for 40.0 ms; trig <= '1';
+
+ wait for 1.0 ms; trig <= '0';
+
+ wait for 1.0 ms; trig <= '1';
+ wait;
+ end process;
+end TB_timer_w_stim;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/timer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/timer.vhd
new file mode 100644
index 000000000..793a9e504
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/timer.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity timer is
+ generic ( threshold : real;
+ clamp_on_resistance, clamp_off_resistance : real );
+ port ( signal trigger_n, reset : in std_ulogic; signal q : out std_ulogic;
+ terminal rc_ext : electrical );
+end entity timer;
+
+----------------------------------------------------------------
+
+architecture behavioral of timer is
+
+ quantity v_rc_ext across i_clamp through rc_ext to electrical_ref;
+ signal q_n : std_ulogic := '1';
+
+begin
+
+ if q_n = '1' use
+ i_clamp == v_rc_ext / clamp_on_resistance;
+ else
+ i_clamp == v_rc_ext / clamp_off_resistance;
+ end use;
+
+ timer_state : process ( trigger_n, reset, v_rc_ext'above(threshold) ) is
+ begin
+ if reset = '1' or reset = 'H' or v_rc_ext > threshold then
+ q <= '0'; q_n <= '1';
+ elsif trigger_n = '0' or trigger_n = 'L' then
+ q <= '1'; q_n <= '0';
+ end if;
+ end process timer_state;
+
+ break on q_n;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd
new file mode 100644
index 000000000..c4707cdcb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity circuit is
+ generic ( inpad_delay, outpad_delay : delay_length );
+ port ( in1, in2, in3 : in bit; out1, out2 : out bit );
+end entity circuit;
+
+--------------------------------------------------
+
+architecture with_pad_delays of circuit is
+
+ component subcircuit is
+ port ( a, b : in bit; y1, y2 : out bit );
+ end component subcircuit;
+
+ signal delayed_in1, delayed_in2, delayed_in3 : bit;
+ signal undelayed_out1, undelayed_out2 : bit;
+
+begin
+
+ input_delays : block is
+ begin
+ delayed_in1 <= in1 after inpad_delay;
+ delayed_in2 <= in2 after inpad_delay;
+ delayed_in3 <= in3 after inpad_delay;
+ end block input_delays;
+
+ functionality : block is
+ signal intermediate : bit;
+ begin
+ cell1 : component subcircuit
+ port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate );
+ cell2 : component subcircuit
+ port map ( intermediate, delayed_in3, undelayed_out2, open );
+ end block functionality;
+
+ output_delays : block is
+ begin
+ out1 <= undelayed_out1 after outpad_delay;
+ out2 <= undelayed_out2 after outpad_delay;
+ end block output_delays;
+
+end architecture with_pad_delays;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system-1.vhd
new file mode 100644
index 000000000..dded8af1b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system-1.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity computer_system_abstract is
+end entity computer_system_abstract;
+
+
+-- code from book
+
+architecture abstract of computer_system_abstract is
+
+ -- not in book
+
+ subtype word is bit_vector(31 downto 0);
+ type word_vector is array (natural range <>) of word;
+
+ function resolve_word ( drivers : word_vector ) return word is
+ begin
+ if drivers'length > 0 then
+ return drivers(drivers'left);
+ else
+ return X"00000000";
+ end if;
+ end function resolve_word;
+
+ -- end not in book
+
+ -- . . .
+
+ signal address_bus : resolve_word word bus;
+ signal hold_req : bit;
+ -- . . .
+
+ -- not in book
+ signal clk : bit := '0';
+ -- end not in book
+
+begin
+
+ cpu : block is
+
+ signal guard : boolean := false;
+ signal cpu_internal_address : word;
+ -- . . .
+
+ begin
+
+ cpu_address_driver:
+ address_bus <= guarded cpu_internal_address;
+
+ -- . . . -- other bus drivers
+
+ controller : process is
+ -- . . .
+ begin
+ -- . . .
+ -- . . . -- determine when to disable cpu bus drivers
+ guard <= false;
+ wait on clk until hold_req = '0' and clk = '1';
+ guard <= true; -- reenable cpu bus drivers
+ -- . . .
+ -- not in book
+ wait until clk = '1';
+ -- end not in book
+ end process controller;
+
+ -- . . . -- cpu data-path processes
+
+ -- not in book
+ cpu_internal_address <= X"11111111";
+ -- end not in book
+
+ end block cpu;
+
+ -- . . . -- blocks for DMA and other modules
+
+ -- not in book
+ clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+ -- end not in book
+
+end architecture abstract;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system.vhd
new file mode 100644
index 000000000..8b71df4f9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+architecture top_level of computer_system is
+
+ function resolve_bits ( bits : bit_vector ) return bit is
+ variable result : bit := '0';
+ begin
+ for index in bits'range loop
+ result := result or bits(index);
+ exit when result = '1';
+ end loop;
+ return result;
+ end function resolve_bits;
+
+ signal write_en : resolve_bits bit bus;
+ -- . . .
+
+ -- not in book
+ constant Tpd : delay_length := 2 ns;
+ signal clock, hold_req : bit := '0';
+ -- end not in book
+
+begin
+
+ CPU : process is
+ -- . . .
+ begin
+ write_en <= '0' after Tpd;
+ -- . . .
+ loop
+ wait until clock = '1';
+ if hold_req = '1' then
+ write_en <= null after Tpd;
+ wait on clock until clock = '1' and hold_req = '0';
+ write_en <= '0' after Tpd;
+ end if;
+ -- . . .
+ end loop;
+ end process CPU;
+
+ -- . . .
+
+ -- not in book
+
+ clock_gen : clock <= '1' after 5 ns, '0' after 10 ns when clock = '0';
+
+ stimulus : hold_req <= '1' after 40 ns, '0' after 80 ns;
+
+ process is
+ begin
+ write_en <= null, '1' after 50 ns, '0' after 60 ns, null after 70 ns;
+ wait;
+ end process;
+
+ -- end not in book
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/data_logger.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/data_logger.vhd
new file mode 100644
index 000000000..22a42dfb9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/data_logger.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity data_logger is
+end entity data_logger;
+
+
+-- code from book
+
+architecture high_level of data_logger is
+
+ subtype byte is bit_vector(7 downto 0);
+
+ type byte_array is array (integer range <>) of byte;
+
+ function resolver ( bytes : byte_array ) return byte is
+ begin
+ if bytes'length > 0 then
+ return bytes( bytes'left );
+ else
+ return X"00";
+ end if;
+ end function resolver;
+
+ subtype resolved_byte is resolver byte;
+
+ procedure reg ( signal clock, out_enable : in bit;
+ signal d : in byte;
+ signal q : out resolved_byte ) is
+ variable stored_byte : byte;
+ begin
+ loop
+ if clock = '1' then
+ stored_byte := d;
+ end if;
+ if out_enable = '1' then
+ q <= stored_byte;
+ else
+ q <= null;
+ end if;
+ wait on clock, out_enable, d;
+ end loop;
+ end procedure reg;
+
+ signal data_bus : resolved_byte bus;
+ -- . . .
+
+ -- not in book
+ signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0';
+ signal port_a, port_b : byte := X"00";
+ -- end not in book
+
+begin
+
+ a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus);
+
+ b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus);
+
+ -- . . .
+
+ -- not in book
+
+ stimulus : process is
+ begin
+ port_a <= X"11"; a_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
+ a_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
+ port_b <= X"21"; b_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
+ b_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
+ a_reg_read <= '1', '0' after 5 ns;
+ b_reg_read <= '1', '0' after 5 ns;
+
+ wait;
+ end process stimulus;
+
+ -- end not in book
+
+end architecture high_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/example_entity.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/example_entity.vhd
new file mode 100644
index 000000000..819d6e43b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/example_entity.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity example_entity is
+end entity example_entity;
+
+-- end not in book
+
+
+architecture contrived of example_entity is
+
+ constant sig_width : positive := 16;
+ signal s1, s2, s3 : bit_vector (0 to sig_width - 1);
+ signal sel : bit;
+ -- . . .
+
+begin
+
+ mux : block is
+ generic ( width : positive );
+ generic map ( width => sig_width );
+ port ( d0, d1 : in bit_vector(0 to width - 1);
+ y : out bit_vector(0 to width - 1);
+ sel : in bit);
+ port map ( d0 => s1, d1=> s2, y => s3, sel => sel );
+
+ constant zero : bit_vector(0 to width - 1) := ( others => '0' );
+ signal gated_d0, gated_d1 : bit_vector(0 to width - 1);
+
+ begin
+ gated_d0 <= d0 when sel = '0' else zero;
+ gated_d1 <= d1 when sel = '1' else zero;
+ y <= gated_d0 or gated_d1;
+ end block mux;
+
+ -- . . .
+
+ -- not in book
+
+ stimulus : process is
+ begin
+ s1 <= X"1111"; s2 <= X"2222"; sel <= '0'; wait for 10 ns;
+ s1 <= X"0101"; wait for 10 ns;
+ s2 <= X"0202"; wait for 10 ns;
+ sel <= '1'; wait for 10 ns;
+ s1 <= X"0001"; wait for 10 ns;
+ s2 <= X"0002"; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+ -- end not in book
+
+end architecture contrived;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/full.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/full.vhd
new file mode 100644
index 000000000..bb46694b4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/full.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity real_subcircuit is
+ port ( a, b : in bit; y1, y2 : out bit );
+end entity real_subcircuit;
+
+
+architecture basic of real_subcircuit is
+begin
+ y1 <= a and b after 10 ns;
+ y2 <= a nand b after 10 ns;
+end architecture basic;
+
+
+
+-- code from book
+
+configuration full of circuit is
+
+ for with_pad_delays -- configure the architecture
+
+ for functionality -- configure the block
+
+ for all : subcircuit
+ use entity work.real_subcircuit(basic);
+ end for;
+
+ end for;
+
+ end for;
+
+end configuration full;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/index-ams.txt
new file mode 100644
index 000000000..fa600e31d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/index-ams.txt
@@ -0,0 +1,34 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 19 - Guards and Blocks
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+computer_system.vhd entity computer_system top_level Figure 19-1
+processor.vhd entity processor rtl Figure 19-2
+resolve.vhd package resolve body Section 19.1, Figure 19-4
+tri_state_reg.vhd entity tri_state_reg behavioral Section 19.1, Figure 19-5
+data_logger.vhd entity data_logger high_level Figure 19-6
+reg_read_selector.vhd entity reg_read_selector test Figure 19-7
+processor_node.vhd entity processor_node dataflow Figure 19-8
+latch.vhd entity latch behavioral Figure 19-9
+computer_system-1.vhd entity computer_system_abstract abstract Figure 19-10
+sensor.vhd entity sensor detailed_timing Figures 19-12, 19-13
+example_entity.vhd entity example_entity contrived Figure 19-14
+circuit.vhd entity circuit with_pad_delays Figure 19-15
+full.vhd entity real_subcircuit basic --
+-- configuration full -- Figure 19-16
+inline_01.vhd entity inline_01 test Section 19.1
+inline_02.vhd entity inline_02 test Section 19.1
+inline_03.vhd entity inline_03 test Section 19.1
+inline_04.vhd entity inline_04 test Section 19.2
+inline_05.vhd entity inline_05 test Section 19.2
+inline_06.vhd entity inline_06 test Section 19.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_tri_state_reg.vhd entity tb_tri_state_reg test tri_state_reg.vhd
+tb_latch.vhd entity tb_latch test latch.vhd
+tb_sensor.vhd entity tb_sensor tb_sensor sensor.vhd
+tb_full.vhd entity tb_full test full.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_01.vhd
new file mode 100644
index 000000000..27b98a66e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_01.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+
+ function pulled_up ( drivers : bit_vector ) return bit is
+ begin
+ for index in drivers'range loop
+ if drivers(index) = '0' then
+ return '0';
+ end if;
+ end loop;
+ return '1';
+ end function pulled_up;
+
+ type state_type is (init_state, state1, state2, state3);
+ type state_vector is array (integer range <>) of state_type;
+
+ function resolve_state ( drivers : state_vector ) return state_type is
+ begin
+ return drivers(drivers'left);
+ end function resolve_state;
+
+
+ -- code from book:
+
+ signal interrupt_request : pulled_up bit bus;
+
+ signal stored_state : resolve_state state_type register := init_state;
+
+ -- end of code from book
+
+begin
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_02.vhd
new file mode 100644
index 000000000..1a2c612bf
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_02.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+
+ -- code from book:
+
+ subtype word is bit_vector(0 to 31);
+ type word_array is array (integer range <>) of word;
+
+ function resolve_words ( words : word_array ) return word;
+
+ signal s : resolve_words word bus;
+
+ -- end of code from book
+
+ function resolve_words ( words : word_array ) return word is
+ begin
+ if words'length > 0 then
+ return words(words'left);
+ else
+ return X"00000000";
+ end if;
+ end function resolve_words;
+
+ constant T_delay : delay_length := 2 ns;
+
+begin
+
+
+ process is
+ begin
+
+ -- code from book (should fail)
+
+ s(0 to 15) <= X"003F" after T_delay;
+ s(16 to 31) <= null after T_delay;
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_03.vhd
new file mode 100644
index 000000000..a1498abec
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_03.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+
+ function pulled_up ( drivers : bit_vector ) return bit is
+ begin
+ for index in drivers'range loop
+ if drivers(index) = '0' then
+ return '0';
+ end if;
+ end loop;
+ return '1';
+ end function pulled_up;
+
+ signal s : pulled_up bit bus;
+
+begin
+
+
+ process is
+ begin
+
+ s <= '1' after 11 ns, '0' after 16 ns, '1' after 18 ns,
+ null after 19 ns, '0' after 25 ns;
+ wait for 10 ns;
+
+ -- code from book:
+
+ s <= reject 3 ns inertial null after 10 ns;
+
+ -- end of code from book
+
+ wait;
+ end process;
+
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_04.vhd
new file mode 100644
index 000000000..eefda275e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_04.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_04 is
+
+end entity inline_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04 is
+
+ subtype word is bit_vector(0 to 31);
+ type word_array is array (integer range <>) of word;
+
+ function resolve_words ( words : word_array ) return word is
+ begin
+ if words'length > 0 then
+ return words(words'left);
+ else
+ return X"00000000";
+ end if;
+ end function resolve_words;
+
+ subtype resolved_word is resolve_words word;
+
+ -- code from book:
+
+ signal memory_data_bus : resolved_word bus;
+ disconnect memory_data_bus : resolved_word after 3 ns;
+
+ -- end of code from book
+
+ signal mem_sel, mem_write : boolean;
+ signal cache_data_bus : word;
+
+begin
+
+
+ -- code from book:
+
+ mem_write_buffer : block (mem_sel and mem_write) is
+ begin
+ memory_data_bus <=
+ guarded reject 2 ns inertial cache_data_bus after 4 ns;
+ end block mem_write_buffer;
+
+ -- end of code from book
+
+ stimulus : process is
+ begin
+ cache_data_bus <= X"DDDDDDDD";
+ wait for 10 ns;
+ mem_sel <= true; mem_write <= true;
+ wait for 10 ns;
+ cache_data_bus <= X"AAAAAAAA";
+ wait for 10 ns;
+ mem_sel <= false; mem_write <= false;
+ wait for 10 ns;
+ cache_data_bus <= X"11111111";
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_05.vhd
new file mode 100644
index 000000000..578845470
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_05.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+architecture test of inline_05 is
+
+ subtype word is bit_vector(0 to 31);
+ type word_array is array (integer range <>) of word;
+
+ function resolve_words ( words : word_array ) return word is
+ begin
+ if words'length > 0 then
+ return words(words'left);
+ else
+ return X"00000000";
+ end if;
+ end function resolve_words;
+
+ subtype resolved_word is resolve_words word;
+
+ -- code from book:
+
+ signal source_bus_1, source_bus_2 : resolved_word bus;
+ signal address_bus : resolved_word bus;
+
+ disconnect all : resolved_word after 2 ns;
+
+ -- end of code from book
+
+ signal s : word;
+ signal g : boolean;
+
+begin
+
+
+ b : block (g) is
+ begin
+ source_bus_1 <= guarded s after 4 ns;
+ source_bus_2 <= guarded s after 4 ns;
+ address_bus <= guarded s after 4 ns;
+ end block b;
+
+ stimulus : process is
+ begin
+ s <= X"DDDDDDDD";
+ wait for 10 ns;
+ g <= true;
+ wait for 10 ns;
+ s <= X"AAAAAAAA";
+ wait for 10 ns;
+ g <= false;
+ wait for 10 ns;
+ s <= X"11111111";
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_06.vhd
new file mode 100644
index 000000000..00534b5c0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_06.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+ subtype word is bit_vector(0 to 31);
+ type word_array is array (integer range <>) of word;
+
+ function resolve_words ( words : word_array ) return word is
+ begin
+ if words'length > 0 then
+ return words(words'left);
+ else
+ return X"00000000";
+ end if;
+ end function resolve_words;
+
+ subtype resolved_word is resolve_words word;
+
+ signal source_bus_1, source_bus_2 : resolved_word bus;
+ signal address_bus : resolved_word bus;
+
+ -- code from book:
+
+ disconnect address_bus : resolved_word after 3 ns;
+
+ disconnect others : resolved_word after 2 ns;
+
+ -- end of code from book
+
+ signal s : word;
+ signal g : boolean;
+
+begin
+
+
+ b : block (g) is
+ begin
+ source_bus_1 <= guarded s after 4 ns;
+ source_bus_2 <= guarded s after 4 ns;
+ address_bus <= guarded s after 4 ns;
+ end block b;
+
+ stimulus : process is
+ begin
+ s <= X"DDDDDDDD";
+ wait for 10 ns;
+ g <= true;
+ wait for 10 ns;
+ s <= X"AAAAAAAA";
+ wait for 10 ns;
+ g <= false;
+ wait for 10 ns;
+ s <= X"11111111";
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/latch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/latch.vhd
new file mode 100644
index 000000000..aaceb5c4e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/latch.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity latch is
+ generic ( width : positive );
+ port ( enable : in bit;
+ d : in bit_vector(0 to width - 1);
+ q : out bit_vector(0 to width - 1) );
+end entity latch;
+
+--------------------------------------------------
+
+architecture behavioral of latch is
+begin
+
+ transfer_control : block ( enable = '1' ) is
+ begin
+ q <= guarded d;
+ end block transfer_control;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd
new file mode 100644
index 000000000..412f9e368
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity processor is
+end entity processor;
+
+
+
+-- code from book
+
+architecture rtl of processor is
+
+ subtype word is bit_vector(0 to 31);
+ type word_vector is array (natural range <>) of word;
+
+ function resolve_unique ( drivers : word_vector ) return word is
+ begin
+ return drivers(drivers'left);
+ end function resolve_unique;
+
+ signal source1, source2 : resolve_unique word register;
+ -- . . .
+
+ -- not in book
+
+ type alu_op_type is (pass1, pass2, add, subtract);
+
+ procedure perform_alu_op ( signal alu_opcode : in alu_op_type;
+ signal source1, source2 : in word;
+ signal destination : out word;
+ constant ignored : in integer := 0 ) is
+ begin
+ null;
+ end procedure perform_alu_op;
+
+ signal phase1, source1_reg_out_en,other_signal : bit;
+ signal alu_opcode : alu_op_type;
+ signal destination : word;
+
+ -- end not in book
+
+begin
+
+ source1_reg : process (phase1, source1_reg_out_en, -- . . .) is
+ -- not in book
+ other_signal) is
+ -- end not in book
+ variable stored_value : word;
+ begin
+ -- . . .
+ if source1_reg_out_en = '1' and phase1 = '1' then
+ source1 <= stored_value;
+ -- not in book
+ stored_value := not stored_value;
+ -- end not in book
+ else
+ source1 <= null;
+ end if;
+ end process source1_reg;
+
+ alu : perform_alu_op ( alu_opcode, source1, source2, destination, -- . . . );
+ -- not in book
+ open );
+ -- end not in book
+
+ -- . . .
+
+ -- not in book
+
+ process is
+ begin
+ wait for 10 ns;
+ source1_reg_out_en <= '1';
+ phase1 <= '1', '0' after 10 ns;
+ wait for 20 ns;
+ source1_reg_out_en <= '1';
+ phase1 <= '1', '0' after 10 ns;
+ wait;
+ end process;
+
+ -- end not in book
+
+end architecture rtl;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor_node.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor_node.vhd
new file mode 100644
index 000000000..20c782792
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor_node.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity processor_node is
+end entity processor_node;
+
+
+-- code from book
+
+architecture dataflow of processor_node is
+
+ -- not in book
+
+ subtype word is bit_vector(31 downto 0);
+ type word_vector is array (natural range <>) of word;
+
+ function resolve_unique ( drivers : word_vector ) return word is
+ begin
+ if drivers'length > 0 then
+ return drivers(drivers'left);
+ else
+ return X"00000000";
+ end if;
+ end function resolve_unique;
+
+ -- end not in book
+
+ signal address_bus : resolve_unique word bus;
+ -- . . .
+
+ -- not in book
+ signal cache_miss, dirty, replace_section,
+ snoop_hit, flag_update : bit := '0';
+ constant tag_section0 : bit_vector(11 downto 0) := X"000";
+ constant tag_section1 : bit_vector(11 downto 0) := X"001";
+ constant set_index : bit_vector(15 downto 0) := X"6666";
+ constant snoop_address : word := X"88888888";
+ -- end not in book
+
+begin
+
+ cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is
+ begin
+ address_bus <= guarded
+ tag_section0 & set_index & B"0000" when replace_section = '0' else
+ tag_section1 & set_index & B"0000";
+ end block cache_to_address_buffer;
+
+ snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is
+ begin
+ address_bus <= guarded snoop_address(31 downto 4) & B"0000";
+ end block snoop_to_address_buffer;
+
+ -- . . .
+
+ -- not in book
+
+ stimulus : process is
+ begin
+ wait for 10 ns;
+ dirty <= '0'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
+ dirty <= '1'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
+ replace_section <= '1';
+ cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
+ flag_update <= '0'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
+ flag_update <= '1'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+ -- end not in book
+
+end architecture dataflow;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd
new file mode 100644
index 000000000..569fe0384
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity reg_read_selector is
+end entity reg_read_selector;
+
+
+architecture test of reg_read_selector is
+
+ constant reg0 : std_logic_vector(7 downto 0) := "00000000";
+ constant reg1 : std_logic_vector(7 downto 0) := "11111111";
+ signal dbus : std_logic_vector(7 downto 0);
+ signal reg_sel, read, reg_addr : X01 := '0';
+
+begin
+
+ -- code from book
+
+ reg_read_selector : block (reg_sel = '1' and read = '1') is
+ begin
+ dbus <= reg0 when guard and reg_addr = '0' else
+ reg1 when guard and reg_addr = '1' else
+ "ZZZZZZZZ";
+ end block reg_read_selector;
+
+ -- end code from book
+
+ stimulus : process is
+ begin
+ reg_sel <= '1'; wait for 10 ns;
+ read <= '1', '0' after 5 ns; wait for 10 ns;
+ reg_sel <= '0'; wait for 10 ns;
+ read <= '1', '0' after 5 ns; wait for 10 ns;
+ reg_addr <= '1'; wait for 10 ns;
+ reg_sel <= '1'; wait for 10 ns;
+ read <= '1', '0' after 5 ns; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/resolve.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/resolve.vhd
new file mode 100644
index 000000000..4cdeeb52f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/resolve.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package resolve is
+
+ -- code from book (in text)
+
+ subtype byte is bit_vector(0 to 7);
+ type byte_array is array (integer range <>) of byte;
+ function resolve ( bytes : byte_array ) return byte;
+ subtype resolved_byte is resolve byte;
+
+ -- end code from book
+
+end package resolve;
+
+
+package body resolve is
+
+ -- code from book
+
+ function resolve ( bytes : byte_array ) return byte is
+ variable result : byte := b"0000_0000";
+ begin
+ for index in bytes'range loop
+ result := result or bytes(index);
+ end loop;
+ return result;
+ end function resolve;
+
+ -- end code from book
+
+end package body resolve;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd
new file mode 100644
index 000000000..1a27df3fc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity sensor is
+
+ generic ( threshold : real; -- voltage threshold
+ tipd_clk : delay_length; -- input prop delay on clk
+ tipd_input : real; -- input prop delay on sensor input
+ topd_q : delay_length ); -- output prop delay on q
+
+ port ( terminal input : electrical; -- sensor analog input
+ signal clk : in bit; -- edge–triggered clock input
+ signal q : out bit ); -- sensor digital output
+
+end entity sensor;
+
+
+architecture detailed_timing of sensor is
+
+ quantity vin across input; -- analog input values
+ quantity v_delayed : voltage; -- input voltage delayed
+ signal clk_delayed : bit; -- clk input port delayed
+ signal q_int : bit; -- q output with zero delay
+
+begin
+
+ input_port_delay : block is
+ begin
+ v_delayed == vin'delayed(tipd_input);
+ clk_delayed <= clk'delayed(tipd_clk);
+ end block input_port_delay;
+
+ AD_conversion : block is
+ begin
+ q_int <= '1' when vin'above(threshold) else
+ '0';
+ end block AD_conversion;
+
+ output_port_delay : block is
+ begin
+ q <= q_int'delayed(topd_q);
+ end block output_port_delay;
+
+end architecture detailed_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_full.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_full.vhd
new file mode 100644
index 000000000..bc6300a9d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_full.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_full is
+end entity tb_full;
+
+
+library util; use util.stimulus_generators.all;
+
+architecture test of tb_full is
+
+ signal in1, in2, in3, out1, out2 : bit;
+ signal test_vector : bit_vector(1 to 3);
+
+begin
+
+ dut : configuration work.full
+ generic map ( inpad_delay => 2 ns, outpad_delay => 3 ns )
+ port map ( in1 => in1, in2 => in2, in3 => in3, out1 => out1, out2 => out2 );
+
+ stimulus : all_possible_values ( test_vector, 50 ns );
+
+ (in1, in2, in3) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_latch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_latch.vhd
new file mode 100644
index 000000000..e6fb12f09
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_latch.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_latch is
+end entity tb_latch;
+
+
+architecture test of tb_latch is
+
+ signal enable : bit := '0';
+ signal d, q : bit_vector(0 to 7);
+
+begin
+
+ dut : entity work.latch(behavioral)
+ generic map ( width => 8 )
+ port map ( enable => enable, d => d, q => q );
+
+ stimulus : process is
+ begin
+ wait for 10 ns;
+ d <= X"11"; wait for 10 ns;
+ enable <= '1'; wait for 10 ns;
+ d <= X"AA"; wait for 10 ns;
+ enable <= '0'; wait for 10 ns;
+ d <= X"00"; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_sensor.vhd
new file mode 100644
index 000000000..de3d13094
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_sensor.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_sensor is
+end tb_sensor;
+
+architecture tb_sensor of tb_sensor is
+ -- Component declarations
+ -- Signal declarations
+ terminal vin : electrical;
+ signal clk, q : bit;
+ signal lclclkinitwire : bit := '0';
+begin
+ -- Signal assignments
+ -- Component instances
+ v1 : entity work.v_sine(ideal)
+ generic map(
+ freq => 10.0,
+ amplitude => 1.0
+ )
+ port map(
+ pos => vin,
+ neg => electrical_ref
+ );
+ sens1 : entity work.sensor_wa(detailed_timing)
+ generic map(
+ threshold => 0.25,
+ tipd_clk => 10 ns,
+ tipd_input => 20.0e-9,
+ topd_q => 10 ns
+ )
+ port map(
+ input => vin,
+ clk => clk,
+ q => q
+ );
+ -- ctrl
+ P_ctrl :
+ process
+ begin
+ if (lclclkinitwire /= '1')
+ then
+ clk <= '0';
+ wait for 1000.000 ns;
+ else
+ clk <= '1';
+ wait for 5240.000 ns;
+ clk <= '0';
+ wait for 34760.000 ns;
+ end if;
+ end process P_ctrl;
+
+ KillerProc :
+ process
+ begin
+ wait for 1 ns;
+ lclclkinitwire <= '1';
+ wait;
+ end process;
+end tb_sensor;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_tri_state_reg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_tri_state_reg.vhd
new file mode 100644
index 000000000..993cdf4ca
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_tri_state_reg.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+use work.resolve.all;
+
+entity tb_tri_state_reg is
+end entity tb_tri_state_reg;
+
+
+architecture test of tb_tri_state_reg is
+
+ signal d1, d2, q : resolved_byte := X"00";
+ signal clk1, clk2, oe1, oe2 : bit := '0';
+
+begin
+
+ dut1 : entity work.tri_state_reg(behavioral)
+ port map ( d => d1, q => q, clock => clk1, out_enable => oe1 );
+
+ dut2 : entity work.tri_state_reg(behavioral)
+ port map ( d => d2, q => q, clock => clk2, out_enable => oe2 );
+
+ stimulus : process is
+ begin
+ d1 <= X"11"; clk1 <= '1', '0' after 5 ns; wait for 10 ns;
+ oe1 <= '1', '0' after 5 ns; wait for 10 ns;
+ d2 <= X"21"; clk2 <= '1', '0' after 5 ns; wait for 10 ns;
+ oe2 <= '1', '0' after 5 ns; wait for 10 ns;
+ oe1 <= '1', '0' after 5 ns;
+ oe2 <= '1', '0' after 5 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd
new file mode 100644
index 000000000..8c0bd7a6a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+use work.resolve.all;
+
+-- code from book (in text)
+
+entity tri_state_reg is
+ port ( d : in resolved_byte;
+ q : out resolved_byte bus;
+ clock, out_enable : in bit );
+end entity tri_state_reg;
+
+-- end code from book
+
+
+
+-- code from book
+
+architecture behavioral of tri_state_reg is
+begin
+
+ reg_behavior : process (d, clock, out_enable) is
+ variable stored_byte : byte;
+ begin
+ if clock'event and clock = '1' then
+ stored_byte := d;
+ end if;
+ if out_enable = '1' then
+ q <= stored_byte;
+ else
+ q <= null;
+ end if;
+ end process reg_behavior;
+
+end architecture behavioral;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd
new file mode 100644
index 000000000..863f9e942
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity SR_flipflop is
+ port ( s_n, r_n : in bit; q, q_n : inout bit );
+
+begin
+
+ postponed process (q, q_n) is
+ begin
+ assert now = 0 fs or q = not q_n
+ report "implementation error: q /= not q_n";
+ end postponed process;
+
+end entity SR_flipflop;
+
+--------------------------------------------------
+
+architecture dataflow of SR_flipflop is
+begin
+
+ gate_1 : q <= s_n nand q_n;
+ gate_2 : q_n <= r_n nand q;
+
+end architecture dataflow;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/count2-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/count2-1.vhd
new file mode 100644
index 000000000..e810c66c2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/count2-1.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity D_flipflop is
+ port ( clk, d : in bit; q : buffer bit );
+end entity D_flipflop;
+
+
+architecture behavioral of D_flipflop is
+begin
+ q <= d when clk'event and clk = '1';
+end architecture behavioral;
+
+
+
+entity inverter is
+ port ( a : in bit; y : out bit );
+end entity inverter;
+
+
+architecture behavioral of inverter is
+begin
+ y <= not a;
+end architecture behavioral;
+
+
+
+-- code from book
+
+entity count2 is
+ port ( clk : in bit; q0, q1 : buffer bit );
+end entity count2;
+
+--------------------------------------------------
+
+architecture buffered_outputs of count2 is
+
+ component D_flipflop is
+ port ( clk, d : in bit; q : buffer bit );
+ end component D_flipflop;
+
+ component inverter is
+ port ( a : in bit; y : out bit );
+ end component inverter;
+
+ signal q0_n, q1_n : bit;
+
+begin
+
+ bit0 : component D_flipflop
+ port map ( clk => clk, d => q0_n, q => q0 );
+
+ inv0 : component inverter
+ port map ( a => q0, y => q0_n );
+
+ bit1 : component D_flipflop
+ port map ( clk => q0_n, d => q1_n, q => q1 );
+
+ inv1 : component inverter
+ port map ( a => q1, y => q1_n );
+
+end architecture buffered_outputs;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/index-ams.txt
new file mode 100644
index 000000000..9e0658eea
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/index-ams.txt
@@ -0,0 +1,25 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 24 - Miscellaneous Topics
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+count2-1.vhd entity D_flipflop behavioral --
+-- entity inverter behavioral --
+-- entity count2 buffered_outputs Figure 24-1
+limit_checker.vhd package project_util body Section 24.2
+-- entity limit_checker behavioral Figure 24-2
+test_bench.vhd entity random_source fudged Section 24.2
+-- entity test_bench random_test Figure 24-3
+processor.vhd entity processor rtl Figure 24-4
+SR_flipflop.vhd entity SR_flipflop dataflow Figure 24-5
+inline_01.vhd entity inline_01 test Section 24.2
+inline_02.vhd entity inline_02 test Section 24.3
+inline_04a.vhd entity controller instrumented Section 24.4
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_count2.vhd entity tb_count2 test count2.vhd
+tb_limit_checker.vhd entity tb_limit_checker test limit_checker.vhd
+tb_SR_flipflop.vhd entity tb_SR_flipflop test SR_flipflop.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_01.vhd
new file mode 100644
index 000000000..2cc6670f4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_01.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+
+ type std_ulogic is (t1, t2, t3);
+ subtype std_logic is std_ulogic;
+
+ -- code from book:
+
+ type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+
+ type std_logic_vector is array ( natural range <>) of std_logic;
+
+ -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_02.vhd
new file mode 100644
index 000000000..e087f5b2b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_02.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+
+ signal s : bit;
+
+begin
+
+ -- code from book:
+
+ p : postponed process is
+ -- . . .
+ begin
+ -- . . .
+ wait until s = '1';
+ -- . . . -- s may not be '1'!!
+ -- not in book
+ report bit'image(s);
+ wait;
+ -- end not in book
+ end postponed process p;
+
+ -- end of code from book
+
+ stimulus : process is
+ begin
+ wait for 10 ns;
+ s <= '1';
+ wait for 0 ns;
+ s <= '0';
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_04a.vhd
new file mode 100644
index 000000000..4e180342d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_04a.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity controller is
+end entity controller;
+
+
+-- code from book
+
+architecture instrumented of controller is
+
+ shared variable operation_count : natural := 0;
+ -- . . .
+
+begin
+ -- . . .
+end architecture instrumented;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/limit_checker.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/limit_checker.vhd
new file mode 100644
index 000000000..dca143795
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/limit_checker.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+package project_util is
+
+ -- code from book (in text)
+
+ function "<" ( bv1, bv2 : bit_vector ) return boolean;
+
+ subtype word is std_logic_vector(31 downto 0);
+
+ -- end code from book
+
+end package project_util;
+
+
+package body project_util is
+
+ function "<" ( bv1, bv2 : bit_vector ) return boolean is
+ variable tmp1 : bit_vector(bv1'range) := bv1;
+ variable tmp2 : bit_vector(bv2'range) := bv2;
+ begin
+ assert bv1'length = bv2'length
+ report "vectors are of different length in ""<"" comparison"
+ severity failure;
+ tmp1(tmp1'left) := not tmp1(tmp1'left);
+ tmp2(tmp2'left) := not tmp2(tmp2'left);
+ return std.standard."<" ( tmp1, tmp2 );
+ end function "<";
+
+end package body project_util;
+
+
+
+-- code from book
+
+library ieee; use ieee.std_logic_1164.all;
+use work.project_util.all;
+
+entity limit_checker is
+ port ( input, lower_bound, upper_bound : in word;
+ out_of_bounds : out std_logic );
+end entity limit_checker;
+
+--------------------------------------------------
+
+architecture behavioral of limit_checker is
+
+ subtype bv_word is bit_vector(31 downto 0);
+
+ function word_to_bitvector ( w : in word ) return bv_word is
+ begin
+ return To_bitvector ( w, xmap => '0' );
+ end function word_to_bitvector;
+
+begin
+
+ algorithm : process (input, lower_bound, upper_bound) is
+ begin
+ if "<" ( bv1 => word_to_bitvector(input),
+ bv2 => word_to_bitvector(lower_bound) )
+ or "<" ( bv1 => word_to_bitvector(upper_bound),
+ bv2 => word_to_bitvector(input) ) then
+ out_of_bounds <= '1';
+ else
+ out_of_bounds <= '0';
+ end if;
+ end process algorithm;
+
+end architecture behavioral;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/processor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/processor.vhd
new file mode 100644
index 000000000..94b5beb5f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/processor.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity processor is
+end entity processor;
+
+
+-- code from book
+
+architecture rtl of processor is
+
+ component latch is
+ generic ( width : positive );
+ port ( d : in std_ulogic_vector(0 to width - 1);
+ q : out std_ulogic_vector(0 to width - 1);
+ -- . . . );
+ -- not in book
+ other_port : in std_ulogic := '-' );
+ -- end not in book
+ end component latch;
+
+ component ROM is
+ port ( d_out : out std_ulogic_vector; -- . . . );
+ -- not in book
+ other_port : in std_ulogic := '-' );
+ -- end not in book
+ end component ROM;
+
+ subtype std_logic_word is std_logic_vector(0 to 31);
+
+ signal source1, source2, destination : std_logic_word;
+ -- . . .
+
+begin
+
+ temp_register : component latch
+ generic map ( width => 32 )
+ port map ( d => std_ulogic_vector(destination),
+ std_logic_vector(q) => source1, -- . . . );
+ -- not in book
+ other_port => open );
+ -- end not in book
+
+ constant_ROM : component ROM
+ port map ( std_logic_word(d_out) => source2, -- . . . );
+ -- not in book
+ other_port => open );
+ -- end not in book
+
+ -- . . .
+
+end architecture rtl;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_SR_flipflop.vhd
new file mode 100644
index 000000000..f729f0b2a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_SR_flipflop.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_SR_flipflop is
+end entity tb_SR_flipflop;
+
+
+architecture test of tb_SR_flipflop is
+
+ signal s_n, r_n, q, q_n : bit;
+
+begin
+
+ dut : entity work.SR_flipflop
+ port map ( s_n, r_n, q, q_n );
+
+ s_n <= '1',
+ '0' after 10 ns, '1' after 15 ns,
+ '0' after 30 ns, '1' after 40 ns;
+
+ r_n <= '0', '1' after 5 ns,
+ '0' after 20 ns, '1' after 25 ns,
+ '0' after 30 ns, '1' after 35 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_count2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_count2.vhd
new file mode 100644
index 000000000..7fd2e9cc5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_count2.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_count2 is
+end entity tb_count2;
+
+
+architecture test of tb_count2 is
+
+ signal clk, q0, q1 : bit;
+
+begin
+
+ dut : entity work.count2(buffered_outputs)
+ port map ( clk => clk, q0 => q0, q1 => q1 );
+
+ clk_gen : clk <= not clk after 10 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_limit_checker.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_limit_checker.vhd
new file mode 100644
index 000000000..42cebc02d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_limit_checker.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+use work.project_util.all;
+
+entity tb_limit_checker is
+end entity tb_limit_checker;
+
+
+architecture test of tb_limit_checker is
+
+ signal input : word;
+ signal out_of_bounds : std_logic;
+
+begin
+
+ dut : entity work.limit_checker(behavioral)
+ port map ( input => input,
+ lower_bound => X"FFFFFFF0", upper_bound => X"00000010",
+ out_of_bounds => out_of_bounds );
+
+ stimulus : input <= X"00000000",
+ X"00000008" after 10 ns,
+ X"00000010" after 20 ns,
+ X"00000018" after 30 ns,
+ X"FFFFFFF8" after 40 ns,
+ X"FFFFFFF0" after 50 ns,
+ X"FFFFFF00" after 60 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/test_bench.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/test_bench.vhd
new file mode 100644
index 000000000..01a92353c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/test_bench.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book (in text)
+
+entity random_source is
+ generic ( min, max : natural;
+ seed : natural;
+ interval : delay_length );
+ port ( number : out natural );
+end entity random_source;
+
+-- end code from book
+
+
+architecture fudged of random_source is
+begin
+
+ process is
+ variable next_number : natural := seed;
+ begin
+ if next_number > max then
+ next_number := min;
+ end if;
+ number <= next_number;
+ next_number := next_number + 1;
+ wait for interval;
+ end process;
+
+end architecture fudged;
+
+
+
+entity test_bench is
+end entity test_bench;
+
+
+-- code from book
+
+architecture random_test of test_bench is
+
+ subtype bv11 is bit_vector(10 downto 0);
+
+ function natural_to_bv11 ( n : natural ) return bv11 is
+ variable result : bv11 := (others => '0');
+ variable remaining_digits : natural := n;
+ begin
+ for index in result'reverse_range loop
+ result(index) := bit'val(remaining_digits mod 2);
+ remaining_digits := remaining_digits / 2;
+ exit when remaining_digits = 0;
+ end loop;
+ return result;
+ end function natural_to_bv11;
+
+ signal stimulus_vector : bv11;
+ -- . . .
+
+begin
+
+ stimulus_generator : entity work.random_source
+ generic map ( min => 0, max => 2**10 - 1, seed => 0,
+ interval => 100 ns )
+ port map ( natural_to_bv11(number) => stimulus_vector );
+
+ -- . . .
+
+end architecture random_test;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/address_decoder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/address_decoder.vhd
new file mode 100644
index 000000000..14c20b022
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/address_decoder.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity address_decoder is
+ port ( addr : in work.cpu_types.address;
+ status : in work.cpu_types.status_value;
+ mem_sel, int_sel, io_sel : out bit );
+end entity address_decoder;
+
+--------------------------------------------------
+
+architecture functional of address_decoder is
+
+ constant mem_low : work.cpu_types.address := X"000000";
+ constant mem_high : work.cpu_types.address := X"EFFFFF";
+ constant io_low : work.cpu_types.address := X"F00000";
+ constant io_high : work.cpu_types.address := X"FFFFFF";
+
+begin
+
+ mem_decoder :
+ mem_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.fetch)
+ or work.cpu_types."="(status, work.cpu_types.mem_read)
+ or work.cpu_types."="(status, work.cpu_types.mem_write) )
+ and addr >= mem_low
+ and addr <= mem_high else
+ '0';
+
+ int_decoder :
+ int_sel <= '1' when work.cpu_types."="(status, work.cpu_types.int_ack) else
+ '0';
+
+ io_decoder :
+ io_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.io_read)
+ or work.cpu_types."="(status, work.cpu_types.io_write) )
+ and addr >= io_low
+ and addr <= io_high else
+ '0';
+
+end architecture functional;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/analog_output_interface.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/analog_output_interface.vhd
new file mode 100644
index 000000000..604a98906
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/analog_output_interface.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity analog_output_interface is
+ port ( signal wr : in std_ulogic;
+ signal data : std_ulogic_vector(7 downto 0);
+ terminal analog_out : electrical );
+end entity analog_output_interface;
+
+
+----------------
+
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity analog_interface_dac is
+ port ( signal d_in : std_ulogic_vector(7 downto 0);
+ terminal output : electrical;
+ terminal plus_supply, minus_supply : electrical );
+end entity analog_interface_dac;
+
+
+architecture macroblock of analog_interface_dac is
+
+begin
+
+end architecture macroblock;
+
+-- end not in book
+
+
+
+
+architecture structural of analog_output_interface is
+
+ -- This architecture implements the interface as a register connected to a DAC.
+ -- NOTE: it uses the analog power supply terminals from clock_power_pkg
+ -- to supply the DAC.
+
+ signal register_out : -- . . .;
+ -- not in book
+ std_ulogic_vector(7 downto 0);
+ -- end not in book
+
+begin
+
+ -- ...
+
+ dac : entity work.analog_interface_dac(macroblock)
+ port map ( d_in => register_out, output => analog_out,
+ plus_supply => work.clock_power_pkg.analog_plus_supply,
+ minus_supply => work.clock_power_pkg.analog_ground );
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bit_vector_signed_arithmetic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bit_vector_signed_arithmetic.vhd
new file mode 100644
index 000000000..80ce3c043
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bit_vector_signed_arithmetic.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package bit_vector_signed_arithmetic is
+
+ function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+ function "-" ( bv : bit_vector ) return bit_vector;
+
+ function "*" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+ -- . . .
+
+end package bit_vector_signed_arithmetic;
+
+--------------------------------------------------
+
+-- not in book
+library ieee; use ieee.numeric_bit.all;
+-- end not in book
+
+package body bit_vector_signed_arithmetic is
+
+ function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
+ -- not in book
+ begin
+ return bit_vector( "+"(signed(bv1), signed(bv2)) );
+ end function "+";
+ -- end not in book
+
+ function "-" ( bv : bit_vector ) return bit_vector is -- . . .
+ -- not in book
+ begin
+ return bit_vector( "-"(signed(bv)) );
+ end function "-";
+ -- end not in book
+
+ function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is
+ -- . . .
+ begin
+ -- not in book
+ -- . . .
+ return bit_vector( "*"(unsigned(bv1), unsigned(bv2)) );
+ -- end not in book
+ end function mult_unsigned;
+
+ function "*" ( bv1, bv2 : bit_vector ) return bit_vector is
+ begin
+ if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then
+ return mult_unsigned(bv1, bv2);
+ elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then
+ return -mult_unsigned(bv1, -bv2);
+ elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then
+ return -mult_unsigned(-bv1, bv2);
+ else
+ return mult_unsigned(-bv1, -bv2);
+ end if;
+ end function "*";
+
+ -- . . .
+
+end package body bit_vector_signed_arithmetic;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.vhd
new file mode 100644
index 000000000..fda35f289
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity bus_sequencer is
+ port ( rd, wr, sel, width, burst : out std_ulogic;
+ addr_low_4 : out std_ulogic_vector(3 downto 0);
+ ready : out std_ulogic;
+ control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+ analog_out_wr_0,
+ other_signal : out std_ulogic );
+end entity bus_sequencer;
+
+----------------
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity state_register is
+ port ( phi1, phi2 : in std_ulogic;
+ next_state : in std_ulogic_vector(3 downto 0);
+ current_state : out std_ulogic_vector(3 downto 0) );
+end entity state_register;
+
+
+architecture std_cell of state_register is
+
+begin
+
+end architecture std_cell;
+
+-- end not in book
+
+
+
+
+architecture fsm of bus_sequencer is
+
+ -- This architecture implements the sequencer as a finite-state machine.
+ -- NOTE: it uses the clock signals from clock_power_pkg to synchronize the fsm.
+
+ signal next_state_vector : -- . . .;
+ -- not in book
+ std_ulogic_vector(3 downto 0);
+ signal current_state_vector : std_ulogic_vector(3 downto 0);
+ -- end not in book
+
+begin
+
+ bus_sequencer_state_register : entity work.state_register(std_cell)
+ port map ( phi1 => work.clock_power_pkg.clock_phase1,
+ phi2 => work.clock_power_pkg.clock_phase2,
+ next_state => next_state_vector,
+ -- . . . );
+ -- not in book
+ current_state => current_state_vector );
+ -- end not in book
+
+ -- . . .
+
+end architecture fsm;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/clock_power_pkg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/clock_power_pkg.vhd
new file mode 100644
index 000000000..2b7edcf64
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/clock_power_pkg.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+package clock_power_pkg is
+
+ constant Tpw : delay_length := 4 ns;
+
+ signal clock_phase1, clock_phase2 : std_ulogic;
+
+ terminal analog_plus_supply, analog_ground : electrical;
+
+end package clock_power_pkg;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd
new file mode 100644
index 000000000..e2fbe121c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity cpu is
+end entity cpu;
+
+-- end not in book
+
+
+
+
+architecture behavioral of cpu is
+begin
+
+ interpreter : process is
+
+ use work.cpu_types.all;
+
+ variable instr_reg : word;
+ variable instr_opcode : opcode;
+
+ begin
+ -- . . . -- initialize
+ loop
+ -- . . . -- fetch instruction
+ instr_opcode := extract_opcode ( instr_reg );
+ case instr_opcode is
+ when op_nop => null;
+ when op_breq => -- . . .
+ -- . . .
+ -- not in book
+ when others => null;
+ -- end not in book
+ end case;
+ end loop;
+ end process interpreter;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu.vhd
new file mode 100644
index 000000000..c961c8837
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity cpu is
+end entity cpu;
+
+-- end not in book
+
+
+
+
+architecture behavioral of cpu is
+begin
+
+ interpreter : process is
+
+ variable instr_reg : work.cpu_types.word;
+ variable instr_opcode : work.cpu_types.opcode;
+
+ begin
+ -- . . . -- initialize
+ loop
+ -- . . . -- fetch instruction
+ instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
+ case instr_opcode is
+ when work.cpu_types.op_nop => null;
+ when work.cpu_types.op_breq => -- . . .
+ -- . . .
+ -- not in book
+ when others => null;
+ -- end not in book
+ end case;
+ end loop;
+ end process interpreter;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types-1.vhd
new file mode 100644
index 000000000..bf0bebd64
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types-1.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package cpu_types is
+
+ constant word_size : positive := 16;
+ constant address_size : positive := 24;
+
+ subtype word is bit_vector(word_size - 1 downto 0);
+ subtype address is bit_vector(address_size - 1 downto 0);
+
+ type status_value is ( halted, idle, fetch, mem_read, mem_write,
+ io_read, io_write, int_ack );
+
+ subtype opcode is bit_vector(5 downto 0);
+
+ function extract_opcode ( instr_word : word ) return opcode;
+
+ constant op_nop : opcode := "000000";
+ constant op_breq : opcode := "000001";
+ constant op_brne : opcode := "000010";
+ constant op_add : opcode := "000011";
+ -- . . .
+
+end package cpu_types;
+
+
+
+-- not in book
+
+package body cpu_types is
+
+ function extract_opcode ( instr_word : word ) return opcode is
+ begin
+ return work.cpu_types.op_nop;
+ end function extract_opcode;
+
+end package body cpu_types;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types.vhd
new file mode 100644
index 000000000..10d497c63
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book
+
+package cpu_types is
+
+ constant word_size : positive := 16;
+ constant address_size : positive := 24;
+
+ subtype word is bit_vector(word_size - 1 downto 0);
+ subtype address is bit_vector(address_size - 1 downto 0);
+
+ type status_value is ( halted, idle, fetch, mem_read, mem_write,
+ io_read, io_write, int_ack );
+
+end package cpu_types;
+
+-- end code from book
+
+
+
+package cpu_types_test is
+
+ constant status :
+ -- code from book
+ work.cpu_types.status_value
+ -- end code from book
+ :=
+ -- code from book
+ work.cpu_types.status_value'(work.cpu_types.fetch)
+ -- end code from book
+ ;
+
+end package cpu_types_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/index-ams.txt
new file mode 100644
index 000000000..4e8165c17
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/index-ams.txt
@@ -0,0 +1,39 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 10 - Packages
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+cpu_types.vhd package cpu_types -- Figure 10-1
+-- package cpu_types_test -- Section 10.1
+address_decoder.vhd entity address_decoder functional Figure 10-2
+clock_power_pkg.vhd package clock_power_pkg -- Figure 10-3
+io_controller-1.vhd entity phase_locked_clock_gen std_cell --
+-- entity regulator device_level --
+-- entity io_controller top_level Figure 10-4
+bus_sequencer-1.vhd entity state_register std_cell --
+-- entity bus_sequencer fsm Figure 10-5
+analog_output_interface.vhd entity analog_interface_dac macroblock --
+-- entity analog_output_interface structural Figure 10-6
+cpu_types-1.vhd package cpu_types -- Figure 10-7
+cpu.vhd entity cpu behavioral Figure 10-8
+bit_vector_signed_arithmetic.vhd package bit_vector_signed_arithmetic body Figure 10-9
+cpu-1.vhd entity cpu behavioral Figure 10-10
+lessthan.vhd entity lessthan test Figure 10-11
+test_alu.vhd package alu_types -- Section 10.5
+-- entity ALU structural Section 10.5
+-- test_alu random_test Figure 10-14
+inline_01.vhd entity inline_01 test Section 10.1
+inline_02.vhd package inline_02 body Section 10.1
+inline_03.vhd entity inline_03 test Section 10.3
+inline_04a.vhd entity inline_04a test Section 10.3
+inline_05.vhd entity logic_block -- Section 10.3
+inline_06.vhd entity inline_06 test Section 10.4
+inline_08.vhd package inline_08 -- Section 10.5
+inline_09.vhd entity inline_09 test Section 10.5
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_address_decoder.vhd entity tb_address_decoder test address_decoder.vhd
+tb_bit_vector_signed_arithmetic.vhd tb_bit_vector_signed_arithmetic test bit_vector_signed_arithmetic.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_01.vhd
new file mode 100644
index 000000000..641ba6bc8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_01.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+library ieee;
+
+architecture test of inline_01 is
+
+begin
+
+ process_1_a : process is
+
+ -- code from book:
+
+ variable stored_state : ieee.std_logic_1164.std_ulogic;
+
+ -- end of code from book
+
+ begin
+
+ wait;
+ end process process_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_02.vhd
new file mode 100644
index 000000000..0019d2e9a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_02.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package inline_02 is
+
+ -- code from book
+
+ subtype word32 is bit_vector(31 downto 0);
+
+ procedure add ( a, b : in word32;
+ result : out word32; overflow : out boolean );
+
+ function "<" ( a, b : in word32 ) return boolean;
+
+ constant max_buffer_size : positive;
+
+ -- end code from book
+
+end package inline_02;
+
+
+package body inline_02 is
+
+ -- code from book
+
+ constant max_buffer_size : positive := 4096;
+
+ -- end code from book
+
+end package body inline_02;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd
new file mode 100644
index 000000000..640c35e8c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+library ieee;
+
+architecture test of inline_03 is
+begin
+
+
+ process_3_a : process is
+
+ -- code from book:
+
+ use work.cpu_types;
+
+ variable data_word : cpu_types.word;
+ variable next_address : cpu_types.address;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_3_a;
+
+
+ ----------------
+
+
+ process_3_b : process is
+
+ -- code from book:
+
+ use work.cpu_types.word, work.cpu_types.address;
+
+ variable data_word : word;
+ variable next_address : address;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_04a.vhd
new file mode 100644
index 000000000..6d695d0af
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_04a.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+----------------------------------------------------------------
+
+
+library ieee_proposed;
+
+architecture test of inline_04a is
+begin
+
+
+ block_3_c : block is
+
+ -- code from book:
+
+ use ieee_proposed.electrical_systems.all;
+
+ -- end of code from book
+
+ begin
+ end block block_3_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_05.vhd
new file mode 100644
index 000000000..c8b9f9ef8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_05.vhd
@@ -0,0 +1,25 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.std_ulogic;
+
+entity logic_block is
+ port ( a, b : in std_ulogic;
+ y, z : out std_ulogic );
+end entity logic_block;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_06.vhd
new file mode 100644
index 000000000..c6e2f6ec1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_06.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- code from book:
+
+library std, work; use std.standard.all;
+
+-- end of code from book
+
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+begin
+
+
+ process_4_a : process is
+
+ constant a : integer := 10;
+ constant b : integer := 20;
+ variable result : boolean;
+
+ begin
+
+ -- code from book:
+
+ result := std.standard."<" ( a, b );
+
+ -- end of code from book
+
+ wait;
+ end process process_4_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_08.vhd
new file mode 100644
index 000000000..9c6bdf412
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_08.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package inline_08 is
+
+ -- code from book
+
+ procedure uniform ( variable seed1, seed2 : inout positive;
+ variable x : out real);
+
+ -- end code from book
+
+end package inline_08;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_09.vhd
new file mode 100644
index 000000000..c26ede7c6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_09.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee;
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+begin
+
+ process_5_c : process is
+
+ use ieee.math_real.all;
+
+ -- code from book
+
+ type complex is record
+ re : real; -- Real part
+ im : real; -- Imaginary part
+ end record;
+
+ subtype positive_real is real range 0.0 to real'high;
+ subtype principal_value is real range -math_pi to math_pi;
+
+ type complex_polar is record
+ mag : positive_real; -- Magnitude
+ arg : principal_value; -- Angle in radians; -math_pi is illegal
+ end record;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process process_5_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd
new file mode 100644
index 000000000..56fb1faeb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity phase_locked_clock_gen is
+ port ( ref_clock : in std_ulogic;
+ phi1, phi2 : out std_ulogic );
+end entity phase_locked_clock_gen;
+
+
+architecture std_cell of phase_locked_clock_gen is
+
+ use work.clock_power_pkg.Tpw;
+
+begin
+
+ phi1_gen : phi1 <= '1', '0' after Tpw when rising_edge(ref_clock);
+
+ phi2_gen : phi2 <= '1', '0' after Tpw when falling_edge(ref_clock);
+
+end architecture std_cell;
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity regulator is
+ port ( terminal plus_in, minus_in, plus_out, minus_out : electrical );
+end entity regulator;
+
+
+architecture device_level of regulator is
+begin
+end architecture device_level;
+
+
+
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+-- end not in book
+
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity io_controller is
+ port ( signal ref_clock : in std_ulogic;
+ terminal ext_supply, ext_ground : electrical; -- . . . );
+ -- not in book
+ other_port : in std_ulogic );
+ -- end not in book
+end entity io_controller;
+
+--------------------------------------------------
+
+architecture top_level of io_controller is
+
+ -- . . .
+
+ -- not in book
+ signal rd, wr, sel, width, burst : std_ulogic;
+ signal addr : std_ulogic_vector(3 downto 0);
+ signal ready : std_ulogic;
+ signal control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+ other_signal : std_ulogic;
+
+ signal analog_out_wr_0 : std_ulogic;
+ signal internal_data : std_ulogic_vector(7 downto 0);
+ terminal analog_out_0 : electrical;
+ -- end not in book
+
+begin
+
+ internal_clock_gen : entity work.phase_locked_clock_gen(std_cell)
+ port map ( ref_clock => ref_clock,
+ phi1 => work.clock_power_pkg.clock_phase1,
+ phi2 => work.clock_power_pkg.clock_phase2 );
+
+ internal_analog_regulator : entity work.regulator(device_level)
+ port map ( plus_in => ext_supply, minus_in => ext_ground,
+ plus_out => work.clock_power_pkg.analog_plus_supply,
+ minus_out => work.clock_power_pkg.analog_ground );
+
+ the_bus_sequencer : entity work.bus_sequencer(fsm)
+ port map ( rd, wr, sel, width, burst, addr(3 downto 0), ready,
+ control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+ analog_out_wr_0, -- . . . );
+ -- not in book
+ other_signal );
+ -- not in book
+
+ analog_output_interface_0 : entity work.analog_output_interface(structural)
+ port map ( analog_out_wr_0, internal_data(7 downto 0), analog_out_0 );
+
+ -- . . .
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/lessthan.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/lessthan.vhd
new file mode 100644
index 000000000..4a9720006
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/lessthan.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity lessthan is
+end entity lessthan;
+
+
+
+architecture test of lessthan is
+
+ -- code from book
+
+ function "<" ( a, b : bit_vector ) return boolean is
+ variable tmp1 : bit_vector(a'range) := a;
+ variable tmp2 : bit_vector(b'range) := b;
+ begin
+ tmp1(tmp1'left) := not tmp1(tmp1'left);
+ tmp2(tmp2'left) := not tmp2(tmp2'left);
+ return std.standard."<" ( tmp1, tmp2 );
+ end function "<";
+
+ -- end code from book
+
+ signal a, b : bit_vector(7 downto 0);
+ signal result : boolean;
+
+begin
+
+ dut : result <= a < b;
+
+ stimulus : process is
+ begin
+ wait for 10 ns;
+ a <= X"02"; b <= X"04"; wait for 10 ns;
+ a <= X"02"; b <= X"02"; wait for 10 ns;
+ a <= X"02"; b <= X"01"; wait for 10 ns;
+ a <= X"02"; b <= X"FE"; wait for 10 ns;
+ a <= X"FE"; b <= X"02"; wait for 10 ns;
+ a <= X"FE"; b <= X"FE"; wait for 10 ns;
+ a <= X"FE"; b <= X"FC"; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_address_decoder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_address_decoder.vhd
new file mode 100644
index 000000000..7be5b79c0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_address_decoder.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_address_decoder is
+end entity tb_address_decoder;
+
+
+architecture test of tb_address_decoder is
+
+ use work.cpu_types.all;
+
+ signal addr : address := X"000000";
+ signal status : status_value := idle;
+ signal mem_sel, int_sel, io_sel : bit;
+
+begin
+
+ dut : entity work.address_decoder
+ port map ( addr => addr, status => status,
+ mem_sel => mem_sel, int_sel => int_sel, io_sel => io_sel );
+
+ stimulus : process is
+ begin
+ wait for 10 ns;
+
+ status <= fetch; wait for 10 ns;
+ status <= mem_read; wait for 10 ns;
+ status <= mem_write; wait for 10 ns;
+ status <= io_read; wait for 10 ns;
+ status <= io_write; wait for 10 ns;
+ status <= int_ack; wait for 10 ns;
+ status <= idle; wait for 10 ns;
+
+ addr <= X"EFFFFF"; wait for 10 ns;
+ status <= fetch; wait for 10 ns;
+ status <= mem_read; wait for 10 ns;
+ status <= mem_write; wait for 10 ns;
+ status <= io_read; wait for 10 ns;
+ status <= io_write; wait for 10 ns;
+ status <= int_ack; wait for 10 ns;
+ status <= idle; wait for 10 ns;
+
+ addr <= X"F00000"; wait for 10 ns;
+ status <= fetch; wait for 10 ns;
+ status <= mem_read; wait for 10 ns;
+ status <= mem_write; wait for 10 ns;
+ status <= io_read; wait for 10 ns;
+ status <= io_write; wait for 10 ns;
+ status <= int_ack; wait for 10 ns;
+ status <= idle; wait for 10 ns;
+
+ addr <= X"FFFFFF"; wait for 10 ns;
+ status <= fetch; wait for 10 ns;
+ status <= mem_read; wait for 10 ns;
+ status <= mem_write; wait for 10 ns;
+ status <= io_read; wait for 10 ns;
+ status <= io_write; wait for 10 ns;
+ status <= int_ack; wait for 10 ns;
+ status <= idle; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_bit_vector_signed_arithmetic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_bit_vector_signed_arithmetic.vhd
new file mode 100644
index 000000000..130f1dca4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_bit_vector_signed_arithmetic.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_bit_vector_signed_arithmetic is
+end entity tb_bit_vector_signed_arithmetic;
+
+
+architecture test of tb_bit_vector_signed_arithmetic is
+begin
+
+ stimulus : process is
+ use work.bit_vector_signed_arithmetic.all;
+ use std.textio.all;
+ variable L : line;
+ begin
+ write(L, X"0002" + X"0005");
+ writeline(output, L);
+ write(L, X"0002" + X"FFFE");
+ writeline(output, L);
+ write(L, - X"0005");
+ writeline(output, L);
+ write(L, - X"FFFE");
+ writeline(output, L);
+ write(L, X"0002" * X"0005");
+ writeline(output, L);
+ write(L, X"0002" * X"FFFD");
+ writeline(output, L);
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/test_alu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/test_alu.vhd
new file mode 100644
index 000000000..3ed4d1aac
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/test_alu.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee;
+
+package alu_types is
+
+ -- code from book (in text)
+
+ use ieee.numeric_bit.all;
+ subtype ALU_func is unsigned(3 downto 0);
+ subtype data_word is unsigned(15 downto 0);
+ -- . . .
+
+ -- end code from book (in text)
+
+end package alu_types;
+
+
+
+use work.alu_types.all;
+
+-- code from book (in text)
+
+entity ALU is
+ port ( a, b : in data_word; func : in ALU_func;
+ result : out data_word; carry : out bit );
+end entity ALU;
+
+-- end code from book (in text)
+
+
+
+architecture structural of ALU is
+begin
+end architecture structural;
+
+
+entity test_ALU is
+end entity test_ALU;
+
+
+
+library ieee;
+use work.alu_types.all;
+
+-- code from book
+
+architecture random_test of test_ALU is
+
+ use ieee.numeric_bit.all;
+ use ieee.math_real.uniform;
+
+ signal a, b, result : data_word;
+ signal func : ALU_func;
+ signal carry : bit;
+
+begin
+
+ dut : entity work.ALU(structural)
+ port map ( a, b, func, result, carry );
+
+ stimulus : process is
+ variable seed1, seed2 : positive := 1;
+ variable a_real, b_real, func_real : real;
+ begin
+ wait for 100 ns;
+ uniform ( seed1, seed2, a_real );
+ uniform ( seed1, seed2, b_real );
+ uniform ( seed1, seed2, func_real );
+ a <= to_unsigned( natural(a_real * real(2**integer'(data_word'length)) - 0.5),
+ data_word'length );
+ b <= to_unsigned( natural(b_real * real(2**integer'(data_word'length)) - 0.5),
+ data_word'length );
+ func <= to_unsigned( natural(func_real
+ * real(2**integer'(ALU_func'length)) - 0.5),
+ ALU_func'length );
+ end process stimulus;
+
+ -- . . . --verification process to check result and carry
+
+end architecture random_test;
+
+-- end code from book
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd
new file mode 100644
index 000000000..82c582609
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package MVL4 is
+
+ type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type
+
+ type MVL4_ulogic_vector is array (natural range <>) of MVL4_ulogic;
+
+ function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
+ return MVL4_ulogic;
+
+ subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
+
+ -- code from book (in text)
+
+ type MVL4_logic_vector is array (natural range <>) of MVL4_logic;
+
+ -- end code from book
+
+end package MVL4;
+
+--------------------------------------------------
+
+package body MVL4 is
+
+ type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
+
+ constant resolution_table : table :=
+ -- 'X' '0' '1' 'Z'
+ -- ------------------
+ ( ( 'X', 'X', 'X', 'X' ), -- 'X'
+ ( 'X', '0', 'X', '0' ), -- '0'
+ ( 'X', 'X', '1', '1' ), -- '1'
+ ( 'X', '0', '1', 'Z' ) ); -- 'Z'
+
+ function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
+ return MVL4_ulogic is
+ variable result : MVL4_ulogic := 'Z';
+ begin
+ for index in contribution'range loop
+ result := resolution_table(result, contribution(index));
+ end loop;
+ return result;
+ end function resolve_MVL4;
+
+end package body MVL4;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd
new file mode 100644
index 000000000..8efe10e6a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity bus_module is
+ port ( synch : inout std_ulogic; -- . . . );
+ -- not in book
+ other_port : in std_ulogic := 'U' );
+ -- end not in book
+end entity bus_module;
+
+--------------------------------------------------
+
+-- not in book
+
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity bus_based_system is
+end entity bus_based_system;
+
+-- end not in book
+
+
+architecture top_level of bus_based_system is
+
+ signal synch_control : std_logic;
+ -- . . .
+
+begin
+
+ synch_control_pull_up : synch_control <= 'H';
+
+ bus_module_1 : entity work.bus_module(behavioral)
+ port map ( synch => synch_control, -- . . . );
+ -- not in book
+ other_port => open );
+ -- end not in book
+
+ bus_module_2 : entity work.bus_module(behavioral)
+ port map ( synch => synch_control, -- . . . );
+ -- not in book
+ other_port => open );
+ -- end not in book
+
+ -- . . .
+
+end architecture top_level;
+
+
+
+architecture behavioral of bus_module is
+begin
+
+ behavior : process is
+ -- . . .
+ -- not in book
+ constant Tdelay_synch : delay_length := 10 ns;
+ constant wait_delay : delay_length := 100 ns;
+ -- end not in book
+ begin
+ synch <= '0' after Tdelay_synch;
+ -- . . .
+ -- not in book
+ wait for wait_delay;
+ -- end not in book
+ -- ready to start operation
+ synch <= 'Z' after Tdelay_synch;
+ wait until synch = 'H';
+ -- proceed with operation
+ -- . . .
+ end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd
new file mode 100644
index 000000000..6bd829c2f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd
@@ -0,0 +1,118 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+use work.words.all;
+
+entity cpu is
+ port ( address : out uword; data : inout uword; -- . . . );
+ -- not in book
+ other_port : in X01Z := 'Z' );
+ -- end not in book
+end entity cpu;
+
+
+-- not in book
+
+architecture behavioral of cpu is
+begin
+end architecture behavioral;
+
+-- end not in book
+
+
+--------------------------------------------------
+
+use work.words.all;
+
+entity memory is
+ port ( address : in uword; data : inout uword; -- . . . );
+ -- not in book
+ other_port : in X01Z := 'Z' );
+ -- end not in book
+end entity memory;
+
+
+-- not in book
+
+architecture behavioral of memory is
+begin
+end architecture behavioral;
+
+-- end not in book
+
+
+--------------------------------------------------
+
+
+-- not in book
+
+use work.words.all;
+
+entity ROM is
+ port ( a : in uword; d : out ubyte; other_port : in X01Z := 'Z' );
+end entity ROM;
+
+
+architecture behavioral of ROM is
+begin
+end architecture behavioral;
+
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+
+architecture top_level of computer_system is
+
+ use work.words.all;
+
+ signal address : uword;
+ signal data : word;
+ -- . . .
+
+begin
+
+ the_cpu : entity work.cpu(behavioral)
+ port map ( address, data, -- . . . );
+ -- not in book
+ open );
+ -- end not in book
+
+ the_memory : entity work.memory(behavioral)
+ port map ( address, data, -- . . . );
+ -- not in book
+ open );
+ -- end not in book
+
+ -- . . .
+
+ -- code from book (in text)
+
+-- boot_rom : entity work.ROM(behavioral)
+-- port map ( a => address, d => data(24 to 31), -- . . . ); -- illegal
+-- -- not in book
+-- other_port => open );
+-- -- end not in book
+
+ -- end code from book
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/index-ams.txt
new file mode 100644
index 000000000..433c3104d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/index-ams.txt
@@ -0,0 +1,30 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 15 - Resolved Signals
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+resolve_tri_state_logic.vhd entity resolve_tri_state_logic test Section 15.1, Figure 15-1
+MVL4.vhd package MVL4 body Section 15.1, Figure 15-2
+tri_state_buffer.vhd entity tri_state_buffer behavioral Figure 15.3
+misc_logic.vhd entity misc_logic gate_level Figure 15.4
+words.vhd package words body Figure 15.5
+computer_system.vhd entity cpu behavioral Figure 15.6
+-- entity memory behavioral Figure 15.6
+-- entity ROM behavioral --
+-- entity computer_system top_level Figure 15.6
+memory_system.vhd entity ROM behavioral Figure 15-7
+-- entity SIMM behavioral Figure 15-7
+-- entity memory_system detailed Figure 15-7
+resolved.vhd package resolved body Figure 15-8
+bus_based_system.vhd entity bus_module behavioral Figures 15-9, 15-10
+-- entity bus_based_system top_level Figure 15-9
+synchronize.vhd package synchronize body Figure 15-12
+synchronized_module.vhd entity synchronized_module test Figure 15-13
+inline_01.vhd entity inline_01 test Section 15.1
+inline_02.vhd package inline_02 test Section 15.2
+inline_03.vhd entity IO_section -- Section 15.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd
new file mode 100644
index 000000000..84df14af6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+
+ type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type
+
+ -- code from book:
+
+ type small_int is range 1 to 4;
+ type small_array is array (small_int range <>) of -- . . . ;
+ -- not in book
+ MVL4_ulogic;
+ -- end not in book
+
+ -- end of code from book
+
+ type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
+ constant resolution_table : table :=
+ -- 'X' '0' '1' 'Z'
+ -- ------------------
+ ( ( 'X', 'X', 'X', 'X' ), -- 'X'
+ ( 'X', '0', 'X', '0' ), -- '0'
+ ( 'X', 'X', '1', '1' ), -- '1'
+ ( 'X', '0', '1', 'Z' ) ); -- 'Z'
+
+ function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is
+ variable result : MVL4_ulogic := 'Z';
+ begin
+ for index in contribution'range loop
+ result := resolution_table(result, contribution(index));
+ end loop;
+ return result;
+ end function resolve_MVL4;
+
+ subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
+
+ signal s : MVL4_logic;
+
+begin
+
+ driver_1 : s <= 'Z';
+
+ driver_2 : s <= 'Z';
+
+ driver_3 : s <= 'Z';
+
+ driver_4 : s <= 'Z';
+
+ driver_5 : s <= 'Z';
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd
new file mode 100644
index 000000000..5c5fb5d9d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package inline_02 is
+
+ -- code from book
+
+ type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
+
+ type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+
+ function resolved ( s : std_ulogic_vector ) return std_ulogic;
+
+ subtype std_logic is resolved std_ulogic;
+
+ type std_logic_vector is array ( natural range <>) of std_logic;
+
+ subtype X01 is resolved std_ulogic range 'X' to '1'; -- ('X','0','1')
+ subtype X01Z is resolved std_ulogic range 'X' to 'Z'; -- ('X','0','1','Z')
+ subtype UX01 is resolved std_ulogic range 'U' to '1'; -- ('U','X','0','1')
+ subtype UX01Z is resolved std_ulogic range 'U' to 'Z'; -- ('U','X','0','1','Z')
+
+ -- end code from book
+
+end package inline_02;
+
+
+
+package body inline_02 is
+
+ function resolved ( s : std_ulogic_vector ) return std_ulogic is
+ begin
+ return 'U';
+ end function resolved;
+
+end package body inline_02;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd
new file mode 100644
index 000000000..c459a8faa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd
@@ -0,0 +1,27 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity IO_section is
+ port ( data_ack : inout std_logic; -- . . . );
+ -- not in book
+ other_port : in std_ulogic := 'U' );
+ -- end not in book
+end entity IO_section;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd
new file mode 100644
index 000000000..53f67971d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+use work.MVL4.all;
+
+entity ROM is
+ port ( a : in MVL4_ulogic_vector(15 downto 0);
+ d : inout MVL4_logic_vector(7 downto 0);
+ rd : in MVL4_ulogic );
+end entity ROM;
+
+-- not in book
+architecture behavioral of ROM is
+begin
+end architecture behavioral;
+-- end not in book
+
+--------------------------------------------------
+
+use work.MVL4.all;
+
+entity SIMM is
+ port ( a : in MVL4_ulogic_vector(9 downto 0);
+ d : inout MVL4_logic_vector(31 downto 0);
+ ras, cas, we, cs : in MVL4_ulogic );
+end entity SIMM;
+
+-- not in book
+architecture behavioral of SIMM is
+begin
+end architecture behavioral;
+-- end not in book
+
+--------------------------------------------------
+
+-- not in book
+
+use work.MVL4.all;
+
+entity memory_subsystem is
+end entity memory_subsystem;
+
+-- end not in book
+
+architecture detailed of memory_subsystem is
+
+ signal internal_data : MVL4_logic_vector(31 downto 0);
+ -- . . .
+
+ -- not in book
+ signal internal_addr : MVL4_ulogic_vector(31 downto 0);
+ signal main_mem_addr : MVL4_ulogic_vector(9 downto 0);
+ signal ROM_select : MVL4_ulogic;
+ -- end not in book
+
+begin
+
+ boot_ROM : entity work.ROM(behavioral)
+ port map ( a => internal_addr(15 downto 0),
+ d => internal_data(7 downto 0),
+ rd => ROM_select );
+
+ main_mem : entity work.SIMM(behavioral)
+ port map ( a => main_mem_addr, d => internal_data, -- . . . );
+ -- not in book
+ ras => '0', cas => '0', we => '0', cs => '0' );
+ -- end not in book
+
+ -- . . .
+
+end architecture detailed;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd
new file mode 100644
index 000000000..34b6f84fa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity misc_logic is
+end entity misc_logic;
+
+-- end not in book
+
+
+
+use work.MVL4.all;
+
+architecture gate_level of misc_logic is
+
+ signal src1, src1_enable : MVL4_ulogic;
+ signal src2, src2_enable : MVL4_ulogic;
+ signal selected_val : MVL4_logic;
+ -- . . .
+
+begin
+
+ src1_buffer : entity work.tri_state_buffer(behavioral)
+ port map ( a => src1, enable => src1_enable, y => selected_val );
+
+ src2_buffer : entity work.tri_state_buffer(behavioral)
+ port map ( a => src2, enable => src2_enable, y => selected_val );
+
+ -- . . .
+
+ -- not in book
+
+ stimulus : process is
+ begin
+ wait for 10 ns;
+ src1_enable <= '0'; src2_enable <= '0'; wait for 10 ns;
+ src1 <= '0'; src2 <= '1'; wait for 10 ns;
+ src1_enable <= '1'; wait for 10 ns;
+ src1 <= 'Z'; wait for 10 ns;
+ src1 <= '1'; wait for 10 ns;
+ src1_enable <= '0'; wait for 10 ns;
+ src2_enable <= '1'; wait for 10 ns;
+ src2 <= 'Z'; wait for 10 ns;
+ src2 <= '0'; wait for 10 ns;
+ src2_enable <= '0'; wait for 10 ns;
+ src1_enable <= '1'; src2_enable <= '1'; wait for 10 ns;
+ src1 <= '0'; wait for 10 ns;
+ src1 <= 'X'; wait for 10 ns;
+ src1 <= '1'; src2 <= '1'; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+ -- end not in book
+
+end architecture gate_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd
new file mode 100644
index 000000000..233339aaf
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity resolve_tri_state_logic is
+end entity resolve_tri_state_logic;
+
+
+
+architecture test of resolve_tri_state_logic is
+
+ -- code from book (in text)
+
+ type tri_state_logic is ('0', '1', 'Z');
+
+ type tri_state_logic_array is array (integer range <>) of tri_state_logic;
+
+ -- end code from book
+
+
+ -- code from book
+
+ function resolve_tri_state_logic ( values : in tri_state_logic_array )
+ return tri_state_logic is
+ variable result : tri_state_logic := 'Z';
+ begin
+ for index in values'range loop
+ if values(index) /= 'Z' then
+ result := values(index);
+ end if;
+ end loop;
+ return result;
+ end function resolve_tri_state_logic;
+
+ -- end code from book
+
+
+ -- code from book (in text)
+
+ signal s1 : resolve_tri_state_logic tri_state_logic;
+
+ subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
+
+ signal s2, s3 : resolved_logic;
+
+ -- end code from book
+
+begin
+
+ source_1 : s1 <= 'Z',
+ '0' after 10 ns,
+ 'Z' after 20 ns,
+ '1' after 30 ns,
+ 'Z' after 40 ns,
+ '1' after 200 ns,
+ 'Z' after 220 ns;
+
+ source_2 : s1 <= 'Z',
+ '0' after 110 ns,
+ 'Z' after 120 ns,
+ '1' after 130 ns,
+ 'Z' after 140 ns,
+ '1' after 200 ns,
+ '0' after 210 ns,
+ 'Z' after 220 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd
new file mode 100644
index 000000000..21db85828
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package resolved is
+
+ type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
+ type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+ function resolved ( s : std_ulogic_vector ) return std_ulogic;
+
+end package resolved;
+
+
+package body resolved is
+
+ -- code from book
+
+ type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
+ constant resolution_table : stdlogic_table :=
+ -- ---------------------------------------------
+ -- 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
+ -- ---------------------------------------------
+ ( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- 'U'
+ ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- 'X'
+ ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- '0'
+ ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- '1'
+ ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- 'Z'
+ ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- 'W'
+ ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- 'L'
+ ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- 'H'
+ ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- '-'
+ );
+
+ function resolved ( s : std_ulogic_vector ) return std_ulogic is
+ variable result : std_ulogic := 'Z'; -- weakest state default
+ begin
+ if s'length = 1 then
+ return s(s'low);
+ else
+ for i in s'range loop
+ result := resolution_table(result, s(i));
+ end loop;
+ end if;
+ return result;
+ end function resolved;
+
+ -- end code from book
+
+end package body resolved;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd
new file mode 100644
index 000000000..1591023e6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+package synchronize is
+
+ procedure init_synchronize ( signal synch : out std_logic );
+
+ procedure begin_synchronize ( signal synch : inout std_logic;
+ Tdelay : in delay_length := 0 fs );
+
+ procedure end_synchronize ( signal synch : inout std_logic;
+ Tdelay : in delay_length := 0 fs );
+
+end package synchronize;
+
+
+
+package body synchronize is
+
+ -- code from book
+
+ procedure init_synchronize ( signal synch : out std_logic ) is
+ begin
+ synch <= '0';
+ end procedure init_synchronize;
+
+ procedure begin_synchronize ( signal synch : inout std_logic;
+ Tdelay : in delay_length := 0 fs ) is
+ begin
+ synch <= 'Z' after Tdelay;
+ wait until synch = 'H';
+ end procedure begin_synchronize;
+
+ procedure end_synchronize ( signal synch : inout std_logic;
+ Tdelay : in delay_length := 0 fs ) is
+ begin
+ synch <= '0' after Tdelay;
+ wait until synch = '0';
+ end procedure end_synchronize;
+
+ -- end code from book
+
+end package body synchronize;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd
new file mode 100644
index 000000000..99649caf4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity synchronized_module is
+end entity synchronized_module;
+
+
+
+architecture test of synchronized_module is
+
+ use work.synchronize.all;
+
+ signal barrier : std_logic;
+
+begin
+
+ pullup : barrier <= 'H';
+
+ -- code from book
+
+ synchronized_module : process is
+ -- . . .
+ begin
+ init_synchronize(barrier);
+ -- . . .
+ loop
+ -- . . .
+ begin_synchronize(barrier);
+ -- . . . -- perform operation, synchronized with other processes
+ end_synchronize(barrier);
+ -- . . .
+ end loop;
+ end process synchronized_module;
+
+ -- end code from book
+
+ another_synchronized_module : process is
+ begin
+ init_synchronize(barrier);
+ loop
+ wait for 10 ns;
+ begin_synchronize(barrier);
+ -- . . . -- perform operation, synchronized with other processes
+ end_synchronize(barrier);
+ end loop;
+ end process another_synchronized_module;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd
new file mode 100644
index 000000000..a4b3d1d19
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+use work.MVL4.all;
+
+entity tri_state_buffer is
+ port ( a, enable : in MVL4_ulogic; y : out MVL4_ulogic );
+end entity tri_state_buffer;
+
+--------------------------------------------------
+
+architecture behavioral of tri_state_buffer is
+begin
+
+ y <= 'Z' when enable = '0' else
+ a when enable = '1' and (a = '0' or a = '1') else
+ 'X';
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd
new file mode 100644
index 000000000..d5ccffc72
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package words is
+
+ type X01Z is ('X', '0', '1', 'Z');
+ type uword is array (0 to 31) of X01Z;
+
+ type uword_vector is array (natural range <>) of uword;
+
+ function resolve_word ( contribution : uword_vector ) return uword;
+
+ subtype word is resolve_word uword;
+
+ -- not in book
+ type ubyte is array (0 to 7) of X01Z;
+ -- end not in book
+
+end package words;
+
+--------------------------------------------------
+
+package body words is
+
+ type table is array (X01Z, X01Z) of X01Z;
+
+ constant resolution_table : table :=
+ -- 'X' '0' '1' 'Z'
+ -- ------------------
+ ( ( 'X', 'X', 'X', 'X' ), -- 'X'
+ ( 'X', '0', 'X', '0' ), -- '0'
+ ( 'X', 'X', '1', '1' ), -- '1'
+ ( 'X', '0', '1', 'Z' ) ); -- 'Z'
+
+ function resolve_word ( contribution : uword_vector ) return uword is
+ variable result : uword := (others => 'Z');
+ begin
+ for index in contribution'range loop
+ for element in uword'range loop
+ result(element) :=
+ resolution_table( result(element), contribution(index)(element) );
+ end loop;
+ end loop;
+ return result;
+ end function resolve_word;
+
+end package body words;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/ent.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/ent.vhd
new file mode 100644
index 000000000..9815cbd11
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/ent.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity ent is
+
+end entity ent;
+
+architecture sample of ent is
+
+ constant pi : real := 3.14159;
+
+begin
+
+ process is
+ variable counter : integer;
+ begin
+ -- . . . -- statements using pi and counter
+ end process;
+
+end architecture sample;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/index-ams.txt
new file mode 100644
index 000000000..714094204
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/index-ams.txt
@@ -0,0 +1,14 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 2 - Scalar Data
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure
+----------- ------------ -------------- -------
+ent.vhd entity ent sample Figure 2-1
+int_types.vhd package int_types -- Section 2.2
+small_adder.vhd entity small_adder -- Section 2.2
+inline_01a.vhd entity inline_01a test Sections 2.1-2.5
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/inline_01a.vhd
new file mode 100644
index 000000000..f9c854be4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/inline_01a.vhd
@@ -0,0 +1,784 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01a is
+
+end entity inline_01a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01a is
+begin
+
+
+ section_1_a : process is
+
+ -- code from book:
+
+ constant number_of_bytes : integer := 4;
+ constant number_of_bits : integer := 8 * number_of_bytes;
+ constant e : real := 2.718281828;
+ constant prop_delay : time := 3 ns;
+ constant q : real := 1.60218E-19;
+ constant resistivity : real := 2.5E5;
+
+ --
+
+ variable index : integer := 0;
+ variable temperature : real;
+ variable start, finish : time := 0 ns;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_1_a;
+
+
+ ----------------
+
+
+ section_1_b : process is
+
+ -- code from book:
+
+ variable start : time := 0 ns;
+ variable finish : time := 0 ns;
+
+ -- end of code from book
+
+ variable program_counter : integer;
+ variable index : integer;
+ variable resonance_frequency : real;
+ constant L, C : real := 0.0;
+
+ begin
+
+ -- code from book:
+
+ program_counter := 0;
+ index := index + 1;
+ resonance_frequency := L * C;
+
+ -- end of code from book
+
+ wait;
+ end process section_1_b;
+
+
+ ----------------
+
+
+ section_2_a : process is
+
+ -- code from book:
+
+ type apples is range 0 to 100;
+ type oranges is range 0 to 100;
+
+ --
+
+ type day_of_month is range 0 to 31;
+ type year is range 0 to 2100;
+
+ variable today : day_of_month := 9;
+ variable start_year : year := 1987;
+
+ --
+
+ constant number_of_bits : integer := 32;
+ type bit_index is range 0 to number_of_bits - 1;
+
+ --
+
+ type set_index_range is range 21 downto 11;
+ type mode_pos_range is range 5 to 7;
+ variable set_index : set_index_range;
+ variable mode_pos : mode_pos_range;
+
+ --
+
+ type input_level is range -10.0 to +10.0;
+ type probability is range 0.0 to 1.0;
+
+ --
+
+ variable input_A : input_level;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ -- error: Incompatible types for assignment
+ -- start_year := today;
+
+ -- end of code from book
+
+ wait;
+ end process section_2_a;
+
+
+ ----------------
+
+
+ section_2_b : process is
+
+ -- code from book:
+
+ type resistance is range 0 to 1E9
+ units
+ ohm;
+ end units resistance;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_2_b;
+
+
+ ----------------
+
+
+ section_2_c : process is
+
+ -- code from book:
+
+ type resistance is range 0 to 1E9
+ units
+ ohm;
+ kohm = 1000 ohm;
+ Mohm = 1000 kohm;
+ end units resistance;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_2_c;
+
+
+ ----------------
+
+
+ section_2_d : process is
+
+ -- code from book:
+
+ type length is range 0 to 1E9
+ units
+ um; -- primary unit: micron
+ mm = 1000 um; -- metric units
+ m = 1000 mm;
+ inch = 25400 um; -- imperial units
+ foot = 12 inch;
+ end units length;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_2_d;
+
+
+ ----------------
+
+
+ section_2_e : process is
+
+ -- code from book:
+
+ -- type time is range implementation_defined
+ type time is range integer'low to integer'high
+ units
+ fs;
+ ps = 1000 fs;
+ ns = 1000 ps;
+ us = 1000 ns;
+ ms = 1000 us;
+ sec = 1000 ms;
+ min = 60 sec;
+ hr = 60 min;
+ end units;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_2_e;
+
+
+ ----------------
+
+
+ section_2_f : process is
+
+ -- code from book:
+
+ type transistor_region is (linear, saturation);
+
+ --
+
+ type octal_digit is ('0', '1', '2', '3', '4', '5', '6', '7');
+
+ --
+
+ variable transistor_state : transistor_region;
+ variable last_digit : octal_digit := '0';
+
+ --
+
+ type logic_level is (unknown, low, undriven, high);
+ variable control : logic_level;
+ type water_level is (dangerously_low, low, ok);
+ variable water_sensor : water_level;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ transistor_state := linear;
+ last_digit := '7';
+
+ --
+
+ control := low;
+ water_sensor := low;
+
+ -- end of code from book
+
+ wait;
+ end process section_2_f;
+
+
+ ----------------
+
+
+ section_2_g : process is
+
+ -- code from book:
+
+ type severity_level is (note, warning, error, failure);
+ type file_open_status is (open_ok, status_error, name_error, mode_error);
+ type file_open_kind is (read_mode, write_mode, append_mode);
+ type domain_type is (quiescent_domain, time_domain, frequency_domain);
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_2_g;
+
+
+ ----------------
+
+
+ section_2_g1 : process is
+
+ -- code from book:
+
+ type character is (
+ nul, soh, stx, etx, eot, enq, ack, bel,
+ bs, ht, lf, vt, ff, cr, so, si,
+ dle, dc1, dc2, dc3, dc4, nak, syn, etb,
+ can, em, sub, esc, fsp, gsp, rsp, usp,
+ ' ', '!', '"', '#', '$', '%', '&', ''',
+ '(', ')', '*', '+', ',', '-', '.', '/',
+ '0', '1', '2', '3', '4', '5', '6', '7',
+ '8', '9', ':', ';', '<', '=', '>', '?',
+ '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
+ 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
+ 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
+ 'X', 'Y', 'Z', '[', '\', ']', '^', '_',
+ '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
+ 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
+ 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
+ 'x', 'y', 'z', '{', '|', '}', '~', DEL,
+ c128, c129, c130, c131, c132, c133, c134, c135,
+ c136, c137, c138, c139, c140, c141, c142, c143,
+ c144, c145, c146, c147, c148, c149, c150, c151,
+ c152, c153, c154, c155, c156, c157, c158, c159,
+ ' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
+ '¨', '©', 'ª', '«', '¬', '­', '®', '¯',
+ '°', '±', '²', '³', '´', 'µ', '¶', '·',
+ '¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
+ 'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
+ 'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
+ 'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
+ 'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
+ 'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
+ 'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
+ 'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
+ 'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ');
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_2_g1;
+
+
+ ----------------
+
+
+ section_2_h : process is
+
+ -- code from book:
+
+ variable cmd_char, terminator : character;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ cmd_char := 'P';
+ terminator := cr;
+
+ -- end of code from book
+
+ wait;
+ end process section_2_h;
+
+
+ ----------------
+
+
+ section_2_i : process is
+
+ -- code from book:
+
+ type boolean is (false, true);
+
+ --
+
+ type bit is ('0', '1');
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_2_i;
+
+
+ ----------------
+
+
+ section_2_j : process is
+
+ variable write_enable_n, select_reg_n, write_reg_n : bit;
+
+ begin
+
+ -- code from book:
+
+ write_reg_n := not ( not write_enable_n and not select_reg_n );
+
+ -- end of code from book
+
+ wait;
+ end process section_2_j;
+
+
+ ----------------
+
+
+ section_2_k : process is
+
+ -- code from book:
+
+ type std_ulogic is ( 'U', -- Uninitialized
+ 'X', -- Forcing Unknown
+ '0', -- Forcing zero
+ '1', -- Forcing one
+ 'Z', -- High Impedance
+ 'W', -- Weak Unknown
+ 'L', -- Weak zero
+ 'H', -- Weak one
+ '-' ); -- Don't care
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_2_k;
+
+
+ ----------------
+
+
+ section_3_a : process is
+
+ -- code from book:
+
+ subtype small_int is integer range -128 to 127;
+
+ --
+
+ variable deviation : small_int;
+ variable adjustment : integer;
+
+ --
+
+ subtype bit_index is integer range 31 downto 0;
+
+ -- end of code from book
+
+ begin
+
+ deviation := 0;
+ adjustment := 0;
+
+ -- code from book:
+
+ deviation := deviation + adjustment;
+
+ -- end of code from book
+
+ wait;
+ end process section_3_a;
+
+
+ ----------------
+
+
+ section_3_b : process is
+
+ constant highest_integer : integer := integer'high;
+
+ constant highest_time : time := time'high;
+
+ -- code from book:
+
+ subtype pressure is real tolerance "default_pressure";
+
+ --
+
+ subtype natural is integer range 0 to highest_integer;
+ subtype positive is integer range 1 to highest_integer;
+
+ --
+
+ subtype delay_length is time range 0 fs to highest_time;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_3_b;
+
+
+ ----------------
+
+
+ section_3_c : process is
+
+ -- code from book:
+
+ type logic_level is (unknown, low, undriven, high);
+ type transistor_state is (unknown, unsaturated, saturated);
+
+ --
+
+ subtype valid_level is logic_level range low to high;
+
+ -- end of code from book
+
+ begin
+ wait;
+ end process section_3_c;
+
+
+ ----------------
+
+
+ section_4_a : block is
+
+ -- code from book:
+
+ subtype voltage is real tolerance "default_voltage";
+ subtype current is real tolerance "default_current";
+
+ nature electrical is
+ voltage across
+ current through
+ electrical_ref reference;
+
+ --
+
+ terminal in_plus, in_minus, preamp_out : electrical;
+
+ --
+
+ quantity signal_level across in_plus to in_minus;
+ quantity output_level across output_current through preamp_out;
+
+ -- end of code from book
+
+ begin
+ end block section_4_a;
+
+
+ ----------------
+
+
+ section_4_b : block is
+
+ -- code from book:
+
+ subtype temperature is real tolerance "default_temperature";
+ subtype heat_flow is real tolerance "default_heat_flow";
+ subtype cryo_temp is real tolerance "default_temperature";
+ subtype cryo_flow is real tolerance "default_heat_flow";
+
+ nature thermal is
+ temperature across
+ heat_flow through
+ thermal_ref reference;
+
+ nature cryogenic is
+ cryo_temp across
+ cryo_flow through
+ cryo_ref reference;
+
+ --
+
+ subtype illuminance is real tolerance "default_illuminance";
+ subtype optic_flux is real tolerance "default_optic_flux";
+
+ nature radiant is
+ illuminance across
+ optic_flux through
+ radiant_ref reference;
+
+ -- end of code from book
+
+ begin
+ end block section_4_b;
+
+
+ ----------------
+
+
+ section_4_c : block is
+
+ subtype voltage is real tolerance "default_voltage";
+ subtype current is real tolerance "default_current";
+
+ nature electrical is
+ voltage across
+ current through
+ electrical_ref reference;
+
+ -- code from book:
+
+ subnature coarse_electrical is electrical
+ tolerance "coarse_voltage" across "coarse_current" through;
+
+ terminal supply_plus, supply_minus : coarse_electrical;
+ terminal bias : electrical;
+
+ quantity bias_pullup_v across supply_plus to bias;
+ quantity bias_pulldown_v across bias to supply_minus;
+
+ -- end of code from book
+
+ begin
+ end block section_4_c;
+
+
+----------------
+
+
+ section_5_a : process is
+
+ -- code from book:
+
+ type resistance is range 0 to 1E9
+ units
+ ohm;
+ kohm = 1000 ohm;
+ Mohm = 1000 kohm;
+ end units resistance;
+
+ type set_index_range is range 21 downto 11;
+
+ type logic_level is (unknown, low, undriven, high);
+
+ -- end of code from book
+
+ begin
+
+ -- output from vsim: "2000"
+ report resistance'image(2 kohm);
+
+ -- code from book:
+
+ assert resistance'left = 0 ohm;
+ assert resistance'right = 1E9 ohm;
+ assert resistance'low = 0 ohm;
+ assert resistance'high = 1E9 ohm;
+ assert resistance'ascending = true;
+ assert resistance'image(2 kohm) = "2000 ohm";
+ assert resistance'value("5 Mohm") = 5_000_000 ohm;
+
+ assert set_index_range'left = 21;
+ assert set_index_range'right = 11;
+ assert set_index_range'low = 11;
+ assert set_index_range'high = 21;
+ assert set_index_range'ascending = false;
+ assert set_index_range'image(14) = "14";
+ assert set_index_range'value("20") = 20;
+
+ assert logic_level'left = unknown;
+ assert logic_level'right = high;
+ assert logic_level'low = unknown;
+ assert logic_level'high = high;
+ assert logic_level'ascending = true;
+ assert logic_level'image(undriven) = "undriven";
+ assert logic_level'value("Low") = low;
+
+ --
+
+ assert logic_level'pos(unknown) = 0;
+ assert logic_level'val(3) = high;
+ assert logic_level'succ(unknown) = low;
+ assert logic_level'pred(undriven) = low;
+
+ --
+
+ assert time'pos(4 ns) = 4_000_000;
+
+ -- end of code from book
+
+ wait;
+ end process section_5_a;
+
+
+ ----------------
+
+
+ section_5_b : process is
+
+ -- code from book:
+
+ type length is range integer'low to integer'high
+ units
+ mm;
+ end units length;
+
+ type area is range integer'low to integer'high
+ units
+ square_mm;
+ end units area;
+
+ --
+
+ variable L1, L2 : length;
+ variable A : area;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ -- error: No feasible entries for infix op: "*"
+ -- A := L1 * L2; -- this is incorrect
+
+ --
+
+ A := area'val( length'pos(L1) * length'pos(L2) );
+
+ -- end of code from book
+
+ wait;
+ end process section_5_b;
+
+
+ ----------------
+
+
+ section_5_c : process is
+
+ -- code from book:
+
+ subtype voltage is real tolerance "default_voltage";
+ subtype high_current is real tolerance "coarse_current";
+
+ --
+
+ type gear is (unknown, park, reverse, neutral, first, second, third, fourth, fifth);
+ subtype forward is gear range first to fifth;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ assert voltage'tolerance = "default_voltage";
+ assert high_current'tolerance = "coarse_current";
+
+ --
+
+ assert forward'base'left = unknown;
+ assert forward'base'succ(reverse) = neutral;
+
+ -- end of code from book
+
+ wait;
+ end process section_5_c;
+
+
+ ----------------
+
+
+ section_5_d : block is
+
+
+ -- code from book:
+
+ subtype displacement is real tolerance "default_displacement";
+ subtype force is real tolerance "default_force";
+ nature translational is
+ displacement across
+ force through
+ translational_ref reference;
+
+ --
+
+ quantity qdisp : translational'across; -- declares quantity of type displacement
+ quantity qforce : translational'through; -- declares quantity of type force
+
+ -- end of code from book
+
+ begin
+ end block section_5_d;
+
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/int_types.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/int_types.vhd
new file mode 100644
index 000000000..90a87fd30
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/int_types.vhd
@@ -0,0 +1,24 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+package int_types is
+
+ type small_int is range 0 to 255;
+
+end package int_types;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/small_adder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/small_adder.vhd
new file mode 100644
index 000000000..8edf4dd63
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/small_adder.vhd
@@ -0,0 +1,24 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+use work.int_types.all;
+
+entity small_adder is
+ port ( a, b : in small_int; s : out small_int );
+end entity small_adder;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/SR_flipflop.vhd
new file mode 100644
index 000000000..5715c84ef
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/SR_flipflop.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity SR_flipflop is
+ port ( S, R : in bit; Q : out bit );
+end entity SR_flipflop;
+
+--------------------------------------------------
+
+architecture checking of SR_flipflop is
+begin
+
+ set_reset : process (S, R) is
+ begin
+ assert S = '1' nand R = '1';
+ if S = '1' then
+ Q <= '1';
+ end if;
+ if R = '1' then
+ Q <= '0';
+ end if;
+ end process set_reset;
+
+end architecture checking;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd
new file mode 100644
index 000000000..508f6835d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity cos is
+ port ( theta : in real; result : out real );
+end entity cos;
+
+--------------------------------------------------
+
+architecture series of cos is
+begin
+
+ summation : process (theta) is
+ variable sum, term : real;
+ variable n : natural;
+ begin
+ sum := 1.0;
+ term := 1.0;
+ n := 0;
+ while abs term > abs (sum / 1.0E6) loop
+ n := n + 2;
+ term := (-term) * theta**2 / real(((n-1) * n));
+ sum := sum + term;
+ end loop;
+ result <= sum;
+ end process summation;
+
+end architecture series;
+
+
+architecture fixed_length_series of cos is
+begin
+
+ summation : process (theta) is
+ variable sum, term : real;
+ begin
+ sum := 1.0;
+ term := 1.0;
+ for n in 1 to 9 loop
+ term := (-term) * theta**2 / real(((2*n-1) * 2*n));
+ sum := sum + term;
+ end loop;
+ result <= sum;
+ end process summation;
+
+end architecture fixed_length_series;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter-1.vhd
new file mode 100644
index 000000000..359a22ead
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter-1.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity counter is
+ port ( clk, reset : in bit; count : out natural );
+end entity counter;
+
+--------------------------------------------------
+
+architecture behavior of counter is
+begin
+
+ incrementer : process is
+ variable count_value : natural := 0;
+ begin
+ count <= count_value;
+ loop
+ loop
+ wait until clk = '1' or reset = '1';
+ exit when reset = '1';
+ count_value := (count_value + 1) mod 16;
+ count <= count_value;
+ end loop;
+ -- at this point, reset = '1'
+ count_value := 0;
+ count <= count_value;
+ wait until reset = '0';
+ end loop;
+ end process incrementer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd
new file mode 100644
index 000000000..37c586cfc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity counter is
+ port ( clk : in bit; count : out natural );
+end entity counter;
+
+--------------------------------------------------
+
+architecture behavior of counter is
+begin
+
+ incrementer : process is
+ variable count_value : natural := 0;
+ begin
+ count <= count_value;
+ loop
+ wait until clk = '1';
+ count_value := (count_value + 1) mod 16;
+ count <= count_value;
+ end loop;
+ end process incrementer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/edge_triggered_register.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/edge_triggered_register.vhd
new file mode 100644
index 000000000..b8bdf9b76
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/edge_triggered_register.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity edge_triggered_register is
+ port ( clock : in bit;
+ d_in : in real; d_out : out real );
+end entity edge_triggered_register;
+
+--------------------------------------------------
+
+architecture check_timing of edge_triggered_register is
+begin
+
+ store_and_check : process (clock) is
+ variable stored_value : real;
+ variable pulse_start : time;
+ begin
+ case clock is
+ when '1' =>
+ pulse_start := now;
+ stored_value := d_in;
+ d_out <= stored_value;
+ when '0' =>
+ assert now = 0 ns or (now - pulse_start) >= 5 ns
+ report "clock pulse too short";
+ end case;
+ end process store_and_check;
+
+end architecture check_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/index-ams.txt
new file mode 100644
index 000000000..25a2efcee
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/index-ams.txt
@@ -0,0 +1,47 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 3 - Sequential Statements
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure
+----------- ------------ -------------- -------
+thermostat-1.vhd entity thermostat example Figure 3-1
+mux4.vhd package mux4_types body Section 3.2
+-- entity mux4 demo Figure 3-2
+counter.vhd entity counter behavior Figure 3-3
+counter-1.vhd entity counter behavior Figure 3-4
+cos.vhd entity cos series Figure 3-5
+-- fixed_length_series Figure 3-6
+SR_flipflop.vhd entity SR_flipflop checking Figure 3-7
+max3.vhd entity max3 check_error Figure 3-8
+edge_triggered_register.vhd entity edge_triggered_register check_timing Figure 3-9
+inline_01.vhd entity inline_01 test Section 3.1
+inline_02.vhd entity inline_02 test Section 3.1
+inline_03.vhd entity inline_03 test Section 3.1
+inline_04a.vhd entity inline_04a test Section 3.1
+inline_05.vhd entity inline_05 test Section 3.1
+inline_06.vhd entity inline_06 test Section 3.2
+inline_07.vhd entity inline_07 test Section 3.2
+inline_08.vhd entity inline_08 test Section 3.2
+inline_09.vhd entity inline_09 test Section 3.2
+inline_10a.vhd entity inline_10a test Section 3.3
+inline_11.vhd entity inline_11 test Section 3.3
+inline_12.vhd entity inline_12 test Section 3.4
+inline_13.vhd entity inline_13 test Section 3.4
+inline_14.vhd entity inline_14 test Section 3.4
+inline_15.vhd entity inline_15 test Section 3.4
+inline_16.vhd entity inline_16 test Section 3.4
+inline_17.vhd entity inline_17 test Section 3.4
+inline_18.vhd entity inline_18 test Section 3.5
+inline_19.vhd entity inline_19 test Section 3.5
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_mux4.vhd entity tb_mux4 test_demo mux4.vhd
+tb_counter.vhd entity tb_counter test_behavior counter.vhd
+tb_counter-1.vhd entity tb_counter test_behavior counter-1.vhd
+tb_cos.vhd entity tb_cos test_series cos.vhd
+tb_cos-1.vhd entity tb_cos test_fixed_length_series cos.vhd
+tb_SR_flipflop.vhd tb_SR_flipflop test_checking SR_flipflop.vhd
+tb_max3.vhd entity tb_max3 test_check_error max3.vhd
+tb_edge_triggered_register.vhd entity tb_edge_triggered_register test_check_timing edge_triggered_register.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_01.vhd
new file mode 100644
index 000000000..022459e6d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_01.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+
+ signal en : bit := '0';
+ signal data_in : integer := 0;
+
+begin
+
+ process_1_a : process (en, data_in) is
+
+ variable stored_value : integer := 0;
+
+ begin
+
+ -- code from book:
+
+ if en = '1' then
+ stored_value := data_in;
+ end if;
+
+ -- end of code from book
+
+ end process process_1_a;
+
+ stimulus : process is
+ begin
+ en <= '1' after 10 ns, '0' after 20 ns;
+ data_in <= 1 after 5 ns, 2 after 15 ns, 3 after 25 ns;
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd
new file mode 100644
index 000000000..fa2e3249e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+
+ signal sel : integer range 0 to 1 := 0;
+ signal input_0 : integer := 0;
+ signal input_1 : integer := 10;
+ signal result : integer;
+
+begin
+
+ process_1_b : process (sel, input_0, input_1) is
+ begin
+
+ -- code from book:
+
+ if sel = 0 then
+ result <= input_0; -- executed if sel = 0
+ else
+ result <= input_1; -- executed if sel /= 0
+ end if;
+
+ -- end of code from book
+
+ end process process_1_b;
+
+ stimulus : process is
+ begin
+ sel <= 1 after 40 ns;
+ input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
+ input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd
new file mode 100644
index 000000000..f997c913b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+begin
+
+ process_1_c : process is
+
+ type mode_type is (immediate, other_mode);
+ type opcode_type is (load, add, subtract, other_opcode);
+
+ variable mode : mode_type;
+ variable opcode : opcode_type;
+ constant immed_operand : integer := 1;
+ constant memory_operand : integer := 2;
+ constant address_operand : integer := 3;
+ variable operand : integer;
+
+ procedure procedure_1_c is
+ begin
+
+ -- code from book:
+
+ if mode = immediate then
+ operand := immed_operand;
+ elsif opcode = load or opcode = add or opcode = subtract then
+ operand := memory_operand;
+ else
+ operand := address_operand;
+ end if;
+
+ -- end of code from book
+
+ end procedure_1_c;
+
+ begin
+ mode := immediate;
+ procedure_1_c;
+
+ mode := other_mode;
+ opcode := load;
+ procedure_1_c;
+
+ opcode := add;
+ procedure_1_c;
+
+ opcode := subtract;
+ procedure_1_c;
+
+ opcode := other_opcode;
+ procedure_1_c;
+
+ wait;
+ end process process_1_c;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_04a.vhd
new file mode 100644
index 000000000..ae1c5af6b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_04a.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04a is
+
+ type gear_type is (gear_1, gear_2, neutral);
+ signal gear : gear_type := gear_1;
+
+ signal gear_engaged : boolean := false;
+
+begin
+
+ process_1_d : process (gear) is
+
+ variable max_acceleration : real := 0.0;
+ variable reverse_indicator : boolean := true;
+
+ begin
+
+ -- code from book:
+
+ if gear = neutral then
+ max_acceleration := 0.0;
+ reverse_indicator := false;
+ gear_engaged <= false;
+ end if;
+
+ -- end of code from book
+
+ end process process_1_d;
+
+ stimulus : process is
+ begin
+ gear <= gear_2 after 100 ns, neutral after 200 ns;
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_05.vhd
new file mode 100644
index 000000000..30c27654a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_05.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+ type phase_type is (wash, other_phase);
+ signal phase : phase_type := other_phase;
+
+ type cycle_type is (delicate_cycle, other_cycle);
+ signal cycle_select : cycle_type := delicate_cycle;
+
+ type speed_type is (slow, fast);
+ signal agitator_speed : speed_type := slow;
+
+ signal agitator_on : boolean := false;
+
+begin
+
+ process_1_e : process (phase, cycle_select) is
+ begin
+
+ -- code from book:
+
+ if phase = wash then
+ if cycle_select = delicate_cycle then
+ agitator_speed <= slow;
+ else
+ agitator_speed <= fast;
+ end if;
+ agitator_on <= true;
+ end if;
+
+ -- end of code from book
+
+ end process process_1_e;
+
+ stimulus : process is
+ begin
+ cycle_select <= other_cycle; wait for 100 ns;
+ phase <= wash; wait for 100 ns;
+ cycle_select <= delicate_cycle; wait for 100 ns;
+ cycle_select <= other_cycle; wait for 100 ns;
+ phase <= other_phase; wait for 100 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_06.vhd
new file mode 100644
index 000000000..5fb91e479
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_06.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+ -- code from book:
+
+ type alu_func is (pass1, pass2, add, subtract);
+
+ -- end of code from book
+
+ signal func : alu_func := pass1;
+ signal operand1 : integer := 10;
+ signal operand2 : integer := 3;
+
+begin
+
+ process_2_a : process (func, operand1, operand2) is
+
+ variable result : integer := 0;
+
+ begin
+
+ -- code from book:
+
+ case func is
+ when pass1 =>
+ result := operand1;
+ when pass2 =>
+ result := operand2;
+ when add =>
+ result := operand1 + operand2;
+ when subtract =>
+ result := operand1 - operand2;
+ end case;
+
+ -- end of code from book
+
+ end process process_2_a;
+
+
+ stimulus : process is
+ begin
+ func <= pass2 after 10 ns,
+ add after 20 ns,
+ subtract after 30 ns;
+ wait;
+ end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_07.vhd
new file mode 100644
index 000000000..461363079
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_07.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_07 is
+begin
+
+ process_2_b : process is
+
+ -- code from book:
+
+ subtype index_mode is integer range 0 to 3;
+
+ variable instruction_register : integer range 0 to 2**16 - 1;
+
+ -- end of code from book
+
+ variable index_value : integer;
+ constant accumulator_A : integer := 1;
+ constant accumulator_B : integer := 2;
+ constant index_register : integer := 3;
+
+ begin
+
+ for i in index_mode loop
+ instruction_register := i * 2**12;
+
+ -- code from book:
+
+ case index_mode'((instruction_register / 2**12) rem 2**2) is
+ when 0 =>
+ index_value := 0;
+ when 1 =>
+ index_value := accumulator_A;
+ when 2 =>
+ index_value := accumulator_B;
+ when 3 =>
+ index_value := index_register;
+ end case;
+
+ -- end of code from book
+
+ end loop;
+
+ wait;
+ end process process_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_08.vhd
new file mode 100644
index 000000000..7c5496ad7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_08.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_08 is
+begin
+
+ process_2_c : process is
+
+ -- code from book:
+
+ type opcodes is
+ (nop, add, subtract, load, store, jump, jumpsub, branch, halt);
+
+ subtype control_transfer_opcodes is opcodes range jump to branch;
+
+ -- end of code from book
+
+ variable opcode : opcodes;
+ variable operand : integer;
+ constant memory_operand : integer := 1;
+ constant address_operand : integer := 2;
+
+ begin
+
+ for i in opcodes loop
+ opcode := i;
+
+ -- code from book:
+
+ case opcode is
+ when load | add | subtract =>
+ operand := memory_operand;
+ when store | jump | jumpsub | branch =>
+ operand := address_operand;
+ when others =>
+ operand := 0;
+ end case;
+
+ --
+
+ case opcode is
+ when add to load =>
+ operand := memory_operand;
+ when branch downto store =>
+ operand := address_operand;
+ when others =>
+ operand := 0;
+ end case;
+
+ -- end of code from book
+
+ case opcode is
+ when add to load =>
+ operand := memory_operand;
+ -- code from book:
+ when control_transfer_opcodes | store =>
+ operand := address_operand;
+ -- end of code from book
+ when others =>
+ operand := 0;
+ end case;
+
+ end loop;
+
+ wait;
+ end process process_2_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd
new file mode 100644
index 000000000..9539cca2c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+begin
+
+
+ process_2_d : process is
+
+ -- code from book:
+
+ variable N : integer := 1;
+
+ --
+
+ constant C : integer := 1;
+
+ -- end of code from book
+
+ constant expression : integer := 7;
+
+ begin
+
+ -- code from book:
+
+ -- error: Case choice must be a locally static expression
+
+ -- case expression is -- example of an illegal case statement
+ -- when N | N+1 => -- . . .
+ -- when N+2 to N+5 => -- . . .
+ -- when others => -- . . .
+ -- end case;
+
+ --
+
+ case expression is
+ when C | C+1 => -- . . .
+ when C+2 to C+5 => -- . . .
+ when others => -- . . .
+ end case;
+
+ -- end of code from book
+
+ wait;
+ end process process_2_d;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd
new file mode 100644
index 000000000..8911f431f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_10a is
+
+end entity inline_10a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_10a is
+
+ -- code from book:
+
+ type stick_position is (down, center, up);
+
+ -- end of code from book
+
+ signal throttle : stick_position;
+
+begin
+
+
+ process_3_a : process (throttle) is
+
+ variable speed : integer := 0;
+ constant decrement : integer := 1;
+ constant increment : integer := 1;
+
+ begin
+
+ -- code from book:
+
+ case throttle is
+ when down =>
+ speed := speed - decrement;
+ when up =>
+ speed := speed + increment;
+ when center =>
+ null; -- no change to speed
+ end case;
+
+ -- end of code from book
+
+ end process process_3_a;
+
+
+ stimulus : process is
+ begin
+ throttle <= down after 10 ns, center after 20 ns, up after 30 ns;
+ wait;
+ end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd
new file mode 100644
index 000000000..a03dfa75d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_11 is
+
+end entity inline_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_11 is
+
+ signal sensitivity_list : bit := '0';
+
+begin
+
+
+ -- code from book:
+
+ -- make "sensitivity_list" roman italic
+ control_section : process ( sensitivity_list ) is
+ begin
+ null;
+ end process control_section;
+
+ -- end of code from book
+
+ stimulus : process is
+ begin
+ sensitivity_list <= '1' after 10 ns, '0' after 20 ns;
+ wait;
+ end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_12.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_12.vhd
new file mode 100644
index 000000000..c6170470c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_12.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_12 is
+
+end entity inline_12;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_12 is
+begin
+
+
+ process_4_a : process is
+
+ constant condition, condition_1,
+ condition_2, condition_3 : boolean := true;
+ variable index : integer;
+
+ begin
+
+ -- code from book: syntax check only
+
+ -- change "condition" to roman italic
+
+ -- not in book:
+ loop
+ -- end not in book
+
+ if condition then
+ exit;
+ end if;
+
+ -- not in book:
+ end loop;
+ -- end not in book
+
+ --
+
+ -- change "condition" to roman italic
+
+ loop
+ -- . . .
+ exit when condition;
+ -- . . .
+ end loop;
+ -- . . . -- control transferred to here
+ -- when condition becomes true within the loop
+
+ --
+
+ loop_name : loop
+ -- . . .
+ exit loop_name;
+ -- . . .
+ end loop loop_name ;
+
+ --
+
+ -- change conditions to roman italic with hyphens
+
+ outer : loop
+ -- . . .
+ inner : loop
+ -- . . .
+ exit outer when condition_1; -- exit 1
+ -- . . .
+ exit when condition_2; -- exit 2
+ -- . . .
+ end loop inner;
+ -- . . . -- target A
+ exit outer when condition_3; -- exit 3
+ -- . . .
+ end loop outer;
+ -- . . . -- target B
+
+ --
+
+ -- "statement..." in roman italic with hyphens
+
+ loop
+ -- statement_1;
+ next when condition;
+ -- statement_2;
+ end loop;
+
+ --
+
+ -- "statement..." in roman italic with hyphens
+
+ loop
+ -- statement_1;
+ if not condition then
+ -- statement_2;
+ end if;
+ end loop;
+
+ --
+
+ while index > 0 loop
+ -- . . . -- statement A: do something with index
+ end loop;
+ -- . . . -- statement B
+
+
+ -- end of code from book
+
+ wait;
+ end process process_4_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_13.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_13.vhd
new file mode 100644
index 000000000..b2ab59683
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_13.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_13 is
+
+end entity inline_13;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_13 is
+
+ signal count_out : integer;
+
+begin
+
+
+ process_4_b : process is
+ begin
+
+ -- code from book:
+
+ for count_value in 0 to 127 loop
+ count_out <= count_value;
+ wait for 5 ns;
+ end loop;
+
+ -- end of code from book
+
+ wait;
+ end process process_4_b;
+
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_14.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_14.vhd
new file mode 100644
index 000000000..09ee78785
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_14.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_14 is
+
+end entity inline_14;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_14 is
+
+ -- code from book:
+
+ type controller_state is (initial, idle, active, error);
+
+ -- end of code from book
+
+ signal current_state : controller_state := initial;
+
+begin
+
+
+ process_4_c : process is
+ begin
+
+ -- code from book:
+
+ for state in controller_state loop
+ -- . . .
+ -- not in book:
+ current_state <= state;
+ wait for 10 ns;
+ -- end not in book
+ end loop;
+
+ -- end of code from book
+
+ wait;
+ end process process_4_c;
+
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_15.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_15.vhd
new file mode 100644
index 000000000..70860667c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_15.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_15 is
+
+end entity inline_15;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_15 is
+begin
+
+ -- code from book:
+
+ erroneous : process is
+ variable i, j : integer;
+ begin
+ i := loop_param; -- error!
+ for loop_param in 1 to 10 loop
+ loop_param := 5; -- error!
+ end loop;
+ j := loop_param; -- error!
+ end process erroneous;
+
+ -- end of code from book
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_16.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_16.vhd
new file mode 100644
index 000000000..f75a6ce62
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_16.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_16 is
+
+end entity inline_16;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_16 is
+begin
+
+ -- code from book:
+
+ hiding_example : process is
+ variable a, b : integer;
+ begin
+ a := 10;
+ for a in 0 to 7 loop
+ b := a;
+ end loop;
+ -- a = 10, and b = 7
+ -- . . .
+ -- not in book:
+ wait;
+ -- end not in book
+ end process hiding_example;
+
+ -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_17.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_17.vhd
new file mode 100644
index 000000000..f4983840e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_17.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_17 is
+
+end entity inline_17;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_17 is
+begin
+
+
+ process_4_f : process is
+ begin
+
+ -- code from book:
+
+ for i in 10 to 1 loop
+ -- . . .
+ end loop;
+
+ for i in 10 downto 1 loop
+ -- . . .
+ end loop;
+
+ -- end of code from book
+
+ wait;
+ end process process_4_f;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd
new file mode 100644
index 000000000..87917a50e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_18 is
+
+end entity inline_18;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_18 is
+begin
+
+
+ process_5_a : process is
+
+ constant initial_value : natural := 10;
+ constant max_value : natural := 8;
+ constant current_character : character := 'A';
+ constant input_string : string := "012ABC";
+ constant free_memory : natural := 0;
+ constant low_water_limit : natural := 1024;
+ constant packet_length : natural := 0;
+ constant clock_pulse_width : delay_length := 10 ns;
+ constant min_clock_width : delay_length := 20 ns;
+ constant last_position : natural := 10;
+ constant first_position : natural := 5;
+ constant number_of_entries : natural := 0;
+
+ begin
+
+ -- code from book:
+
+ assert initial_value <= max_value;
+
+ --
+
+ assert initial_value <= max_value
+ report "initial value too large";
+
+ --
+
+ assert current_character >= '0' and current_character <= '9'
+ report "Input number " & input_string & " contains a non-digit";
+
+ --
+
+ assert free_memory >= low_water_limit
+ report "low on memory, about to start garbage collect"
+ severity note;
+
+ --
+
+ assert packet_length /= 0
+ report "empty network packet received"
+ severity warning;
+
+ --
+
+ assert clock_pulse_width >= min_clock_width
+ severity error;
+
+ --
+
+ assert (last_position - first_position + 1) = number_of_entries
+ report "inconsistency in buffer model"
+ severity failure;
+
+ -- end of code from book
+
+ wait;
+ end process process_5_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_19.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_19.vhd
new file mode 100644
index 000000000..6a3c9592f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_19.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_19 is
+
+end entity inline_19;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_19 is
+
+ subtype data_type is integer;
+
+ signal transmit_data : data_type := 0;
+
+begin
+
+
+ -- code from book:
+
+ transmit_element : process (transmit_data) is
+ -- . . . -- variable declarations
+ begin
+ report "transmit_element: data = "
+ & data_type'image(transmit_data);
+ -- . . .
+ end process transmit_element;
+
+ -- end of code from book
+
+
+ stimulus : process is
+ begin
+ transmit_data <= 10 after 10 ns, 20 after 20 ns;
+ wait;
+ end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/max3.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/max3.vhd
new file mode 100644
index 000000000..cf515d462
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/max3.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity max3 is
+ port ( a, b, c : in integer; z : out integer );
+end entity max3;
+
+--------------------------------------------------
+
+architecture check_error of max3 is
+begin
+
+ maximizer : process (a, b, c)
+ variable result : integer;
+ begin
+ if a > b then
+ if a > c then
+ result := a;
+ else
+ result := a; -- Oops! Should be: result := c;
+ end if;
+ elsif b > c then
+ result := b;
+ else
+ result := c;
+ end if;
+ assert result >= a and result >= b and result >= c
+ report "inconsistent result for maximum"
+ severity failure;
+ z <= result;
+ end process maximizer;
+
+end architecture check_error;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd
new file mode 100644
index 000000000..da1831913
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- test code:
+
+package mux4_types is
+
+ -- code from book:
+
+ type sel_range is range 0 to 3;
+
+ -- end of code from book
+
+end package mux4_types;
+
+
+
+use work.mux4_types.all;
+
+-- end test code
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity mux4 is
+ port ( sel : in sel_range;
+ d0, d1, d2, d3 : in std_ulogic;
+ z : out std_ulogic );
+end entity mux4;
+
+--------------------------------------------------
+
+architecture demo of mux4 is
+begin
+
+ out_select : process (sel, d0, d1, d2, d3) is
+ begin
+ case sel is
+ when 0 =>
+ z <= d0;
+ when 1 =>
+ z <= d1;
+ when 2 =>
+ z <= d2;
+ when 3 =>
+ z <= d3;
+ end case;
+ end process out_select;
+
+end architecture demo;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_SR_flipflop.vhd
new file mode 100644
index 000000000..dc67dcd56
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_SR_flipflop.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_SR_flipflop is
+
+end entity tb_SR_flipflop;
+
+
+----------------------------------------------------------------
+
+
+architecture test_checking of tb_SR_flipflop is
+
+ signal S, R, Q : bit := '0';
+
+begin
+
+ dut : entity work.SR_flipflop(checking)
+ port map ( S => S, R => R, Q => Q );
+
+ stumulus : process is
+
+ begin
+ wait for 10 ns;
+ S <= '1'; wait for 10 ns;
+ S <= '0'; wait for 10 ns;
+ S <= '1'; wait for 10 ns;
+ S <= '0'; wait for 10 ns;
+ R <= '1'; wait for 10 ns;
+ R <= '0'; wait for 10 ns;
+ R <= '1'; wait for 10 ns;
+ R <= '0'; wait for 10 ns;
+ S <= '1'; R <= '1'; wait for 10 ns;
+ R <= '0'; wait for 10 ns;
+ S <= '0'; wait for 10 ns;
+
+ wait;
+ end process stumulus;
+
+end architecture test_checking;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos-1.vhd
new file mode 100644
index 000000000..45799a0ab
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos-1.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_cos is
+
+end entity tb_cos;
+
+
+----------------------------------------------------------------
+
+
+architecture test_fixed_length_series of tb_cos is
+
+ signal theta, result : real := 0.0;
+
+begin
+
+ dut : entity work.cos(fixed_length_series)
+ port map ( theta => theta, result => result );
+
+ stimulus : process is
+
+ constant pi : real := 3.1415927;
+
+ begin
+ wait for 10 ns;
+ theta <= pi / 6.0; wait for 10 ns;
+ theta <= pi / 4.0; wait for 10 ns;
+ theta <= pi / 3.0; wait for 10 ns;
+ theta <= pi / 2.0; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test_fixed_length_series;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos.vhd
new file mode 100644
index 000000000..ab0afeabc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_cos is
+
+end entity tb_cos;
+
+
+----------------------------------------------------------------
+
+
+architecture test_series of tb_cos is
+
+ signal theta, result : real := 0.0;
+
+begin
+
+ dut : entity work.cos(series)
+ port map ( theta => theta, result => result );
+
+ stimulus : process is
+
+ constant pi : real := 3.1415927;
+
+ begin
+ wait for 10 ns;
+ theta <= pi / 6.0; wait for 10 ns;
+ theta <= pi / 4.0; wait for 10 ns;
+ theta <= pi / 3.0; wait for 10 ns;
+ theta <= pi / 2.0; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test_series;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd
new file mode 100644
index 000000000..383732ac9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_counter is
+
+end entity tb_counter;
+
+
+----------------------------------------------------------------
+
+
+architecture test_behavior of tb_counter is
+
+ signal clk, reset : bit := '0';
+ signal count : natural;
+
+begin
+
+ dut : entity work.counter(behavior)
+ port map ( clk => clk, reset => reset, count => count );
+
+ stimulus : process is
+ begin
+
+ for cycle_count in 1 to 5 loop
+ wait for 20 ns;
+ clk <= '1', '0' after 10 ns;
+ end loop;
+
+ reset <= '1' after 15 ns;
+ for cycle_count in 1 to 5 loop
+ wait for 20 ns;
+ clk <= '1', '0' after 10 ns;
+ end loop;
+
+ reset <= '0' after 15 ns;
+ for cycle_count in 1 to 30 loop
+ wait for 20 ns;
+ clk <= '1', '0' after 10 ns;
+ end loop;
+
+ wait;
+ end process stimulus;
+
+end architecture test_behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd
new file mode 100644
index 000000000..aa0dafcaa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_counter is
+
+end entity tb_counter;
+
+
+----------------------------------------------------------------
+
+
+architecture test_behavior of tb_counter is
+
+ signal clk : bit := '0';
+ signal count : natural;
+
+begin
+
+ dut : entity work.counter(behavior)
+ port map ( clk => clk, count => count );
+
+ stimulus : process is
+ begin
+ for cycle_count in 1 to 100 loop
+ wait for 20 ns;
+ clk <= '1', '0' after 10 ns;
+ end loop;
+
+ wait;
+ end process stimulus;
+
+end architecture test_behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_edge_triggered_register.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_edge_triggered_register.vhd
new file mode 100644
index 000000000..bacfd0250
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_edge_triggered_register.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_edge_triggered_register is
+
+end entity tb_edge_triggered_register;
+
+
+----------------------------------------------------------------
+
+
+architecture test_check_timing of tb_edge_triggered_register is
+
+ signal clock : bit := '0';
+ signal d_in, d_out : real := 0.0;
+
+begin
+
+ dut : entity work.edge_triggered_register(check_timing)
+ port map ( clock => clock, d_in => d_in, d_out => d_out );
+
+ stumulus : process is
+
+ begin
+ wait for 20 ns;
+
+ d_in <= 1.0; wait for 10 ns;
+ clock <= '1', '0' after 10 ns; wait for 20 ns;
+
+ d_in <= 2.0; wait for 10 ns;
+ clock <= '1', '0' after 5 ns; wait for 20 ns;
+
+ d_in <= 3.0; wait for 10 ns;
+ clock <= '1', '0' after 4 ns; wait for 20 ns;
+
+ wait;
+ end process stumulus;
+
+end architecture test_check_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_max3.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_max3.vhd
new file mode 100644
index 000000000..d8096eb50
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_max3.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_max3 is
+
+end entity tb_max3;
+
+
+----------------------------------------------------------------
+
+
+architecture test_check_error of tb_max3 is
+
+ signal a, b, c, z : integer := 0;
+
+begin
+
+ dut : entity work.max3(check_error)
+ port map ( a => a, b => b, c => c, z => z );
+
+ stumulus : process is
+
+ begin
+ wait for 10 ns;
+ a <= 7; wait for 10 ns;
+ b <= 10; wait for 10 ns;
+ c <= 15; wait for 10 ns;
+ a <= 12; wait for 10 ns;
+ a <= 20; wait for 10 ns;
+
+ wait;
+ end process stumulus;
+
+end architecture test_check_error;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_mux4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_mux4.vhd
new file mode 100644
index 000000000..5e76e43fd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_mux4.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_mux4 is
+
+end entity tb_mux4;
+
+
+----------------------------------------------------------------
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+
+architecture test_demo of tb_mux4 is
+
+ signal sel : work.mux4_types.sel_range := 0;
+ signal d0, d1, d2, d3, z : std_ulogic;
+
+begin
+
+ dut : entity work.mux4(demo)
+ port map ( sel => sel,
+ d0 => d0, d1 => d1, d2 => d2, d3 => d3,
+ z => z );
+
+ stimulus : process is
+ begin
+ wait for 5 ns;
+ d0 <= '1'; wait for 5 ns;
+ d1 <= 'H'; wait for 5 ns;
+ sel <= 1; wait for 5 ns;
+ d1 <= 'L'; wait for 5 ns;
+ sel <= 2; wait for 5 ns;
+ d0 <= '0'; wait for 5 ns;
+ d2 <= '1'; wait for 5 ns;
+ d2 <= '0'; wait for 5 ns;
+ sel <= 3; wait for 5 ns;
+ d3 <= '1'; wait for 5 ns;
+ d3 <= '0'; wait for 5 ns;
+
+ wait;
+ end process stimulus;
+
+end architecture test_demo;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/thermostat-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/thermostat-1.vhd
new file mode 100644
index 000000000..356e7d1f6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/thermostat-1.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.thermal_systems.all;
+
+entity thermostat is
+ port ( quantity sensor_temp : in temperature;
+ signal desired_temp : in real;
+ signal heater_on : out boolean );
+end entity thermostat;
+
+----------------------------------------------------
+
+architecture example of thermostat is
+begin
+
+ controller : process ( desired_temp,
+ sensor_temp'above(desired_temp + 2.0),
+ sensor_temp'above(desired_temp - 2.0) ) is
+ begin
+ if sensor_temp < desired_temp - 2.0 then
+ heater_on <= true;
+ elsif sensor_temp > desired_temp + 2.0 then
+ heater_on <= false;
+ end if;
+ end process controller;
+
+end architecture example;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/addu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/addu.vhd
new file mode 100644
index 000000000..377f266c4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/addu.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity addu is
+end entity addu;
+
+
+architecture test of addu is
+
+ subtype word32 is bit_vector(31 downto 0);
+
+ -- code in book
+
+ procedure addu ( a, b : in word32;
+ result : out word32; overflow : out boolean ) is
+ variable sum : word32;
+ variable carry : bit := '0';
+ begin
+ for index in sum'reverse_range loop
+ sum(index) := a(index) xor b(index) xor carry;
+ carry := ( a(index) and b(index) ) or ( carry and ( a(index) xor b(index) ) );
+ end loop;
+ result := sum;
+ overflow := carry = '1';
+ end procedure addu;
+
+ -- end code in book
+
+begin
+
+ stimulus : process is
+
+ -- code in book (in text)
+
+ variable PC, next_PC : word32;
+ variable overflow_flag : boolean;
+ -- . . .
+
+ -- end code in book
+
+ begin
+ PC := X"0000_0010";
+
+ -- code in book (in text)
+
+ addu ( PC, X"0000_0004", next_PC, overflow_flag);
+
+ -- end code in book
+
+ PC := X"FFFF_FFFC";
+ addu ( PC, X"0000_0004", next_PC, overflow_flag);
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/average_samples.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/average_samples.vhd
new file mode 100644
index 000000000..55d250c36
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/average_samples.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity average_sample is
+end entity average_sample;
+
+
+
+architecture test of average_sample is
+
+ procedure average_test is
+
+ variable average : real := 0.0;
+ type sample_array is array (positive range <>) of real;
+ constant samples : sample_array :=
+ ( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0 );
+
+ -- code from book
+
+ procedure average_samples is
+ variable total : real := 0.0;
+ begin
+ assert samples'length > 0 severity failure;
+ for index in samples'range loop
+ total := total + samples(index);
+ end loop;
+ average := total / real(samples'length);
+ end procedure average_samples;
+
+ -- end code from book
+
+ begin
+
+ -- code from book (in text)
+
+ average_samples;
+
+ -- end code from book
+
+ end procedure average_test;
+
+
+begin
+
+ average_test;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd
new file mode 100644
index 000000000..bbcf2835a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity bv_lt is
+end entity bv_lt;
+
+
+
+architecture test of bv_lt is
+
+ -- code from book
+
+ procedure bv_lt ( bv1, bv2 : in bit_vector; result : out boolean ) is
+ variable tmp1 : bit_vector(bv1'range) := bv1;
+ variable tmp2 : bit_vector(bv2'range) := bv2;
+ begin
+ tmp1(tmp1'left) := not tmp1(tmp1'left);
+ tmp2(tmp2'left) := not tmp2(tmp2'left);
+ result := tmp1 < tmp2;
+ end procedure bv_lt;
+
+ -- end code from book
+
+begin
+
+ stimulus : process is
+
+ subtype byte is bit_vector(0 to 7);
+ variable result : boolean;
+
+ begin
+ bv_lt( byte'(X"02"), byte'(X"04"), result );
+ assert result;
+
+ bv_lt( byte'(X"02"), byte'(X"02"), result );
+ assert not result;
+
+ bv_lt( byte'(X"02"), byte'(X"02"), result );
+ assert not result;
+
+ bv_lt( byte'(X"FC"), byte'(X"04"), result );
+ assert result;
+
+ bv_lt( byte'(X"04"), byte'(X"FC"), result );
+ assert not result;
+
+ bv_lt( byte'(X"FC"), byte'(X"FC"), result );
+ assert not result;
+
+ bv_lt( byte'(X"FC"), byte'(X"FE"), result );
+ assert result;
+
+ bv_lt( byte'(X"FE"), byte'(X"FC"), result );
+ assert not result;
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_to_natural.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_to_natural.vhd
new file mode 100644
index 000000000..94fe98267
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_to_natural.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity bv_to_natural is
+end entity bv_to_natural;
+
+
+
+architecture test of bv_to_natural is
+
+ -- code from book
+
+ function bv_to_natural ( bv : in bit_vector ) return natural is
+ variable result : natural := 0;
+ begin
+ for index in bv'range loop
+ result := result * 2 + bit'pos(bv(index));
+ end loop;
+ return result;
+ end function bv_to_natural;
+
+ -- end code from book
+
+ signal data : bit_vector(0 to 7);
+ constant address : bit_vector(0 to 3) := "0101";
+ constant Taccess : delay_length := 80 ns;
+
+begin
+
+ tester : process is
+
+ constant rom_size : natural := 8;
+ constant word_size : natural := 8;
+
+ -- code from book (in text)
+
+ type rom_array is array (natural range 0 to rom_size-1)
+ of bit_vector(0 to word_size-1);
+ variable rom_data : rom_array;
+
+ -- end code from book
+
+ begin
+
+ rom_data := (X"00", X"01", X"02", X"03", X"04", X"05", X"06", X"07");
+
+ -- code from book (in text)
+
+ data <= rom_data ( bv_to_natural(address) ) after Taccess;
+
+ -- end code from book
+
+ wait;
+ end process tester;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/cache.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/cache.vhd
new file mode 100644
index 000000000..9df92fcac
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/cache.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity cache is
+end entity cache;
+
+-- end not in book
+
+
+
+architecture behavioral of cache is
+ -- not in book
+ subtype word is bit_vector(0 to 31);
+ signal mem_addr : natural;
+ signal mem_data_in : word;
+ signal mem_read, mem_ack : bit := '0';
+ -- end not in book
+begin
+
+ behavior : process is
+
+ -- not in book
+ constant block_size : positive := 4;
+ type cache_block is array (0 to block_size - 1) of word;
+ type store_array is array (0 to 15) of cache_block;
+ variable data_store : store_array;
+ variable entry_index : natural := 1;
+ variable miss_base_address : natural := 16;
+ -- end not in book
+
+ -- . . .
+
+ procedure read_block( start_address : natural;
+ entry : out cache_block ) is
+
+ variable memory_address_reg : natural;
+ variable memory_data_reg : word;
+
+ procedure read_memory_word is
+ begin
+ mem_addr <= memory_address_reg;
+ mem_read <= '1';
+ wait until mem_ack = '1';
+ memory_data_reg := mem_data_in;
+ mem_read <= '0';
+ wait until mem_ack = '0';
+ end procedure read_memory_word;
+
+ begin -- read_block
+ for offset in 0 to block_size - 1 loop
+ memory_address_reg := start_address + offset;
+ read_memory_word;
+ entry(offset) := memory_data_reg;
+ end loop;
+ end procedure read_block;
+
+ begin -- behavior
+ -- . . .
+ read_block( miss_base_address, data_store(entry_index) );
+ -- . . .
+ -- not in book
+ wait;
+ -- end not in book
+ end process behavior;
+
+
+ -- not in book
+
+ memory : process is
+
+ type store_array is array (0 to 31) of word;
+ constant store : store_array :=
+ ( X"00000000", X"00000001", X"00000002", X"00000003",
+ X"00000004", X"00000005", X"00000006", X"00000007",
+ X"00000008", X"00000009", X"0000000a", X"0000000b",
+ X"0000000c", X"0000000d", X"0000000e", X"0000000f",
+ X"00000010", X"00000011", X"00000012", X"00000013",
+ X"00000014", X"00000015", X"00000016", X"00000017",
+ X"00000018", X"00000019", X"0000001a", X"0000001b",
+ X"0000001c", X"0000001d", X"0000001e", X"0000001f" );
+
+ begin
+ wait until mem_read = '1';
+ mem_data_in <= store(mem_addr);
+ mem_ack <= '1';
+ wait until mem_read = '0';
+ mem_ack <= '0';
+ end process memory;
+
+ -- end not in book
+
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/check_setup.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/check_setup.vhd
new file mode 100644
index 000000000..3c93af74a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/check_setup.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity check_setup is
+end entity check_setup;
+
+
+
+architecture test of check_setup is
+
+ -- code from book
+
+ procedure check_setup ( signal data, clock : in bit;
+ constant Tsu : in time ) is
+ begin
+ if clock'event and clock = '1' then
+ assert data'last_event >= Tsu
+ report "setup time violation" severity error;
+ end if;
+ end procedure check_setup;
+
+ -- end code from book
+
+ signal ready, phi2 : bit := '0';
+ constant Tsu_rdy_clk : delay_length := 4 ns;
+
+begin
+
+ -- code from book (in text)
+
+ check_ready_setup : check_setup ( data => ready, clock => phi2,
+ Tsu => Tsu_rdy_clk );
+
+ -- end code from book
+
+ clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0';
+
+ stimulus : ready <= '1' after 4 ns,
+ '0' after 56 ns,
+ '1' after 87 ns,
+ '0' after 130 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_processor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_processor.vhd
new file mode 100644
index 000000000..950971a89
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_processor.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity control_processor is
+ generic ( Tpd : delay_length := 3 ns );
+end entity control_processor;
+
+-- end not in book
+
+
+
+architecture rtl of control_processor is
+
+ type func_code is (add, subtract);
+
+ signal op1, op2, dest : integer;
+ signal Z_flag : boolean;
+ signal func : func_code;
+ -- . . .
+
+begin
+
+ alu : process is
+
+ procedure do_arith_op is
+ variable result : integer;
+ begin
+ case func is
+ when add =>
+ result := op1 + op2;
+ when subtract =>
+ result := op1 - op2;
+ end case;
+ dest <= result after Tpd;
+ Z_flag <= result = 0 after Tpd;
+ end procedure do_arith_op;
+
+ begin
+ -- . . .
+ do_arith_op;
+ -- . . .
+ -- not in book
+ wait on op1, op2, func;
+ -- end not in book
+ end process alu;
+
+ -- . . .
+
+ -- not in book
+
+ stimulus : process is
+ begin
+ op1 <= 0; op2 <= 0; wait for 10 ns;
+ op1 <= 10; op2 <= 3; wait for 10 ns;
+ func <= subtract; wait for 10 ns;
+ op2 <= 10; wait for 10 ns;
+
+ wait;
+ end process stimulus;
+
+ -- end not in book
+
+end architecture rtl;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_sequencer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_sequencer.vhd
new file mode 100644
index 000000000..521a2f672
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_sequencer.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity control_sequencer is
+end entity control_sequencer;
+
+
+
+architecture test of control_sequencer is
+
+ signal phase1, phase2, reg_file_write_en,
+ A_reg_out_en, B_reg_out_en, C_reg_load_en : bit := '0';
+
+begin
+
+ -- code from book
+
+ control_sequencer : process is
+
+ procedure control_write_back is
+ begin
+ wait until phase1 = '1';
+ reg_file_write_en <= '1';
+ wait until phase2 = '0';
+ reg_file_write_en <= '0';
+ end procedure control_write_back;
+
+ procedure control_arith_op is
+ begin
+ wait until phase1 = '1';
+ A_reg_out_en <= '1';
+ B_reg_out_en <= '1';
+ wait until phase1 = '0';
+ A_reg_out_en <= '0';
+ B_reg_out_en <= '0';
+ wait until phase2 = '1';
+ C_reg_load_en <= '1';
+ wait until phase2 = '0';
+ C_reg_load_en <= '0';
+ control_write_back; -- call procedure
+ end procedure control_arith_op;
+
+ -- . . .
+
+ begin
+ -- . . .
+ control_arith_op; -- call procedure
+ -- . . .
+ -- not in book
+ wait;
+ -- end not in book
+ end process control_sequencer;
+
+ -- end code from book
+
+
+ clock_gen : process is
+ begin
+ phase1 <= '1' after 10 ns, '0' after 20 ns;
+ phase2 <= '1' after 30 ns, '0' after 40 ns;
+ wait for 40 ns;
+ end process clock_gen;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd
new file mode 100644
index 000000000..78435f8a1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity do_arith_op is
+end entity do_arith_op;
+
+
+architecture test of do_arith_op is
+
+ type func_code is (add, subtract);
+
+ signal op1 : integer := 10;
+ signal op2 : integer := 3;
+ signal dest : integer := 0;
+ signal func : func_code := add;
+
+ signal Z_flag : boolean := false;
+
+ constant Tpd : delay_length := 3 ns;
+
+begin
+
+ stimulus : process is
+
+ -- code from book
+
+ procedure do_arith_op ( op : in func_code ) is
+ variable result : integer;
+ begin
+ case op is
+ when add =>
+ result := op1 + op2;
+ when subtract =>
+ result := op1 - op2;
+ end case;
+ dest <= result after Tpd;
+ Z_flag <= result = 0 after Tpd;
+ end procedure do_arith_op;
+
+ -- end code from book
+
+ begin
+ wait for 10 ns;
+
+ -- code from book (in text)
+
+ do_arith_op ( add );
+
+ -- end code from book
+
+ wait for 10 ns;
+
+ -- code from book (in text)
+
+ do_arith_op ( func );
+
+ -- end code from book
+
+ wait for 10 ns;
+ do_arith_op ( subtract );
+ wait for 10 ns;
+ op2 <= 10;
+ wait for 10 ns;
+ do_arith_op ( subtract );
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/ent.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/ent.vhd
new file mode 100644
index 000000000..0bebf8a9d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/ent.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+architecture arch of ent is
+
+ type t is . . .;
+
+ signal s : t;
+
+ procedure p1 ( . . . ) is
+ variable v1 : t;
+ begin
+ v1 := s;
+ end procedure p1;
+
+begin -- arch
+
+ proc1 : process is
+
+ variable v2 : t;
+
+ procedure p2 ( . . . ) is
+ variable v3 : t;
+ begin
+ p1 ( v2, v3, . . . );
+ end procedure p2;
+
+ begin -- proc1
+ p2 ( v2, . . . );
+ end process proc1;
+
+ proc2 : process is
+ . . .
+ begin -- proc2
+ p1 ( . . . );
+ end process proc2;
+
+end architecture arch;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/find_first_set.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/find_first_set.vhd
new file mode 100644
index 000000000..a4efe7846
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/find_first_set.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity find_first_set is
+end entity find_first_set;
+
+
+
+architecture test of find_first_set is
+
+ -- code from book
+
+ procedure find_first_set ( v : in bit_vector;
+ found : out boolean;
+ first_set_index : out natural ) is
+ begin
+ for index in v'range loop
+ if v(index) = '1' then
+ found := true;
+ first_set_index := index;
+ return;
+ end if;
+ end loop;
+ found := false;
+ end procedure find_first_set;
+
+ -- end code from book
+
+begin
+
+ stimulus : process is
+
+ -- code from book (in text)
+
+ variable int_req : bit_vector (7 downto 0);
+ variable top_priority : natural;
+ variable int_pending : boolean;
+ -- . . .
+
+ -- end code from book
+
+ constant block_count : natural := 16;
+
+ -- code from book (in text)
+
+ variable free_block_map : bit_vector(0 to block_count-1);
+ variable first_free_block : natural;
+ variable free_block_found : boolean;
+ -- . . .
+
+ -- end code from book
+
+ begin
+ int_req := "00010000";
+
+ -- code from book (in text)
+
+ find_first_set ( int_req, int_pending, top_priority );
+
+ -- end code from book
+
+ free_block_map := (others => '0');
+
+ -- code from book (in text)
+
+ find_first_set ( free_block_map, free_block_found, first_free_block );
+
+ -- end code from book
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/freq_detect.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/freq_detect.vhd
new file mode 100644
index 000000000..e00165758
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/freq_detect.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity freq_detect is
+ port ( terminal input : electrical;
+ terminal freq_out : electrical );
+end entity freq_detect;
+
+----------------------------------------------------------------
+
+architecture threshold_crossing of freq_detect is
+
+ quantity v_in across input to electrical_ref;
+ quantity v_out across i_out through freq_out to electrical_ref;
+ signal freq : real := 0.0;
+ constant threshold : real := 0.0;
+ constant scale_factor : real := 1.0e-6;
+
+begin
+
+ detect: process ( v_in'above(threshold) ) is
+ variable t_previous : real := real'low;
+ begin
+ if v_in > threshold then
+ freq <= scale_factor / ( now - t_previous );
+ t_previous := now;
+ end if;
+ end process detect;
+
+ v_out == freq'ramp(1.0e-9, 1.0e-9);
+
+end threshold_crossing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd
new file mode 100644
index 000000000..c4cd40d53
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity generate_clock is
+end entity generate_clock;
+
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+architecture test of generate_clock is
+
+ -- code from book
+
+ procedure generate_clock ( signal clk : out std_ulogic;
+ constant Tperiod, Tpulse, Tphase : in time ) is
+ begin
+ wait for Tphase;
+ loop
+ clk <= '1', '0' after Tpulse;
+ wait for Tperiod;
+ end loop;
+ end procedure generate_clock;
+
+ -- end code from book
+
+ -- code from book (in text)
+
+ signal phi1, phi2 : std_ulogic := '0';
+ -- . . .
+
+ -- end code from book
+
+begin
+
+ -- code from book (in text)
+
+ gen_phi1 : generate_clock ( phi1, Tperiod => 50 ns, Tpulse => 20 ns,
+ Tphase => 0 ns );
+
+ gen_phi2 : generate_clock ( phi2, Tperiod => 50 ns, Tpulse => 20 ns,
+ Tphase => 25 ns );
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/hold_time_checker.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/hold_time_checker.vhd
new file mode 100644
index 000000000..e20b60bf2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/hold_time_checker.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity hold_time_checker is
+end entity hold_time_checker;
+
+
+
+architecture test of hold_time_checker is
+
+ constant Thold_d_clk : delay_length := 3 ns;
+
+ signal clk, d : bit := '0';
+
+begin
+
+ -- code from book
+
+ hold_time_checker : process ( clk, d ) is
+ variable last_clk_edge_time : time := 0 fs;
+ begin
+ if clk'event and clk = '1' then
+ last_clk_edge_time := now;
+ end if;
+ if d'event then
+ assert now - last_clk_edge_time >= Thold_d_clk
+ report "hold time violation";
+ end if;
+ end process hold_time_checker;
+
+ -- end code from book
+
+ clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+
+ stimulus : d <= '1' after 15 ns,
+ '0' after 53 ns,
+ '1' after 72 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/increment.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/increment.vhd
new file mode 100644
index 000000000..b6aa145db
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/increment.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity increment is
+end entity increment;
+
+
+
+architecture test of increment is
+
+ subtype word32 is bit_vector(31 downto 0);
+
+ -- code from book
+
+ procedure increment ( a : inout word32; by : in word32 := X"0000_0001" ) is
+ variable sum : word32;
+ variable carry : bit := '0';
+ begin
+ for index in a'reverse_range loop
+ sum(index) := a(index) xor by(index) xor carry;
+ carry := ( a(index) and by(index) ) or ( carry and ( a(index) xor by(index) ) );
+ end loop;
+ a := sum;
+ end procedure increment;
+
+ -- end code from book
+
+begin
+
+ stimulus : process is
+
+ variable count : word32 := X"0001_1100";
+
+ begin
+
+ -- code from book (in text)
+
+ increment(count, X"0000_0004");
+
+ increment(count);
+
+ increment(count, by => open);
+
+ -- end code from book
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/index-ams.txt
new file mode 100644
index 000000000..2a966d277
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/index-ams.txt
@@ -0,0 +1,52 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Chapter 9 - Subprograms
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+average_samples.vhd entity average_samples test Figure 9-1
+control_processor.vhd entity control_processor rtl Figure 9-2
+instruction_interpreter.vhd entity instruction_interpreter test Figure 9-3
+control_sequencer.vhd entity control_sequencer test Figure 9-4
+instruction_interpreter-1.vhd entity instruction_interpreter test Figure 9-5
+do_arith_op.vhd entity do_arith_op test Figure 9-6
+addu.vhd entity addu test Figure 9-7
+negate.vhd entity negate test Figure 9-8
+receiver.vhd entity receiver behavioral Figure 9-9
+signal_generator.vhd entity signal_generator top_level Figure 9-10
+increment.vhd entity increment test Figure 9-11
+find_first_set.vhd entity find_first_set test Figure 9-12
+bv_lt.vhd entity bv_lt test Figure 9-13
+check_setup.vhd entity check_setup test Figure 9-14
+generate_clock.vhd entity generate_clock test Figure 9-15
+limited.vhd entity limited test Figure 9-16
+bv_to_natural.vhd entity bv_to_natural test Figure 9-17
+network_driver.vhd entity network_driver test Figure 9-18
+hold_time_checker.vhd entity hold_time_checker test Figure 9-19
+v_source.vhd entity v_source source_sine Figure 9-20
+freq_detect.vhd entity freq_detect threshold_crossing Figure 9-21
+mixer.vhd entity mixer weighted Figure 9-22
+mixer_wa.vhd entity mixer_wa weighted --
+motor_system.vhd entity motor_control_system state_space Figure 9-24
+motor_system_wa.vhd entity motor_control_system_wa simple --
+reg_ctrl.vhd entity reg_ctrl bool_eqn Figure 9-25
+ent.vhd -- arch Figure 9-26
+cache.vhd entity cache behavioral Figure 9-27
+p1.vhd -- -- Figure 9-28
+inline_01.vhd entity inline_01 test Section 9.2
+inline_02.vhd entity inline_02 test Section 9.3
+inline_03.vhd entity inline_03 test Section 9.4
+inline_04a.vhd entity inline_04a test Section 9.4
+inline_05a.vhd entity inline_05a test Section 9.4
+inline_06a.vhd entity inline_06a -- Section 9.4
+inline_07.vhd entity inline_07 test Section 9.6
+inline_08.vhd entity inline_08 test Section 9.6
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
+tb_v_source.vhd entity tb_v_source TB_v_source v_source.vhd
+tb_freq_detect.vhd entity tb_freq_detect TB_freq_detect freq_detect.vhd
+tb_mixer.vhd entity tb_mixer TB_mixer mixer_wa.vhd
+tb_motor_system.vhd entity tb_motor_system TB_motor_system motor_system_wa.vhd
+tb_reg_ctrl.vhd entity tb_reg_ctrl test reg_ctrl.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_01.vhd
new file mode 100644
index 000000000..69a308e5c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_01.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+ process_2_a : process is
+
+ type t1 is (t1_1, t1_2);
+ type t2 is (t2_1, t2_2);
+ type t3 is (t3_1, t3_2);
+ type t4 is (t4_1, t4_2);
+
+ constant v4 : t4 := t4_1;
+
+ constant val1 : t1 := t1_1;
+ constant val2 : t2 := t2_1;
+ variable var3 : t3 := t3_1;
+ constant val4 : t4 := t4_1;
+
+ -- code from book:
+
+ procedure p ( f1 : in t1; f2 : in t2; f3 : out t3; f4 : in t4 := v4 ) is
+ begin
+ -- . . .
+ end procedure p;
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ p ( val1, val2, var3, val4 );
+ p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 );
+ p ( val1, val2, f4 => open, f3 => var3 );
+ p ( val1, val2, var3 );
+
+ -- end of code from book
+
+ wait;
+ end process process_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_02.vhd
new file mode 100644
index 000000000..ac3ece68e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_02.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+
+ constant val1 : integer := 1;
+
+ procedure p ( signal s1, s2 : in bit; val1 : in integer ) is
+ begin
+ null;
+ end procedure p;
+
+begin
+
+
+ block_3_a : block is
+
+ signal s1, s2 : bit;
+
+ begin
+
+ -- code from book:
+
+ call_proc : p ( s1, s2, val1 );
+
+ -- end of code from book
+
+ end block block_3_a;
+
+
+ ----------------
+
+
+ block_3_b : block is
+
+ signal s1, s2 : bit;
+
+ begin
+
+ -- code from book:
+
+ call_proc : process is
+ begin
+ p ( s1, s2, val1 );
+ wait on s1, s2;
+ end process call_proc;
+
+ -- end of code from book
+
+ end block block_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_03.vhd
new file mode 100644
index 000000000..e9570b3c7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_03.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+library ieee; use ieee.numeric_bit.all;
+
+architecture test of inline_03 is
+
+ constant T_delay_adder : delay_length := 10 ns;
+
+ -- code from book:
+
+ function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is
+ begin
+ -- . . .
+ -- not in book
+ return bit_vector(unsigned(bv1) + unsigned(bv2));
+ -- end not in book
+ end function bv_add;
+
+ signal source1, source2, sum : bit_vector(0 to 31);
+
+ -- end of code from book
+
+
+begin
+
+
+ -- code from book:
+
+ adder : sum <= bv_add(source1, source2) after T_delay_adder;
+
+ -- end of code from book
+
+
+ ----------------
+
+
+ stimulus : process is
+ begin
+ wait for 50 ns;
+ source1 <= X"00000002"; source2 <= X"00000003"; wait for 50 ns;
+ source2 <= X"FFFFFFF0"; wait for 50 ns;
+ source1 <= X"00000010"; wait for 50 ns;
+
+ wait;
+ end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_04a.vhd
new file mode 100644
index 000000000..21c42c004
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_04a.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+architecture test of inline_04a is
+
+ -- code from book
+
+ function vector_multiply ( p : real_vector; r : real ) return real_vector is
+ variable result : real_vector(p'range);
+ begin
+ for index in p'range loop
+ result(index) := p(index) * r;
+ end loop;
+ return result;
+ end function vector_multiply;
+
+ --
+
+ quantity scale_factor : real;
+ quantity source_position, scaled_position : real_vector(1 to 3);
+
+ -- end code from book
+
+begin
+
+ -- code from book
+
+ scaled_position == vector_multiply ( source_position, scale_factor );
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_05a.vhd
new file mode 100644
index 000000000..d6eeefc62
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_05a.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_05a is
+
+end entity inline_05a;
+
+
+architecture test of inline_05a is
+
+ function limited ( value, min, max : real ) return real is
+ begin
+ if value > max then
+ return max;
+ elsif value < min then
+ return min;
+ else
+ return value;
+ end if;
+ end function limited;
+
+ quantity v_in, v_amplified : real;
+ constant gain : real := 10.0;
+ constant v_neg : real := -10.0;
+ constant v_pos : real := 10.0;
+
+begin
+
+ -- code from book
+
+ v_amplified == limited ( gain * v_in, v_neg, v_pos );
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_06a.vhd
new file mode 100644
index 000000000..2f50845fb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_06a.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_06a is
+
+ -- code from book:
+
+ impure function now return delay_length;
+
+ -- end of code from book
+
+ impure function now return delay_length is
+ begin
+ return std.standard.now;
+ end function now;
+
+ -- code from book:
+
+ impure function now return real;
+
+ -- end of code from book
+
+ impure function now return real is
+ begin
+ return std.standard.now;
+ end function now;
+
+end entity inline_06a;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd
new file mode 100644
index 000000000..cf99a5b70
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+library ieee; use ieee.numeric_bit.all;
+
+architecture test of inline_07 is
+begin
+
+
+ process_5_a : process is
+
+ -- code from book:
+
+ procedure increment ( a : inout integer; n : in integer := 1 ) is -- . . .
+ -- not in book
+ begin
+ a := a + n;
+ end procedure increment;
+ -- end not in book;
+
+ procedure increment ( a : inout bit_vector; n : in bit_vector := B"1" ) is -- . . .
+ -- not in book
+ begin
+ a := bit_vector(signed(a) + signed(n));
+ end procedure increment;
+ -- end not in book;
+
+ procedure increment ( a : inout bit_vector; n : in integer := 1 ) is -- . . .
+ -- not in book
+ begin
+ a := bit_vector(signed(a) + to_signed(n, a'length));
+ end procedure increment;
+ -- end not in book;
+
+ variable count_int : integer := 2;
+ variable count_bv : bit_vector (15 downto 0) := X"0002";
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ increment ( count_int, 2 );
+ increment ( count_int );
+
+ increment ( count_bv, X"0002");
+ increment ( count_bv, 1 );
+
+ -- increment ( count_bv );
+
+ -- end of code from book
+
+ wait;
+ end process process_5_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_08.vhd
new file mode 100644
index 000000000..01b5eb5ff
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_08.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+library ieee; use ieee.numeric_bit.all;
+
+architecture test of inline_08 is
+begin
+
+
+ process_5_b : process is
+
+ -- code from book:
+
+ function "+" ( left, right : in bit_vector ) return bit_vector is
+ begin
+ -- . . .
+ -- not in book
+ return bit_vector( "+"(signed(left), signed(right)) );
+ -- end not in book
+ end function "+";
+
+ variable addr_reg : bit_vector(31 downto 0);
+ -- . . .
+
+ -- end of code from book
+
+ -- code from book:
+
+ function "abs" ( right : in bit_vector ) return bit_vector is
+ begin
+ -- . . .
+ -- not in book
+ if right(right'left) = '0' then
+ return right;
+ else
+ return bit_vector( "-"(signed(right)) );
+ end if;
+ -- end not in book
+ end function "abs";
+
+ variable accumulator : bit_vector(31 downto 0);
+ -- . . .
+
+ -- end of code from book
+
+ begin
+
+ -- code from book:
+
+ addr_reg := addr_reg + X"0000_0004";
+
+ -- end of code from book
+
+ accumulator := X"000000FF";
+
+ -- code from book:
+
+ accumulator := abs accumulator;
+
+ -- end of code from book
+
+ accumulator := X"FFFFFFFE";
+ accumulator := abs accumulator;
+
+ wait;
+ end process process_5_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter-1.vhd
new file mode 100644
index 000000000..d72fe6463
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter-1.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity instruction_interpreter is
+end entity instruction_interpreter;
+
+
+architecture test of instruction_interpreter is
+
+ subtype word is bit_vector(31 downto 0);
+
+ signal address_bus, data_bus_in : word := X"0000_0000";
+ signal mem_read, mem_request, mem_ready, reset : bit := '0';
+
+begin
+
+ -- code from book
+
+ instruction_interpreter : process is
+
+ -- . . .
+
+ -- not in book
+ variable mem_address_reg, mem_data_reg : word;
+ -- end not in book
+
+ procedure read_memory is
+ begin
+ address_bus <= mem_address_reg;
+ mem_read <= '1';
+ mem_request <= '1';
+ wait until mem_ready = '1' or reset = '1';
+ if reset = '1' then
+ return;
+ end if;
+ mem_data_reg := data_bus_in;
+ mem_request <= '0';
+ wait until mem_ready = '0';
+ end procedure read_memory;
+
+ begin
+ -- . . . -- initialization
+ -- not in book
+ if reset = '1' then
+ wait until reset = '0';
+ end if;
+ -- end not in book
+ loop
+ -- . . .
+ read_memory;
+ exit when reset = '1';
+ -- . . .
+ end loop;
+ end process instruction_interpreter;
+
+ -- end code from book
+
+
+ memory : process is
+ begin
+ wait until mem_request = '1';
+ data_bus_in <= X"1111_1111";
+ mem_ready <= '1' after 10 ns;
+ wait until mem_request = '0';
+ mem_ready <= '0' after 10 ns;
+ end process memory;
+
+ reset <= '1' after 85 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter.vhd
new file mode 100644
index 000000000..594ef76ab
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity instruction_interpreter is
+end entity instruction_interpreter;
+
+
+library ieee; use ieee.numeric_bit.all;
+
+architecture test of instruction_interpreter is
+
+ subtype word is unsigned(31 downto 0);
+
+ signal address_bus, data_bus_in : word := X"0000_0000";
+ signal mem_read, mem_request, mem_ready : bit := '0';
+
+begin
+
+ -- code from book
+
+ instruction_interpreter : process is
+
+ variable mem_address_reg, mem_data_reg,
+ prog_counter, instr_reg, accumulator, index_reg : word;
+ -- . . .
+ -- not in book
+ type opcode_type is (load_mem);
+ constant opcode : opcode_type := load_mem;
+ constant displacement : word := X"0000_0010";
+ -- end not in book
+
+ procedure read_memory is
+ begin
+ address_bus <= mem_address_reg;
+ mem_read <= '1';
+ mem_request <= '1';
+ wait until mem_ready = '1';
+ mem_data_reg := data_bus_in;
+ mem_request <= '0';
+ wait until mem_ready = '0';
+ end procedure read_memory;
+
+ begin
+ -- . . . -- initialization
+ loop
+ -- fetch next instruction
+ mem_address_reg := prog_counter;
+ read_memory; -- call procedure
+ instr_reg := mem_data_reg;
+ -- . . .
+ case opcode is
+ -- . . .
+ when load_mem =>
+ mem_address_reg := index_reg + displacement;
+ read_memory; -- call procedure
+ accumulator := mem_data_reg;
+ -- . . .
+ end case;
+ end loop;
+ end process instruction_interpreter;
+
+ -- end code from book
+
+
+ memory : process is
+ begin
+ wait until mem_request = '1';
+ data_bus_in <= X"1111_1111";
+ mem_ready <= '1';
+ wait until mem_request = '0';
+ mem_ready <= '0';
+ end process memory;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/limited.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/limited.vhd
new file mode 100644
index 000000000..79f9e4319
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/limited.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity limited is
+end entity limited;
+
+
+
+architecture test of limited is
+
+ -- code from book
+
+ function limited ( value, min, max : real ) return real is
+ begin
+ if value > max then
+ return max;
+ elsif value < min then
+ return min;
+ else
+ return value;
+ end if;
+ end function limited;
+
+ -- end code from book
+
+begin
+
+ tester : process is
+
+ variable new_temperature, current_temperature, increment : real;
+ variable new_motor_speed, old_motor_speed,
+ scale_factor, error : real;
+
+ begin
+
+ current_temperature := 75.0;
+ increment := 10.0;
+
+ -- code from book (in text)
+
+ new_temperature := limited ( current_temperature + increment, 10.0, 100.0 );
+
+ -- end code from book
+
+ increment := 60.0;
+ new_temperature := limited ( current_temperature + increment, 10.0, 100.0 );
+ increment := -100.0;
+ new_temperature := limited ( current_temperature + increment, 10.0, 100.0 );
+
+ old_motor_speed := 1000.0;
+ scale_factor := 5.0;
+ error := 5.0;
+
+ -- code from book (in text)
+
+ new_motor_speed := old_motor_speed
+ + scale_factor * limited ( error, -10.0, +10.0 );
+
+ -- end code from book
+
+ error := 15.0;
+ new_motor_speed := old_motor_speed
+ + scale_factor * limited ( error, -10.0, +10.0 );
+
+ error := -20.0;
+ new_motor_speed := old_motor_speed
+ + scale_factor * limited ( error, -10.0, +10.0 );
+
+ wait;
+ end process tester;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer.vhd
new file mode 100644
index 000000000..8dd836961
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity mixer is
+ port ( terminal inputs : electrical_vector(1 to 8);
+ terminal output : electrical );
+end entity mixer;
+
+----------------------------------------------------------------
+
+architecture weighted of mixer is
+
+ quantity v_in across inputs;
+ quantity v_out across i_out through output;
+ constant gains : real_vector(1 to 8)
+ := ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 );
+
+begin
+
+ apply_weights : procedural is
+ variable sum : real := 0.0;
+ begin
+ for index in v_in'range loop
+ sum := sum + v_in(index) * gains(index);
+ end loop;
+ v_out := sum;
+ end procedural apply_weights;
+
+end architecture weighted;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd
new file mode 100644
index 000000000..1f30454ec
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity mixer_wa is
+ port ( terminal inputs : electrical_vector(1 to 8);
+ terminal output : electrical );
+end entity mixer_wa;
+
+----------------------------------------------------------------
+
+architecture weighted of mixer_wa is
+
+ quantity v_in across inputs;
+ quantity v_out across i_out through output;
+ quantity v1, v2, v3, v4, v5, v6, v7, v8 : real;
+ constant gains : real_vector(1 to 8)
+ := ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 );
+
+begin
+
+ v1 == v_in(1) * gains(1);
+ v2 == v_in(2) * gains(2);
+ v3 == v_in(3) * gains(3);
+ v4 == v_in(4) * gains(4);
+ v5 == v_in(5) * gains(5);
+ v6 == v_in(6) * gains(6);
+ v7 == v_in(7) * gains(7);
+ v8 == v_in(8) * gains(8);
+
+ v_out == v1 + v2 + v3 + v4 + v5 + v6 + v7 + v8;
+
+end architecture weighted;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd
new file mode 100644
index 000000000..42f4d0fc8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity motor_system is
+ port ( terminal vp, vm : electrical;
+ terminal px : electrical_vector(1 to 3) );
+end entity motor_system;
+
+----------------------------------------------------------------
+
+architecture state_space of motor_system is
+
+ quantity v_in across vp to vm;
+ quantity x across i_x through px to electrical_ref;
+ constant Tfb : real := 0.001;
+ constant Kfb : real := 1.0;
+ constant Te : real := 0.001;
+ constant Ke : real := 1.0;
+ constant Tm : real := 0.1;
+ constant Km : real := 1.0;
+
+ type real_matrix is array (1 to 3, 1 to 3) of real;
+ constant c : real_matrix := ( ( -1.0/Tfb, 0.0, Kfb/Tfb ),
+ ( -Ke/Te, -1.0/Te, 0.0 ),
+ ( 0.0, Km/Tm, -1.0/Tm ) );
+
+begin
+
+ state_eqn : procedural is
+ variable sum : real_vector(1 to 3) := (0.0, 0.0, 0.0);
+ begin
+ for i in 1 to 3 loop
+ for j in 1 to 3 loop
+ sum(i) := sum(i) + c(i, j) * x(j);
+ end loop;
+ end loop;
+ x(1)'dot := sum(1);
+ x(2)'dot := sum(2) + (Ke/Te)*v_in;
+ x(3)'dot := sum(3);
+ end procedural state_eqn;
+
+end architecture state_space;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system_wa.vhd
new file mode 100644
index 000000000..90c6110da
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system_wa.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity motor_system_wa is
+ port ( terminal vp, vm, px1, px2, px3 : electrical); -- 2 inputs, 3 outputs
+end entity motor_system_wa;
+
+----------------------------------------------------------------
+
+architecture simple of motor_system_wa is
+
+ quantity v_in across vp to vm; -- Inout voltage/Current
+ quantity x1 across ix1 through px1 to electrical_ref;
+ quantity x2 across ix2 through px2 to electrical_ref;
+ quantity x3 across ix3 through px3 to electrical_ref;
+ constant Tfb : real := 0.001;
+ constant Kfb : real := 1.0;
+ constant Te : real := 0.001;
+ constant Ke : real := 1.0;
+ constant Tm : real := 0.1;
+ constant Km : real := 1.0;
+ constant c11 : real := -1.0/Tfb;
+ constant c12 : real := 0.0;
+ constant c13 : real := Kfb/Tfb;
+ constant c21 : real := -Ke/Te;
+ constant c22 : real := -1.0/Te;
+ constant c23 : real := 0.0;
+ constant c31 : real := 0.0;
+ constant c32 : real := Km/Tm;
+ constant c33 : real := -1.0/Tm;
+
+begin -- architecture simple
+
+ x1'dot == c11*x1 + c12*x2 + c13*x3;
+ x2'dot == c21*x1 + c22*x2 + c23*x3 + (Ke/Te)*v_in;
+ x3'dot == c31*x1 + c32*x2 + c33*x3;
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd
new file mode 100644
index 000000000..8c10cf0d7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity negate is
+end entity negate;
+
+
+architecture test of negate is
+
+ subtype word32 is bit_vector(31 downto 0);
+
+ -- code in book
+
+ procedure negate ( a : inout word32 ) is
+ variable carry_in : bit := '1';
+ variable carry_out : bit;
+ begin
+ a := not a;
+ for index in a'reverse_range loop
+ carry_out := a(index) and carry_in;
+ a(index) := a(index) xor carry_in;
+ carry_in := carry_out;
+ end loop;
+ end procedure negate;
+
+ -- end code in book
+
+begin
+
+ stimulus : process is
+
+ -- code in book (in text)
+
+ variable op1 : word32;
+ -- . . .
+
+ -- end code in book
+
+ begin
+ op1 := X"0000_0002";
+
+ -- code in book (in text)
+
+ negate ( op1 );
+
+ -- end code in book
+
+ wait;
+ end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd
new file mode 100644
index 000000000..02461c8d0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity network_driver is
+end entity network_driver;
+
+
+architecture test of network_driver is
+
+ constant target_host_id : natural := 10;
+ constant my_host_id : natural := 5;
+ type pkt_types is (control_pkt, other_pkt);
+ type pkt_header is record
+ dest, src : natural;
+ pkt_type : pkt_types;
+ seq : natural;
+ end record;
+
+begin
+
+ -- code from book
+
+ network_driver : process is
+
+ constant seq_modulo : natural := 2**5;
+ subtype seq_number is natural range 0 to seq_modulo-1;
+ variable next_seq_number : seq_number := 0;
+ -- . . .
+ -- not in book
+ variable new_header : pkt_header;
+ -- end not in book
+
+ impure function generate_seq_number return seq_number is
+ variable number : seq_number;
+ begin
+ number := next_seq_number;
+ next_seq_number := (next_seq_number + 1) mod seq_modulo;
+ return number;
+ end function generate_seq_number;
+
+ begin -- network_driver
+ -- not in book
+ wait for 10 ns;
+ -- end not in book
+ -- . . .
+ new_header := pkt_header'( dest => target_host_id,
+ src => my_host_id,
+ pkt_type => control_pkt,
+ seq => generate_seq_number );
+ -- . . .
+ end process network_driver;
+
+ -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/p1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/p1.vhd
new file mode 100644
index 000000000..22627f9d8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/p1.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+procedure p1 is
+
+ variable v : integer;
+
+ procedure p2 is
+ variable v : integer;
+ begin -- p2
+ . . .
+ v := v + 1;
+ . . .
+ end procedure p2;
+
+begin -- p1
+ . . .
+ v := 2 * v;
+ . . .
+end procedure p1;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd
new file mode 100644
index 000000000..0c8a0b1eb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity receiver is
+end entity receiver;
+
+
+-- code from book
+
+architecture behavioral of receiver is
+
+ -- . . . -- type declarations, etc
+
+ -- not in book
+
+ subtype packet_index_range is integer range 1 to 8;
+ type packet_array is array (packet_index_range) of bit;
+
+ -- end not in book
+
+ signal recovered_data : bit;
+ signal recovered_clock : bit;
+ -- . . .
+
+ procedure receive_packet ( signal rx_data : in bit;
+ signal rx_clock : in bit;
+ data_buffer : out packet_array ) is
+ begin
+ for index in packet_index_range loop
+ wait until rx_clock = '1';
+ data_buffer(index) := rx_data;
+ end loop;
+ end procedure receive_packet;
+
+begin
+
+ packet_assembler : process is
+ variable packet : packet_array;
+ begin
+ -- . . .
+ receive_packet ( recovered_data, recovered_clock, packet );
+ -- . . .
+ end process packet_assembler;
+
+ -- . . .
+
+
+ -- not in book
+
+ data_generator : recovered_data <= '1' after 5 ns,
+ '0' after 15 ns,
+ '1' after 25 ns,
+ '0' after 35 ns,
+ '0' after 45 ns,
+ '1' after 55 ns,
+ '0' after 65 ns,
+ '1' after 75 ns;
+
+ clock_generator : process is
+ begin
+ recovered_clock <= '0' after 2 ns, '1' after 10 ns;
+ wait for 10 ns;
+ end process clock_generator;
+
+ -- end not in book
+
+end architecture behavioral;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/reg_ctrl.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/reg_ctrl.vhd
new file mode 100644
index 000000000..8d9c884e5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/reg_ctrl.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity reg_ctrl is
+ port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
+ reg_rd, reg_wr : out std_ulogic );
+end entity reg_ctrl;
+
+--------------------------------------------------
+
+architecture bool_eqn of reg_ctrl is
+begin
+
+ rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
+
+ rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
+ and not cpu_clk;
+
+end architecture bool_eqn;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/signal_generator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/signal_generator.vhd
new file mode 100644
index 000000000..b61730f6c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/signal_generator.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- not in book
+
+entity signal_generator is
+ generic ( period : delay_length := 20 ns;
+ pulse_count : natural := 5 );
+end entity signal_generator;
+
+-- end not in book
+
+
+library ieee; use ieee.std_logic_1164.all;
+
+architecture top_level of signal_generator is
+
+ signal raw_signal : std_ulogic;
+ -- . . .
+
+ procedure generate_pulse_train ( width, separation : in delay_length;
+ number : in natural;
+ signal s : out std_ulogic ) is
+ begin
+ for count in 1 to number loop
+ s <= '1', '0' after width;
+ wait for width + separation;
+ end loop;
+ end procedure generate_pulse_train;
+
+begin
+
+ raw_signal_generator : process is
+ begin
+ -- . . .
+ generate_pulse_train ( width => period / 2,
+ separation => period - period / 2,
+ number => pulse_count,
+ s => raw_signal );
+ -- . . .
+ -- not in book
+ wait;
+ -- end not in book
+ end process raw_signal_generator;
+
+ -- . . .
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd
new file mode 100644
index 000000000..2715117e3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_freq_detect is
+
+end tb_freq_detect;
+
+architecture TB_freq_detect of tb_freq_detect is
+ terminal in_src, freq_out : electrical;
+ -- Component declarations
+ -- Signal declarations
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_sine(ideal)
+ generic map(
+ freq => 200.0,
+ amplitude => 5.0
+ )
+ port map(
+ pos => in_src,
+ neg => ELECTRICAL_REF
+ );
+
+ freq1 : entity work.freq_detect(threshold_crossing)
+ port map(
+ input => in_src,
+ freq_out => freq_out
+ );
+end TB_freq_detect;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd
new file mode 100644
index 000000000..e0526b02d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_mixer is
+end tb_mixer;
+
+architecture TB_mixer of tb_mixer is
+ -- Component declarations
+ -- Signal declarations
+ terminal mix_in : electrical_vector(1 to 8);
+ terminal pseudo_gnd : electrical;
+begin
+ -- Signal assignments
+ -- Component instances
+ v3 : entity work.v_sine(ideal)
+ generic map(
+ amplitude => 5.0,
+ freq => 1.0e3
+ )
+ port map(
+ pos => mix_in(7),
+ neg => ELECTRICAL_REF
+ );
+ v4 : entity work.v_sine(ideal)
+ generic map(
+ amplitude => 4.0,
+ freq => 2.0e3
+ )
+ port map(
+ pos => mix_in(8),
+ neg => ELECTRICAL_REF
+ );
+ v9 : entity work.v_sine(ideal)
+ generic map(
+ freq => 1.0e3,
+ amplitude => 5.0
+ )
+ port map(
+ pos => mix_in(5),
+ neg => ELECTRICAL_REF
+ );
+ v10 : entity work.v_sine(ideal)
+ generic map(
+ freq => 2.0e3,
+ amplitude => 4.0
+ )
+ port map(
+ pos => mix_in(6),
+ neg => ELECTRICAL_REF
+ );
+ R2 : entity work.resistor(ideal)
+ generic map(
+ res => 1.0e3
+ )
+ port map(
+ p1 => pseudo_gnd,
+ p2 => ELECTRICAL_REF
+ );
+ mixer1 : entity work.mixer_wa(weighted)
+ port map(
+ inputs => mix_in,
+ output => pseudo_gnd
+ );
+ v14 : entity work.v_sine(ideal)
+ generic map(
+ amplitude => 4.0,
+ freq => 2.0e3
+ )
+ port map(
+ pos => mix_in(2),
+ neg => ELECTRICAL_REF
+ );
+ v15 : entity work.v_sine(ideal)
+ generic map(
+ amplitude => 5.0,
+ freq => 1.0e3
+ )
+ port map(
+ pos => mix_in(1),
+ neg => ELECTRICAL_REF
+ );
+ v16 : entity work.v_sine(ideal)
+ generic map(
+ freq => 2.0e3,
+ amplitude => 4.0
+ )
+ port map(
+ pos => mix_in(4),
+ neg => ELECTRICAL_REF
+ );
+ v17 : entity work.v_sine(ideal)
+ generic map(
+ freq => 1.0e3,
+ amplitude => 5.0
+ )
+ port map(
+ pos => mix_in(3),
+ neg => ELECTRICAL_REF
+ );
+end TB_mixer;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd
new file mode 100644
index 000000000..77fc0d49e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_motor_system is
+end tb_motor_system ;
+
+architecture TB_motor_system of tb_motor_system is
+ -- Component declarations
+ -- Signal declarations
+ terminal in_src, x1_out, x2_out, x3_out : electrical;
+
+begin
+ v7 : entity work.v_sine(ideal)
+ generic map(
+ freq => 10.0,
+ amplitude => 1.0
+ )
+ port map(
+ pos => in_src,
+ neg => electrical_ref
+ );
+ state_var1: entity work.motor_system_wa(simple)
+ port map(
+ vp => in_src,
+ vm => ELECTRICAL_REF,
+ px1 => x1_out,
+ px2 => x2_out,
+ px3 => x3_out
+ );
+end TB_motor_system ;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_reg_ctrl.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_reg_ctrl.vhd
new file mode 100644
index 000000000..c08db00fb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_reg_ctrl.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity tb_reg_ctrl is
+end entity tb_reg_ctrl;
+
+
+
+library ieee; use ieee.std_logic_1164.all;
+library util;
+
+architecture test of tb_reg_ctrl is
+
+ signal reg_addr_decoded, rd, wr, io_en,
+ cpu_clk, reg_rd, reg_wr : std_ulogic := '0';
+ signal test_vector : std_ulogic_vector(1 to 5);
+
+ use util.stimulus_generators.all;
+
+begin
+
+ dut : entity work.reg_ctrl
+ port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr );
+
+ stimulus : process is
+ begin
+ all_possible_values( bv => test_vector,
+ delay_between_values => 10 ns );
+ wait;
+ end process stimulus;
+
+ (reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd
new file mode 100644
index 000000000..e509b5584
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_v_source is
+
+end tb_v_source ;
+
+architecture TB_v_source of tb_v_source is
+ terminal in_src, out_flt : electrical;
+ -- Component declarations
+ -- Signal declarations
+begin
+ -- Signal assignments
+ -- Component instances
+ vio : entity work.v_source(source_sine)
+ port map(
+ p => in_src,
+ m => ELECTRICAL_REF
+ );
+
+ R1 : entity work.resistor(ideal)
+ generic map(
+ res => 10.0e3
+ )
+ port map(
+ p1 => in_src,
+ p2 => electrical_ref
+ );
+end TB_v_source ;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/v_source.vhd
new file mode 100644
index 000000000..845d65ca7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/v_source.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+library ieee; use ieee.math_real.all;
+
+entity v_source is
+ port ( terminal p, m : electrical );
+end entity v_source;
+
+----------------------------------------------------------------
+
+architecture source_sine of v_source is
+ constant ampl : real := 1.0;
+ constant freq : real := 60.0;
+ quantity v across i through p to m;
+begin
+ v == ampl * sin(2.0 * math_pi * freq * now);
+end architecture source_sine;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/clock_duty.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/clock_duty.vhd
new file mode 100644
index 000000000..6538cb3a2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/clock_duty.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- This digital clock allows user to specify the duty cycle using
+-- the parameters "on_time" and "off_time"
+
+library ieee; use ieee.std_logic_1164.all;
+
+entity clock_duty is
+
+ generic ( on_time : time := 20 us;
+ off_time : time := 19.98 ms );
+
+ port ( clock_out : out std_logic := 'Z' );
+
+end entity clock_duty;
+
+
+architecture ideal of clock_duty is
+
+begin
+
+ process
+ begin
+ wait for 1 us;
+ clock_out <= '1';
+ wait for on_time;
+ clock_out <= '0';
+ wait for off_time;
+ end process;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/gain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/gain.vhd
new file mode 100644
index 000000000..3c3af8628
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/gain.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity gain is
+ generic ( k : real := 1.0 ); -- gain multiplier
+ port ( quantity input : in real;
+ quantity output : out real);
+end entity gain;
+
+architecture simple of gain is
+begin
+ output == k * input;
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/util/index-ams.txt
new file mode 100644
index 000000000..4e4d37774
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/index-ams.txt
@@ -0,0 +1,18 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Utilities
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Figure/Section
+----------- ------------ -------------- --------------
+clock_duty.vhd entity clock_duty ideal
+gain.vhd entity gain simple
+resistor.vhd entity resistor ideal
+src_constant.vhd entity src_constant ideal
+src_pulse.vhd entity src_pulse ideal
+src_sine.vhd entity src_sine ideal
+sum2.vhd entity sum2 simple
+stimulus_generators.vhd package stimulus_generators body
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename Primary Unit Secondary Unit Tested Model
+------------ ------------ -------------- ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/resistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/resistor.vhd
new file mode 100644
index 000000000..43d276597
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/resistor.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+ port ( terminal p1, p2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+ quantity v across i through p1 to p2;
+ constant resistance : real := 10000.0;
+begin
+ v == i * resistance;
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_constant.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_constant.vhd
new file mode 100644
index 000000000..e7eb720ad
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_constant.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- Voltage Pulse Source (Includes Frequency Domain settings)
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity src_constant is
+
+ generic ( level : real := 1.0; -- Constant output value (V)
+ ac_mag : real := 1.0; -- AC magnitude
+ ac_phase : real := 0.0 ); -- AC phase (degrees)
+
+ port ( quantity output : out real );
+
+end entity src_constant;
+
+
+architecture ideal of src_constant is
+
+ -- Declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi * ac_phase / 360.0;
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+ output == level;
+ else
+ output == ac_spec; -- used for frequency (AC) analysis
+ end use;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_pulse.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_pulse.vhd
new file mode 100644
index 000000000..ba3c72fe3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_pulse.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- Voltage Pulse Source (Includes Frequency Domain settings)
+
+library ieee; use ieee.math_real.all;
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity src_pulse is
+
+ generic ( initial : real := 0.0; -- initial value
+ pulse : real; -- pulsed value
+ ti2p : real; -- transition time - initial to pulse
+ tp2i : real; -- transition time - pulse to initial
+ delay : time := 0ms; -- delay time
+ width : time; -- duration of pulse (includes ti2p)
+ period : time; -- period
+ ac_mag : real := 1.0; -- AC magnitude
+ ac_phase : real := 0.0 ); -- AC phase (degrees)
+
+ port ( quantity output : out real );
+
+end entity src_pulse;
+
+
+architecture ideal of src_pulse is
+
+ -- Declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi * ac_phase / 360.0;
+
+ -- Signal and constant used in process below
+ signal pulse_signal : real := initial;
+ constant low_width: time := period - width;
+
+begin
+
+ if domain = quiescent_domain or domain = time_domain use
+ output == pulse_signal'ramp(ti2p, tp2i);
+ else
+ output == ac_spec; -- used for frequency (AC) analysis
+ end use;
+
+ -- Process to create events on pulse_signal used for rise and fall edges
+ proc1 : process
+ begin
+ wait for delay;
+ loop
+ pulse_signal <= pulse;
+ wait for width;
+ pulse_signal <= initial;
+ wait for low_width;
+ end loop;
+ end process;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_sine.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_sine.vhd
new file mode 100644
index 000000000..f5b82c839
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_sine.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library IEEE; use IEEE.MATH_REAL.all;
+library IEEE_proposed; use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity src_sine is
+
+ generic ( freq : real; -- frequency [Hertz]
+ amplitude : voltage; -- amplitude [Volts]
+ phase : real := 0.0; -- initial phase [Degrees]
+ offset : voltage := 0.0; -- DC value [Volts]
+ df : real := 0.0; -- damping factor [1/second]
+ ac_mag : voltage := 1.0; -- AC magnitude [Volts]
+ ac_phase : real := 0.0); -- AC phase [Degrees]
+
+ port ( quantity output : out real );
+
+end entity src_sine;
+
+
+architecture ideal of src_sine is
+
+ -- Declare quantity for phase in radians (calculated below)
+ quantity phase_rad : real;
+ -- Declare quantity in frequency domain for AC analysis
+ quantity ac_spec : real spectrum ac_mag, math_2_pi * ac_phase / 360.0;
+
+begin
+
+ -- Convert phase to radians
+ phase_rad == math_2_pi *(freq * now + phase / 360.0);
+
+ if domain = quiescent_domain or domain = time_domain use
+ output == offset + amplitude * sin(phase_rad) * exp(-now * df);
+ else
+ output == ac_spec; -- used for Frequency (AC) analysis
+ end use;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd
new file mode 100644
index 000000000..a5cdc0ae0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee; use ieee.std_logic_1164.all;
+
+package stimulus_generators is
+
+ procedure all_possible_values ( signal bv : out bit_vector;
+ delay_between_values : in delay_length );
+
+ procedure all_possible_values ( signal bv : out std_ulogic_vector;
+ delay_between_values : in delay_length );
+
+ procedure all_possible_values ( signal bv : out std_logic_vector;
+ delay_between_values : in delay_length );
+
+end package stimulus_generators;
+
+
+
+package body stimulus_generators is
+
+ type digit_table is array ( natural range 0 to 1 ) of bit;
+ constant digit : digit_table := ( '0', '1' );
+
+
+ function natural_to_bv ( nat : in natural;
+ length : in natural ) return bit_vector is
+
+ variable temp : natural := nat;
+ variable result : bit_vector(0 to length - 1);
+
+ begin
+ for index in result'reverse_range loop
+ result(index) := digit( temp rem 2 );
+ temp := temp / 2;
+ end loop;
+ return result;
+ end function natural_to_bv;
+
+
+ procedure all_possible_values ( signal bv : out bit_vector;
+ delay_between_values : in delay_length ) is
+ begin
+ bv <= natural_to_bv(0, bv'length);
+ for value in 1 to 2**bv'length - 1 loop
+ wait for delay_between_values;
+ bv <= natural_to_bv(value, bv'length);
+ end loop;
+ end procedure all_possible_values;
+
+
+ procedure all_possible_values ( signal bv : out std_ulogic_vector;
+ delay_between_values : in delay_length ) is
+ begin
+ bv <= To_StdULogicVector(natural_to_bv(0, bv'length));
+ for value in 1 to 2**bv'length - 1 loop
+ wait for delay_between_values;
+ bv <= To_StdULogicVector(natural_to_bv(value, bv'length));
+ end loop;
+ end procedure all_possible_values;
+
+
+ procedure all_possible_values ( signal bv : out std_logic_vector;
+ delay_between_values : in delay_length ) is
+ begin
+ bv <= To_StdLogicVector(natural_to_bv(0, bv'length));
+ for value in 1 to 2**bv'length - 1 loop
+ wait for delay_between_values;
+ bv <= To_StdLogicVector(natural_to_bv(value, bv'length));
+ end loop;
+ end procedure all_possible_values;
+
+end package body stimulus_generators;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/sum2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/sum2.vhd
new file mode 100644
index 000000000..614f4095a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/sum2.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version.
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity sum2 is
+ generic ( k1, k2 : real := 1.0 ); -- Optional gain multipliers
+ port ( quantity in1, in2 : in real; -- Input quantity ports
+ quantity output : out real ); -- Output quantity port
+end entity sum2;
+
+architecture simple of sum2 is
+begin
+ output == k1 * in1 + k2 * in2; -- Sum of inputs (with optional gain)
+end architecture simple;