blob: c961c88371b822e122da51d38320b90a5df0b4f2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity cpu is
end entity cpu;
-- end not in book
architecture behavioral of cpu is
begin
interpreter : process is
variable instr_reg : work.cpu_types.word;
variable instr_opcode : work.cpu_types.opcode;
begin
-- . . . -- initialize
loop
-- . . . -- fetch instruction
instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
case instr_opcode is
when work.cpu_types.op_nop => null;
when work.cpu_types.op_breq => -- . . .
-- . . .
-- not in book
when others => null;
-- end not in book
end case;
end loop;
end process interpreter;
end architecture behavioral;
|
