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-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
package byte_swap_types is
subtype halfword is bit_vector(0 to 15);
end package byte_swap_types;
use work.byte_swap_types.all;
-- end not in book:
entity byte_swap is
port (input : in halfword; output : out halfword);
end entity byte_swap;
--------------------------------------------------
architecture behavior of byte_swap is
begin
swap : process (input)
begin
output(8 to 15) <= input(0 to 7);
output(0 to 7) <= input(8 to 15);
end process swap;
end architecture behavior;
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