| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | Execute techmap and arith_map simultaneously | Eddie Hung | 2019-06-03 | 1 | -6/+6 | |
| * | | | Typo | Eddie Hung | 2019-06-03 | 1 | -1/+1 | |
| * | | | IS_C_INVERTED | Eddie Hung | 2019-06-03 | 1 | -4/+4 | |
| * | | | Fix `ifndef | Eddie Hung | 2019-06-03 | 1 | -1/+1 | |
| * | | | Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) | Eddie Hung | 2019-06-03 | 4 | -8/+8 | |
| * | | | Ooopsie | Eddie Hung | 2019-06-03 | 1 | -1/+1 | |
| * | | | Consistent with xilinx | Eddie Hung | 2019-06-03 | 3 | -4/+4 | |
| * | | | Add flops as blackboxes | Eddie Hung | 2019-05-31 | 2 | -0/+27 | |
| * | | | Add FD*E_1 -> FD*E techmap rules | Eddie Hung | 2019-05-31 | 1 | -5/+31 | |
| * | | | Techmap flops before ABC again | Eddie Hung | 2019-05-31 | 1 | -4/+4 | |
| * | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-05-31 | 2 | -1/+2 | |
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| | * | | | Use nonblocking | Eddie Hung | 2019-04-23 | 1 | -1/+1 | |
| | * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 6 | -36/+222 | |
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| * | | | | | Remove whitebox attribute from DRAMs for now | Eddie Hung | 2019-05-30 | 1 | -2/+2 | |
| * | | | | | Carry in/out to be the last input/output for chains to be preserved | Eddie Hung | 2019-05-30 | 2 | -12/+15 | |
| * | | | | | Some more realistic delays... | Eddie Hung | 2019-05-29 | 1 | -7/+7 | |
| * | | | | | Typo | Eddie Hung | 2019-05-28 | 1 | -1/+1 | |
| * | | | | | Make MUXF{7,8} and CARRY4 whitebox | Eddie Hung | 2019-05-27 | 1 | -3/+3 | |
| * | | | | | Re-enable lib_whitebox | Eddie Hung | 2019-05-27 | 1 | -5/+5 | |
| * | | | | | Blackboxes | Eddie Hung | 2019-05-26 | 2 | -10/+10 | |
| * | | | | | Muck about with LUT delays some more | Eddie Hung | 2019-05-26 | 1 | -5/+5 | |
| * | | | | | Try new LUT delays | Eddie Hung | 2019-05-24 | 1 | -8/+11 | |
| * | | | | | Transpose CARRY4 delays | Eddie Hung | 2019-05-24 | 1 | -10/+8 | |
| * | | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-23 | 1 | -0/+4 | |
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| | * | | | | Add "min bits" and "min wports" to xilinx dram rules | Eddie Hung | 2019-05-23 | 1 | -0/+4 | |
| * | | | | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux | Eddie Hung | 2019-05-23 | 1 | -2/+4 | |
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| | * | | | | Add "wreduce -keepdc", fixes #1016 | Clifford Wolf | 2019-05-20 | 1 | -2/+4 | |
| * | | | | | Add whitebox support to DRAM | Eddie Hung | 2019-05-23 | 5 | -24/+26 | |
| * | | | | | shift register inference before mux | Eddie Hung | 2019-05-22 | 1 | -3/+3 | |
| * | | | | | Fix/workaround symptom unveiled by #1023 | Eddie Hung | 2019-05-21 | 1 | -4/+14 | |
| * | | | | | Instead of MUXCY/XORCY use CARRY4 (with timing) | Eddie Hung | 2019-05-21 | 4 | -11/+20 | |
| * | | | | | Modify LUT area cost to be same as old abc | Eddie Hung | 2019-05-21 | 1 | -10/+9 | |
| * | | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-21 | 5 | -230/+421 | |
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| | * | | | | ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC | Sylvain Munaut | 2019-05-13 | 1 | -0/+11 | |
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| | * | | | Add "stat -tech xilinx" | Clifford Wolf | 2019-05-11 | 1 | -1/+1 | |
| | * | | | Fix formatting for synth_intel.cc | Ben Widawsky | 2019-05-09 | 1 | -222/+211 | |
| | * | | | Add "synth_xilinx -arch" | Clifford Wolf | 2019-05-07 | 1 | -1/+13 | |
| | * | | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 6 | -178/+124 | |
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| | | * | | | Rename cells_map.v to prevent clash with ff_map.v | Eddie Hung | 2019-05-03 | 1 | -6/+8 | |
| | | * | | | Merge pull request #969 from YosysHQ/clifford/pmgenstuff | Clifford Wolf | 2019-05-03 | 2 | -0/+4 | |
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| | * | | | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -2/+2 | |
| | * | | | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -3/+4 | |
| | * | | | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -0/+28 | |
| | * | | | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -70/+70 | |
| | * | | | | | Add $specify2 and $specify3 cells to simlib | Clifford Wolf | 2019-04-23 | 1 | -0/+147 | |
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| * | | | | | Trim off leading 1'bx in A | Eddie Hung | 2019-05-02 | 1 | -7/+20 | |
| * | | | | | Add don't care optimisation | Eddie Hung | 2019-05-02 | 1 | -0/+11 | |
| * | | | | | Use new peepopt from #969 | Eddie Hung | 2019-05-02 | 1 | -10/+15 | |
| * | | | | | Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux | Eddie Hung | 2019-05-02 | 2 | -0/+4 | |
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| | * | | | | Run "peepopt" in generic "synth" pass and "synth_ice40" | Clifford Wolf | 2019-04-30 | 2 | -0/+4 | |
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