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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 12:37:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 12:37:02 -0700 |
| commit | ebcc85b9b86267a25e9126aa3d82ef4a0bd9f6fd (patch) | |
| tree | 70386fbf8d99910ffb6a68893298fb7404a39edf /techlibs | |
| parent | 00927703177d01ad27559aad827b72068b80b12a (diff) | |
| download | yosys-ebcc85b9b86267a25e9126aa3d82ef4a0bd9f6fd.tar.gz yosys-ebcc85b9b86267a25e9126aa3d82ef4a0bd9f6fd.tar.bz2 yosys-ebcc85b9b86267a25e9126aa3d82ef4a0bd9f6fd.zip | |
Fix `ifndef
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index cce03980d..c8450f8d1 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -246,8 +246,8 @@ module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; - generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) `ifndef _ABC + generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; |